1 // SPDX-License-Identifier: GPL-2.0-only
3  *  Support for C64x+ Megamodule Interrupt Controller
9 #include <linux/interrupt.h>
16 #include <asm/megamod-pic.h>
24  * Megamodule Interrupt Controller register layout
68 	irq_hw_number_t src = irqd_to_hwirq(data);  in mask_megamod()  local
69 	u32 __iomem *evtmask = &pic->regs->evtmask[src / 32];  in mask_megamod()
71 	raw_spin_lock(&pic->lock);  in mask_megamod()
72 	soc_writel(soc_readl(evtmask) | (1 << (src & 31)), evtmask);  in mask_megamod()
73 	raw_spin_unlock(&pic->lock);  in mask_megamod()
79 	irq_hw_number_t src = irqd_to_hwirq(data);  in unmask_megamod()  local
80 	u32 __iomem *evtmask = &pic->regs->evtmask[src / 32];  in unmask_megamod()
82 	raw_spin_lock(&pic->lock);  in unmask_megamod()
83 	soc_writel(soc_readl(evtmask) & ~(1 << (src & 31)), evtmask);  in unmask_megamod()
84 	raw_spin_unlock(&pic->lock);  in unmask_megamod()
103 	pic = cascade->pic;  in megamod_irq_cascade()
104 	idx = cascade->index;  in megamod_irq_cascade()
106 	while ((events = soc_readl(&pic->regs->mevtflag[idx])) != 0) {  in megamod_irq_cascade()
109 		irq = irq_linear_revmap(pic->irqhost, idx * 32 + n);  in megamod_irq_cascade()
111 		soc_writel(1 << n, &pic->regs->evtclr[idx]);  in megamod_irq_cascade()
120 	struct megamod_pic *pic = h->host_data;  in megamod_map()
125 		if (pic->output_to_irq[i] == hw)  in megamod_map()
126 			return -1;  in megamod_map()
142 static void __init set_megamod_mux(struct megamod_pic *pic, int src, int output)  in set_megamod_mux()  argument
147 	if (src < 0 || src >= (NR_COMBINERS * 32)) {  in set_megamod_mux()
148 		pic->output_to_irq[output] = IRQ_UNMAPPED;  in set_megamod_mux()
156 	val = soc_readl(&pic->regs->intmux[index]);  in set_megamod_mux()
158 	val |= src << offset;  in set_megamod_mux()
159 	soc_writel(val, &pic->regs->intmux[index]);  in set_megamod_mux()
166  * interrupt. The value of a given cell is the megamodule interrupt source
170  * values are 4 - ((NR_COMBINERS * 32) - 1). Note that the combined interrupt
171  * sources (0 - 3) are not allowed to be mapped through this property. They
178 	struct device_node *np = irq_domain_get_of_node(pic->irqhost);  in parse_priority_map()
183 	map = of_get_property(np, "ti,c64x+megamod-pic-mux", &maplen);  in parse_priority_map()
212 	pic->irqhost = irq_domain_add_linear(np, NR_COMBINERS * 32,  in init_megamod_pic()
214 	if (!pic->irqhost) {  in init_megamod_pic()
219 	pic->irqhost->host_data = pic;  in init_megamod_pic()
221 	raw_spin_lock_init(&pic->lock);  in init_megamod_pic()
223 	pic->regs = of_iomap(np, 0);  in init_megamod_pic()
224 	if (!pic->regs) {  in init_megamod_pic()
237 	 * These cascades can be from the combined interrupt sources or for  in init_megamod_pic()
238 	 * individual interrupt sources. The "interrupts" property only  in init_megamod_pic()
241 	 * as their interrupt parent.  in init_megamod_pic()
253 			pr_err("%pOF: combiner-%d no irq_data for virq %d!\n",  in init_megamod_pic()
258 		hwirq = irq_data->hwirq;  in init_megamod_pic()
262 		 * of the core priority interrupts (4 - 15).  in init_megamod_pic()
265 			pr_err("%pOF: combiner-%d core irq %ld out of range!\n",  in init_megamod_pic()
271 		mapping[hwirq - 4] = i;  in init_megamod_pic()
273 		pr_debug("%pOF: combiner-%d cascading to hwirq %ld\n",  in init_megamod_pic()
280 		soc_writel(~0, &pic->regs->evtmask[i]);  in init_megamod_pic()
281 		soc_writel(~0, &pic->regs->evtclr[i]);  in init_megamod_pic()
306  * Return -1 if no events active.
314 		mask = soc_readl(&mm_pic->regs->mexpflag[i]);  in get_exception()
317 			soc_writel(1 << bit, &mm_pic->regs->evtclr[i]);  in get_exception()
321 	return -1;  in get_exception()
326 	soc_writel(val, &mm_pic->regs->evtasrt);  in assert_event()
333 	np = of_find_compatible_node(NULL, NULL, "ti,c64x+megamod-pic");  in megamod_pic_init()