Lines Matching +full:config +full:- +full:space

1 # SPDX-License-Identifier: GPL-2.0-only
4 config CPU_BIG_ENDIAN
7 config CPU_LITTLE_ENDIAN
11 config FPU
15 	  If FPU ISA is used in user space, this configuration shall be Y to
19 	  If no FPU ISA is used in user space, say N.
21 config LAZY_FPU
32 config SUPPORT_DENORMAL_ARITHMETIC
45 config HWZOL
50 	  A set of Zero-Overhead Loop mechanism is provided to reduce the
51 	  instruction fetch and execution overhead of loop-control instructions.
58 config CPU_CACHE_ALIASING
84 config CPU_N15
86 config CPU_N13
89 config CPU_N10
92 config CPU_D15
94 config CPU_D10
97 config CPU_V3
102 	prompt "Paging -- page size "
104 config  ANDES_PAGE_SIZE_4KB
106 config  ANDES_PAGE_SIZE_8KB
110 config CPU_ICACHE_DISABLE
111 	bool "Disable I-Cache"
116 config CPU_DCACHE_DISABLE
117 	bool "Disable D-Cache"
122 config CPU_DCACHE_WRITETHROUGH
123 	bool "Force write through D-cache"
129 config WBNA
133 	  Say Y here to enable write-back memory with no-write-allocation policy.
135 config ALIGNMENT_TRAP
142 	  address divisible by 4. On 32-bit Andes processors, these non-aligned
144 	  here, which has a severe performance impact. With an IP-only
147 config HW_SUPPORT_UNALIGNMENT_ACCESS
152 	  Andes processors load/store world/half-word instructions can access
154 	  Check exceptions. With an IP-only configuration it is safe to say N,
157 config HIGHMEM
161 	  The address space of Andes processors is only 4 Gigabytes large
162 	  and it has to accommodate user address space, kernel address
163 	  space as well as some memory mapped IO. That means that, if you
169 	  vmalloc space and actual amount of RAM, you may not need this
174 config CACHE_L2
181 config HW_PRE
200 	config VMSPLIT_3G
202 	config VMSPLIT_3G_OPT
204 	config VMSPLIT_2G
206 	config VMSPLIT_1G
210 config PAGE_OFFSET