Lines Matching +full:0 +full:xc02
53 .offset = 0x21000,
56 .enable_reg = 0x0b000,
57 .enable_mask = BIT(0),
82 .offset = 0x21000,
101 { P_XO, 0 },
107 .offset = 0x25000,
111 .enable_reg = 0x0b000,
125 .offset = 0x25000,
139 .offset = 0x37000,
142 .enable_reg = 0x0b000,
156 .offset = 0x37000,
169 .offset = 0x24000,
172 .enable_reg = 0x0b000,
186 .offset = 0x24000,
199 F(24000000, P_XO, 1, 0, 0),
200 F(50000000, P_GPLL0, 16, 0, 0),
201 F(100000000, P_GPLL0, 8, 0, 0),
206 .cmd_rcgr = 0x27000,
219 .offset = 0x4a000,
222 .enable_reg = 0x0b000,
236 .offset = 0x4a000,
249 .offset = 0x22000,
252 .enable_reg = 0x0b000,
266 .offset = 0x22000,
279 F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
280 F(320000000, P_GPLL0, 2.5, 0, 0),
281 F(600000000, P_GPLL4, 2, 0, 0),
294 { P_XO, 0 },
302 .cmd_rcgr = 0x29064,
327 F(66670000, P_GPLL0_DIV2, 6, 0, 0),
328 F(240000000, P_GPLL4, 5, 0, 0),
333 .cmd_rcgr = 0x2900c,
359 F(24000000, P_XO, 1, 0, 0),
360 F(300000000, P_BIAS_PLL, 1, 0, 0),
374 { P_XO, 0 },
383 .cmd_rcgr = 0x68080,
396 .halt_reg = 0x30018,
398 .enable_reg = 0x30018,
413 F(24000000, P_XO, 1, 0, 0),
414 F(200000000, P_GPLL0, 4, 0, 0),
424 { P_XO, 0 },
429 .cmd_rcgr = 0x68098,
442 .halt_reg = 0x30000,
444 .enable_reg = 0x30000,
458 F(24000000, P_XO, 1, 0, 0),
459 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
460 F(100000000, P_GPLL0, 8, 0, 0),
461 F(133333333, P_GPLL0, 6, 0, 0),
462 F(160000000, P_GPLL0, 5, 0, 0),
463 F(200000000, P_GPLL0, 4, 0, 0),
464 F(266666667, P_GPLL0, 3, 0, 0),
477 { P_XO, 0 },
484 .cmd_rcgr = 0x76054,
497 F(24000000, P_XO, 1, 0, 0),
498 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
499 F(50000000, P_GPLL0, 16, 0, 0),
500 F(100000000, P_GPLL0, 8, 0, 0),
505 .cmd_rcgr = 0x46000,
518 F(24000000, P_XO, 1, 0, 0),
519 F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
520 F(25000000, P_UNIPHY0_RX, 5, 0, 0),
521 F(78125000, P_UNIPHY1_RX, 4, 0, 0),
522 F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
523 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
524 F(156250000, P_UNIPHY1_RX, 2, 0, 0),
525 F(312500000, P_UNIPHY1_RX, 1, 0, 0),
542 { P_XO, 0 },
552 .cmd_rcgr = 0x68060,
565 F(24000000, P_XO, 1, 0, 0),
566 F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
567 F(25000000, P_UNIPHY0_TX, 5, 0, 0),
568 F(78125000, P_UNIPHY1_TX, 4, 0, 0),
569 F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
570 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
571 F(156250000, P_UNIPHY1_TX, 2, 0, 0),
572 F(312500000, P_UNIPHY1_TX, 1, 0, 0),
589 { P_XO, 0 },
599 .cmd_rcgr = 0x68068,
612 F(24000000, P_XO, 1, 0, 0),
613 F(200000000, P_GPLL0, 4, 0, 0),
614 F(240000000, P_GPLL4, 5, 0, 0),
619 F(24000000, P_XO, 1, 0, 0),
620 F(100000000, P_GPLL0, 8, 0, 0),
631 { P_XO, 0 },
637 .cmd_rcgr = 0x75054,
650 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
651 F(100000000, P_GPLL0, 8, 0, 0),
652 F(133330000, P_GPLL0, 6, 0, 0),
653 F(200000000, P_GPLL0, 4, 0, 0),
664 { P_XO, 0 },
670 .cmd_rcgr = 0x3e00c,
684 .reg = 0x46018,
712 F(24000000, P_XO, 1, 0, 0),
713 F(25000000, P_UNIPHY0_RX, 5, 0, 0),
714 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
727 { P_XO, 0 },
735 .cmd_rcgr = 0x68020,
748 F(24000000, P_XO, 1, 0, 0),
749 F(25000000, P_UNIPHY0_TX, 5, 0, 0),
750 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
763 { P_XO, 0 },
771 .cmd_rcgr = 0x68028,
784 .cmd_rcgr = 0x68030,
797 .cmd_rcgr = 0x68038,
810 .cmd_rcgr = 0x68040,
823 .cmd_rcgr = 0x68048,
836 .cmd_rcgr = 0x68050,
849 .cmd_rcgr = 0x68058,
862 .reg = 0x68440,
863 .shift = 0,
878 .reg = 0x68444,
879 .shift = 0,
894 F(24000000, P_XO, 1, 0, 0),
895 F(100000000, P_GPLL0_DIV2, 4, 0, 0),
896 F(200000000, P_GPLL0, 4, 0, 0),
897 F(308570000, P_GPLL6, 3.5, 0, 0),
898 F(400000000, P_GPLL0, 2, 0, 0),
899 F(533000000, P_GPLL0, 1.5, 0, 0),
913 { P_XO, 0 },
921 .cmd_rcgr = 0x38048,
934 F(24000000, P_XO, 1, 0, 0),
935 F(300000000, P_NSS_CRYPTO_PLL, 2, 0, 0),
946 { P_XO, 0 },
952 .cmd_rcgr = 0x68144,
966 .reg = 0x68400,
967 .shift = 0,
982 .reg = 0x68404,
983 .shift = 0,
998 .reg = 0x68410,
999 .shift = 0,
1014 .reg = 0x68414,
1015 .shift = 0,
1030 .reg = 0x68420,
1031 .shift = 0,
1046 .reg = 0x68424,
1047 .shift = 0,
1062 .reg = 0x68430,
1063 .shift = 0,
1078 .reg = 0x68434,
1079 .shift = 0,
1094 F(24000000, P_XO, 1, 0, 0),
1095 F(149760000, P_UBI32_PLL, 10, 0, 0),
1096 F(187200000, P_UBI32_PLL, 8, 0, 0),
1097 F(249600000, P_UBI32_PLL, 6, 0, 0),
1098 F(374400000, P_UBI32_PLL, 4, 0, 0),
1099 F(748800000, P_UBI32_PLL, 2, 0, 0),
1100 F(1497600000, P_UBI32_PLL, 1, 0, 0),
1115 { P_XO, 0 },
1124 .cmd_rcgr = 0x68104,
1138 F(24000000, P_XO, 1, 0, 0),
1139 F(100000000, P_GPLL0, 8, 0, 0),
1144 .cmd_rcgr = 0x1c008,
1157 F(24000000, P_XO, 1, 0, 0),
1158 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1159 F(50000000, P_GPLL0, 16, 0, 0),
1164 .cmd_rcgr = 0x0200c,
1178 F(4800000, P_XO, 5, 0, 0),
1182 F(24000000, P_XO, 1, 0, 0),
1184 F(50000000, P_GPLL0, 16, 0, 0),
1189 .cmd_rcgr = 0x02024,
1203 .cmd_rcgr = 0x03000,
1216 .cmd_rcgr = 0x03014,
1230 .cmd_rcgr = 0x04000,
1243 .cmd_rcgr = 0x04014,
1257 .cmd_rcgr = 0x05000,
1270 .cmd_rcgr = 0x05014,
1284 .cmd_rcgr = 0x06000,
1297 .cmd_rcgr = 0x06014,
1311 .cmd_rcgr = 0x07000,
1324 .cmd_rcgr = 0x07014,
1342 F(24000000, P_XO, 1, 0, 0),
1358 .cmd_rcgr = 0x02044,
1372 .cmd_rcgr = 0x03034,
1386 .cmd_rcgr = 0x04034,
1400 .cmd_rcgr = 0x05034,
1414 .cmd_rcgr = 0x06034,
1428 .cmd_rcgr = 0x07034,
1442 F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1443 F(80000000, P_GPLL0, 10, 0, 0),
1444 F(100000000, P_GPLL0, 8, 0, 0),
1445 F(160000000, P_GPLL0, 5, 0, 0),
1450 .cmd_rcgr = 0x16004,
1463 F(24000000, P_XO, 1, 0, 0),
1464 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1465 F(100000000, P_GPLL0, 8, 0, 0),
1466 F(200000000, P_GPLL0, 4, 0, 0),
1467 F(266666666, P_GPLL0, 3, 0, 0),
1480 { P_XO, 0 },
1488 .cmd_rcgr = 0x08004,
1502 .cmd_rcgr = 0x09004,
1516 .cmd_rcgr = 0x0a004,
1543 .reg = 0x68118,
1544 .shift = 0,
1559 F(24000000, P_XO, 1, 0, 0),
1569 { P_XO, 0 },
1575 .cmd_rcgr = 0x75024,
1594 { P_PCIE20_PHY0_PIPE, 0 },
1599 .reg = 0x7501c,
1619 F(96000000, P_GPLL2, 12, 0, 0),
1620 F(177777778, P_GPLL0, 4.5, 0, 0),
1621 F(192000000, P_GPLL2, 6, 0, 0),
1622 F(384000000, P_GPLL2, 3, 0, 0),
1635 { P_XO, 0 },
1642 .cmd_rcgr = 0x42004,
1656 F(24000000, P_XO, 1, 0, 0),
1661 .cmd_rcgr = 0x3e05c,
1675 F(24000000, P_XO, 1, 0, 0),
1689 { P_XO, 0 },
1696 .cmd_rcgr = 0x3e020,
1715 { P_USB3PHY_0_PIPE, 0 },
1720 .reg = 0x3e048,
1736 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1737 F(160000000, P_GPLL0, 5, 0, 0),
1738 F(216000000, P_GPLL6, 5, 0, 0),
1739 F(308570000, P_GPLL6, 3.5, 0, 0),
1750 { P_XO, 0 },
1757 .cmd_rcgr = 0x5d000,
1771 F(24000000, P_XO, 1, 0, 0),
1772 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1773 F(100000000, P_GPLL0, 8, 0, 0),
1774 F(200000000, P_GPLL0, 4, 0, 0),
1779 .cmd_rcgr = 0x2902C,
1792 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1793 F(160000000, P_GPLL0, 5, 0, 0),
1794 F(300000000, P_GPLL4, 4, 0, 0),
1806 { P_XO, 0 },
1813 .cmd_rcgr = 0x29048,
1826 .cmd_rcgr = 0x3f020,
1840 .halt_reg = 0x1c020,
1842 .enable_reg = 0x1c020,
1843 .enable_mask = BIT(0),
1856 .halt_reg = 0x4601c,
1859 .enable_reg = 0x0b004,
1873 F(24000000, P_XO, 1, 0, 0),
1874 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1875 F(100000000, P_GPLL0, 8, 0, 0),
1876 F(133333333, P_GPLL0, 6, 0, 0),
1877 F(160000000, P_GPLL0, 5, 0, 0),
1878 F(200000000, P_GPLL0, 4, 0, 0),
1879 F(266666667, P_GPLL0, 3, 0, 0),
1884 .cmd_rcgr = 0x26004,
1897 F(24000000, P_XO, 1, 0, 0),
1898 F(307670000, P_BIAS_PLL_NSS_NOC, 1.5, 0, 0),
1899 F(533333333, P_GPLL0, 1.5, 0, 0),
1912 { P_XO, 0 },
1919 .cmd_rcgr = 0x68088,
1932 .halt_reg = 0x46020,
1935 .enable_reg = 0x0b004,
1949 .halt_reg = 0x01008,
1952 .enable_reg = 0x0b004,
1966 .halt_reg = 0x02008,
1968 .enable_reg = 0x02008,
1969 .enable_mask = BIT(0),
1982 .halt_reg = 0x02004,
1984 .enable_reg = 0x02004,
1985 .enable_mask = BIT(0),
1998 .halt_reg = 0x03010,
2000 .enable_reg = 0x03010,
2001 .enable_mask = BIT(0),
2014 .halt_reg = 0x0300c,
2016 .enable_reg = 0x0300c,
2017 .enable_mask = BIT(0),
2030 .halt_reg = 0x04010,
2032 .enable_reg = 0x04010,
2033 .enable_mask = BIT(0),
2046 .halt_reg = 0x0400c,
2048 .enable_reg = 0x0400c,
2049 .enable_mask = BIT(0),
2062 .halt_reg = 0x05010,
2064 .enable_reg = 0x05010,
2065 .enable_mask = BIT(0),
2078 .halt_reg = 0x0500c,
2080 .enable_reg = 0x0500c,
2081 .enable_mask = BIT(0),
2094 .halt_reg = 0x06010,
2096 .enable_reg = 0x06010,
2097 .enable_mask = BIT(0),
2110 .halt_reg = 0x0600c,
2112 .enable_reg = 0x0600c,
2113 .enable_mask = BIT(0),
2126 .halt_reg = 0x0700c,
2128 .enable_reg = 0x0700c,
2129 .enable_mask = BIT(0),
2142 .halt_reg = 0x0203c,
2144 .enable_reg = 0x0203c,
2145 .enable_mask = BIT(0),
2158 .halt_reg = 0x0302c,
2160 .enable_reg = 0x0302c,
2161 .enable_mask = BIT(0),
2174 .halt_reg = 0x0402c,
2176 .enable_reg = 0x0402c,
2177 .enable_mask = BIT(0),
2190 .halt_reg = 0x0502c,
2192 .enable_reg = 0x0502c,
2193 .enable_mask = BIT(0),
2206 .halt_reg = 0x0602c,
2208 .enable_reg = 0x0602c,
2209 .enable_mask = BIT(0),
2222 .halt_reg = 0x0702c,
2224 .enable_reg = 0x0702c,
2225 .enable_mask = BIT(0),
2238 .halt_reg = 0x16024,
2241 .enable_reg = 0x0b004,
2242 .enable_mask = BIT(0),
2255 .halt_reg = 0x16020,
2258 .enable_reg = 0x0b004,
2272 .halt_reg = 0x1601c,
2275 .enable_reg = 0x0b004,
2302 .halt_reg = 0x30030,
2304 .enable_reg = 0x30030,
2305 .enable_mask = BIT(0),
2318 .halt_reg = 0x08000,
2320 .enable_reg = 0x08000,
2321 .enable_mask = BIT(0),
2334 .halt_reg = 0x09000,
2336 .enable_reg = 0x09000,
2337 .enable_mask = BIT(0),
2350 .halt_reg = 0x0a000,
2352 .enable_reg = 0x0a000,
2353 .enable_mask = BIT(0),
2366 .halt_reg = 0x58004,
2368 .enable_reg = 0x58004,
2369 .enable_mask = BIT(0),
2382 .halt_reg = 0x68310,
2384 .enable_reg = 0x68310,
2385 .enable_mask = BIT(0),
2398 .halt_reg = 0x68174,
2400 .enable_reg = 0x68174,
2401 .enable_mask = BIT(0),
2414 .halt_reg = 0x68170,
2416 .enable_reg = 0x68170,
2417 .enable_mask = BIT(0),
2430 .halt_reg = 0x68160,
2432 .enable_reg = 0x68160,
2433 .enable_mask = BIT(0),
2446 .halt_reg = 0x68164,
2448 .enable_reg = 0x68164,
2449 .enable_mask = BIT(0),
2462 .halt_reg = 0x68318,
2464 .enable_reg = 0x68318,
2465 .enable_mask = BIT(0),
2478 .halt_reg = 0x6819C,
2480 .enable_reg = 0x6819C,
2481 .enable_mask = BIT(0),
2494 .halt_reg = 0x68198,
2496 .enable_reg = 0x68198,
2497 .enable_mask = BIT(0),
2510 .halt_reg = 0x68168,
2512 .enable_reg = 0x68168,
2513 .enable_mask = BIT(0),
2526 .halt_reg = 0x2606c,
2528 .enable_reg = 0x2606c,
2529 .enable_mask = BIT(0),
2542 .halt_reg = 0x26070,
2544 .enable_reg = 0x26070,
2545 .enable_mask = BIT(0),
2558 F(24000000, P_XO, 1, 0, 0),
2559 F(133333333, P_GPLL0, 6, 0, 0),
2564 F(24000000, P_XO, 1, 0, 0),
2565 F(400000000, P_GPLL0, 2, 0, 0),
2570 .cmd_rcgr = 0x59020,
2591 { P_XO, 0 },
2599 .cmd_rcgr = 0x59120,
2612 F(24000000, P_XO, 1, 0, 0),
2613 F(100000000, P_GPLL0, 8, 0, 0),
2618 .cmd_rcgr = 0x1F020,
2631 F(24000000, P_XO, 1, 0, 0),
2632 F(266666667, P_GPLL0, 3, 0, 0),
2637 .cmd_rcgr = 0x1F040,
2650 F(24000000, P_XO, 1, 0, 0),
2651 F(400000000, P_GPLL0, 2, 0, 0),
2656 .cmd_rcgr = 0x1F008,
2669 F(24000000, P_XO, 1, 0, 0),
2670 F(50000000, P_GPLL0, 16, 0, 0),
2675 .cmd_rcgr = 0x3a00c,
2688 .halt_reg = 0x1F028,
2690 .enable_reg = 0x1F028,
2691 .enable_mask = BIT(0),
2704 .halt_reg = 0x1F048,
2706 .enable_reg = 0x1F048,
2707 .enable_mask = BIT(0),
2720 .halt_reg = 0x1F010,
2722 .enable_reg = 0x1F010,
2723 .enable_mask = BIT(0),
2736 .halt_reg = 0x1F018,
2738 .enable_reg = 0x1F018,
2739 .enable_mask = BIT(0),
2752 .halt_reg = 0x1F01C,
2754 .enable_reg = 0x1F01C,
2755 .enable_mask = BIT(0),
2768 .halt_reg = 0x1F014,
2770 .enable_reg = 0x1F014,
2771 .enable_mask = BIT(0),
2784 .halt_reg = 0x1F038,
2786 .enable_reg = 0x1F038,
2787 .enable_mask = BIT(0),
2800 .halt_reg = 0x12094,
2802 .enable_reg = 0xb00c,
2816 .halt_reg = 0x27020,
2818 .enable_reg = 0x27020,
2819 .enable_mask = BIT(0),
2832 .halt_reg = 0x1D044,
2834 .enable_reg = 0x1D044,
2835 .enable_mask = BIT(0),
2848 .halt_reg = 0x26074,
2850 .enable_reg = 0x26074,
2851 .enable_mask = BIT(0),
2864 .halt_reg = 0x1D03C,
2866 .enable_reg = 0x1D03C,
2867 .enable_mask = BIT(0),
2880 .halt_reg = 0x68240,
2882 .enable_reg = 0x68240,
2883 .enable_mask = BIT(0),
2896 .halt_reg = 0x68244,
2898 .enable_reg = 0x68244,
2899 .enable_mask = BIT(0),
2912 .halt_reg = 0x68248,
2914 .enable_reg = 0x68248,
2915 .enable_mask = BIT(0),
2928 .halt_reg = 0x6824c,
2930 .enable_reg = 0x6824c,
2931 .enable_mask = BIT(0),
2944 .halt_reg = 0x68250,
2946 .enable_reg = 0x68250,
2947 .enable_mask = BIT(0),
2960 .halt_reg = 0x68254,
2962 .enable_reg = 0x68254,
2963 .enable_mask = BIT(0),
2976 .halt_reg = 0x68258,
2978 .enable_reg = 0x68258,
2979 .enable_mask = BIT(0),
2992 .halt_reg = 0x6825c,
2994 .enable_reg = 0x6825c,
2995 .enable_mask = BIT(0),
3008 .halt_reg = 0x68260,
3010 .enable_reg = 0x68260,
3011 .enable_mask = BIT(0),
3024 .halt_reg = 0x68264,
3026 .enable_reg = 0x68264,
3027 .enable_mask = BIT(0),
3040 .halt_reg = 0x68194,
3042 .enable_reg = 0x68194,
3043 .enable_mask = BIT(0),
3056 .halt_reg = 0x68190,
3058 .enable_reg = 0x68190,
3059 .enable_mask = BIT(0),
3072 .halt_reg = 0x68338,
3074 .enable_reg = 0x68338,
3075 .enable_mask = BIT(0),
3088 .halt_reg = 0x6816C,
3090 .enable_reg = 0x6816C,
3091 .enable_mask = BIT(0),
3104 .halt_reg = 0x6830C,
3106 .enable_reg = 0x6830C,
3107 .enable_mask = BIT(0),
3120 .halt_reg = 0x68308,
3122 .enable_reg = 0x68308,
3123 .enable_mask = BIT(0),
3136 .halt_reg = 0x68314,
3138 .enable_reg = 0x68314,
3139 .enable_mask = BIT(0),
3152 .halt_reg = 0x68304,
3154 .enable_reg = 0x68304,
3155 .enable_mask = BIT(0),
3167 .halt_reg = 0x68300,
3169 .enable_reg = 0x68300,
3170 .enable_mask = BIT(0),
3183 .halt_reg = 0x68180,
3185 .enable_reg = 0x68180,
3186 .enable_mask = BIT(0),
3199 .halt_reg = 0x68188,
3201 .enable_reg = 0x68188,
3202 .enable_mask = BIT(0),
3215 .halt_reg = 0x68184,
3217 .enable_reg = 0x68184,
3218 .enable_mask = BIT(0),
3231 .halt_reg = 0x68270,
3233 .enable_reg = 0x68270,
3234 .enable_mask = BIT(0),
3247 .halt_reg = 0x68320,
3249 .enable_reg = 0x68320,
3250 .enable_mask = BIT(0),
3263 .halt_reg = 0x68324,
3265 .enable_reg = 0x68324,
3266 .enable_mask = BIT(0),
3279 .halt_reg = 0x68328,
3281 .enable_reg = 0x68328,
3282 .enable_mask = BIT(0),
3295 .halt_reg = 0x6832c,
3297 .enable_reg = 0x6832c,
3298 .enable_mask = BIT(0),
3311 .halt_reg = 0x68330,
3313 .enable_reg = 0x68330,
3314 .enable_mask = BIT(0),
3327 .halt_reg = 0x6820C,
3330 .enable_reg = 0x6820C,
3331 .enable_mask = BIT(0),
3344 .halt_reg = 0x68200,
3347 .enable_reg = 0x68200,
3348 .enable_mask = BIT(0),
3361 .halt_reg = 0x68204,
3364 .enable_reg = 0x68204,
3365 .enable_mask = BIT(0),
3378 .halt_reg = 0x68210,
3381 .enable_reg = 0x68210,
3382 .enable_mask = BIT(0),
3395 .halt_reg = 0x75010,
3397 .enable_reg = 0x75010,
3398 .enable_mask = BIT(0),
3411 .halt_reg = 0x75014,
3413 .enable_reg = 0x75014,
3414 .enable_mask = BIT(0),
3427 .halt_reg = 0x75008,
3429 .enable_reg = 0x75008,
3430 .enable_mask = BIT(0),
3443 .halt_reg = 0x7500c,
3445 .enable_reg = 0x7500c,
3446 .enable_mask = BIT(0),
3459 .halt_reg = 0x26048,
3461 .enable_reg = 0x26048,
3462 .enable_mask = BIT(0),
3475 .halt_reg = 0x75018,
3478 .enable_reg = 0x75018,
3479 .enable_mask = BIT(0),
3492 .halt_reg = 0x13004,
3495 .enable_reg = 0x0b004,
3509 .halt_reg = 0x29084,
3511 .enable_reg = 0x29084,
3512 .enable_mask = BIT(0),
3525 .halt_reg = 0x57024,
3527 .enable_reg = 0x57024,
3528 .enable_mask = BIT(0),
3541 .halt_reg = 0x57020,
3543 .enable_reg = 0x57020,
3544 .enable_mask = BIT(0),
3557 .halt_reg = 0x4201c,
3559 .enable_reg = 0x4201c,
3560 .enable_mask = BIT(0),
3573 .halt_reg = 0x42018,
3575 .enable_reg = 0x42018,
3576 .enable_mask = BIT(0),
3589 .halt_reg = 0x56008,
3591 .enable_reg = 0x56008,
3592 .enable_mask = BIT(0),
3605 .halt_reg = 0x56010,
3607 .enable_reg = 0x56010,
3608 .enable_mask = BIT(0),
3621 .halt_reg = 0x56014,
3623 .enable_reg = 0x56014,
3624 .enable_mask = BIT(0),
3637 .halt_reg = 0x56018,
3639 .enable_reg = 0x56018,
3640 .enable_mask = BIT(0),
3653 .halt_reg = 0x5601c,
3655 .enable_reg = 0x5601c,
3656 .enable_mask = BIT(0),
3669 .halt_reg = 0x56020,
3671 .enable_reg = 0x56020,
3672 .enable_mask = BIT(0),
3685 .halt_reg = 0x56024,
3687 .enable_reg = 0x56024,
3688 .enable_mask = BIT(0),
3701 .halt_reg = 0x56028,
3703 .enable_reg = 0x56028,
3704 .enable_mask = BIT(0),
3717 .halt_reg = 0x5602c,
3719 .enable_reg = 0x5602c,
3720 .enable_mask = BIT(0),
3733 .halt_reg = 0x56030,
3735 .enable_reg = 0x56030,
3736 .enable_mask = BIT(0),
3749 .halt_reg = 0x56034,
3751 .enable_reg = 0x56034,
3752 .enable_mask = BIT(0),
3765 .halt_reg = 0x5600C,
3767 .enable_reg = 0x5600C,
3768 .enable_mask = BIT(0),
3781 .halt_reg = 0x56108,
3783 .enable_reg = 0x56108,
3784 .enable_mask = BIT(0),
3797 .halt_reg = 0x56110,
3799 .enable_reg = 0x56110,
3800 .enable_mask = BIT(0),
3813 .halt_reg = 0x56114,
3815 .enable_reg = 0x56114,
3816 .enable_mask = BIT(0),
3829 .halt_reg = 0x5610C,
3831 .enable_reg = 0x5610C,
3832 .enable_mask = BIT(0),
3845 .halt_reg = 0x3e044,
3847 .enable_reg = 0x3e044,
3848 .enable_mask = BIT(0),
3861 .halt_reg = 0x3e000,
3863 .enable_reg = 0x3e000,
3864 .enable_mask = BIT(0),
3877 .halt_reg = 0x47014,
3879 .enable_reg = 0x47014,
3880 .enable_mask = BIT(0),
3893 .cmd_rcgr = 0x75070,
3906 .halt_reg = 0x75070,
3908 .enable_reg = 0x75070,
3922 .halt_reg = 0x75048,
3924 .enable_reg = 0x75048,
3925 .enable_mask = BIT(0),
3938 .halt_reg = 0x26040,
3940 .enable_reg = 0x26040,
3941 .enable_mask = BIT(0),
3954 .halt_reg = 0x3e008,
3956 .enable_reg = 0x3e008,
3957 .enable_mask = BIT(0),
3970 .halt_reg = 0x3e080,
3972 .enable_reg = 0x3e080,
3973 .enable_mask = BIT(0),
3986 .halt_reg = 0x3e040,
3989 .enable_reg = 0x3e040,
3990 .enable_mask = BIT(0),
4003 .halt_reg = 0x3e004,
4005 .enable_reg = 0x3e004,
4006 .enable_mask = BIT(0),
4019 .halt_reg = 0x3f000,
4021 .enable_reg = 0x3f000,
4022 .enable_mask = BIT(0),
4035 .halt_reg = 0x3f008,
4037 .enable_reg = 0x3f008,
4038 .enable_mask = BIT(0),
4051 .halt_reg = 0x3f080,
4053 .enable_reg = 0x3f080,
4054 .enable_mask = BIT(0),
4067 .halt_reg = 0x3f004,
4069 .enable_reg = 0x3f004,
4070 .enable_mask = BIT(0),
4083 .halt_reg = 0x56308,
4085 .enable_reg = 0x56308,
4086 .enable_mask = BIT(0),
4099 .halt_reg = 0x5630c,
4101 .enable_reg = 0x5630c,
4102 .enable_mask = BIT(0),
4115 .halt_reg = 0x5d014,
4117 .enable_reg = 0x5d014,
4118 .enable_mask = BIT(0),
4131 .halt_reg = 0x77004,
4133 .enable_reg = 0x77004,
4134 .enable_mask = BIT(0),
4147 .l = 0x3e,
4148 .alpha = 0x57,
4149 .config_ctl_val = 0x240d6aa8,
4150 .config_ctl_hi_val = 0x3c2,
4151 .main_output_mask = BIT(0),
4153 .pre_div_val = 0x0,
4155 .post_div_val = 0x0,
4160 .l = 0x32,
4161 .alpha = 0x0,
4162 .alpha_hi = 0x0,
4163 .config_ctl_val = 0x4001055b,
4164 .main_output_mask = BIT(0),
4165 .pre_div_val = 0x0,
4167 .post_div_val = 0x1 << 8,
4170 .vco_val = 0x0,
4407 [GCC_BLSP1_BCR] = { 0x01000, 0 },
4408 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4409 [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4410 [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4411 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4412 [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4413 [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4414 [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4415 [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4416 [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4417 [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4418 [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4419 [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4420 [GCC_IMEM_BCR] = { 0x0e000, 0 },
4421 [GCC_SMMU_BCR] = { 0x12000, 0 },
4422 [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4423 [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4424 [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4425 [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4426 [GCC_PRNG_BCR] = { 0x13000, 0 },
4427 [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4428 [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4429 [GCC_WCSS_BCR] = { 0x18000, 0 },
4430 [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4431 [GCC_NSS_BCR] = { 0x19000, 0 },
4432 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4433 [GCC_ADSS_BCR] = { 0x1c000, 0 },
4434 [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4435 [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4436 [GCC_PCNOC_BCR] = { 0x27018, 0 },
4437 [GCC_TCSR_BCR] = { 0x28000, 0 },
4438 [GCC_QDSS_BCR] = { 0x29000, 0 },
4439 [GCC_DCD_BCR] = { 0x2a000, 0 },
4440 [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4441 [GCC_MPM_BCR] = { 0x2c000, 0 },
4442 [GCC_SPDM_BCR] = { 0x2f000, 0 },
4443 [GCC_RBCPR_BCR] = { 0x33000, 0 },
4444 [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4445 [GCC_TLMM_BCR] = { 0x34000, 0 },
4446 [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4447 [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4448 [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4449 [GCC_USB0_BCR] = { 0x3e070, 0 },
4450 [GCC_USB1_BCR] = { 0x3f070, 0 },
4451 [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4452 [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4453 [GCC_SDCC1_BCR] = { 0x42000, 0 },
4454 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4455 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x47008, 0 },
4456 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47010, 0 },
4457 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4458 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4459 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4460 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4461 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4462 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4463 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4464 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4465 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4466 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4467 [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4468 [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4469 [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4470 [GCC_QPIC_BCR] = { 0x57018, 0 },
4471 [GCC_MDIO_BCR] = { 0x58000, 0 },
4472 [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4473 [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4474 [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4475 [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4476 [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4477 [GCC_PCIE0_BCR] = { 0x75004, 0 },
4478 [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4479 [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4480 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4481 [GCC_DCC_BCR] = { 0x77000, 0 },
4482 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4483 [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4484 [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4485 [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4486 [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4487 [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4488 [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4489 [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4490 [GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
4491 [GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
4492 [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4493 [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4494 [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4495 [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4496 [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4497 [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4498 [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4499 [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4500 [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4501 [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4502 [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4503 [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4504 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4505 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4506 [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4507 [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4508 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4509 [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4510 [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4511 [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4512 [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4513 [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4514 [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 },
4515 [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 },
4516 [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
4517 [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 },
4518 [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
4519 [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 },
4520 [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 },
4521 [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c },
4522 [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 },
4523 [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 },
4524 [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 },
4525 [GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 },
4526 [GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 },
4527 [GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 },
4528 [GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 },
4529 [GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 },
4530 [GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 },
4531 [GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 },
4532 [GCC_LPASS_BCR] = {0x1F000, 0},
4533 [GCC_UBI32_TBU_BCR] = {0x65000, 0},
4534 [GCC_LPASS_TBU_BCR] = {0x6C000, 0},
4535 [GCC_WCSSAON_RESET] = {0x59010, 0},
4536 [GCC_LPASS_Q6_AXIM_ARES] = {0x1F004, 0},
4537 [GCC_LPASS_Q6SS_TSCTR_1TO2_ARES] = {0x1F004, 1},
4538 [GCC_LPASS_Q6SS_TRIG_ARES] = {0x1F004, 2},
4539 [GCC_LPASS_Q6_ATBM_AT_ARES] = {0x1F004, 3},
4540 [GCC_LPASS_Q6_PCLKDBG_ARES] = {0x1F004, 4},
4541 [GCC_LPASS_CORE_AXIM_ARES] = {0x1F004, 5},
4542 [GCC_LPASS_SNOC_CFG_ARES] = {0x1F004, 6},
4543 [GCC_WCSS_DBG_ARES] = {0x59008, 0},
4544 [GCC_WCSS_ECAHB_ARES] = {0x59008, 1},
4545 [GCC_WCSS_ACMT_ARES] = {0x59008, 2},
4546 [GCC_WCSS_DBG_BDG_ARES] = {0x59008, 3},
4547 [GCC_WCSS_AHB_S_ARES] = {0x59008, 4},
4548 [GCC_WCSS_AXI_M_ARES] = {0x59008, 5},
4549 [GCC_Q6SS_DBG_ARES] = {0x59110, 0},
4550 [GCC_Q6_AHB_S_ARES] = {0x59110, 1},
4551 [GCC_Q6_AHB_ARES] = {0x59110, 2},
4552 [GCC_Q6_AXIM2_ARES] = {0x59110, 3},
4553 [GCC_Q6_AXIM_ARES] = {0x59110, 4},
4566 .max_register = 0x7fffc,
4589 regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0); in gcc_ipq6018_probe()
4591 regmap_update_bits(regmap, 0x3e078, BIT(2), BIT(2)); in gcc_ipq6018_probe()
4593 regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0); in gcc_ipq6018_probe()
4595 regmap_update_bits(regmap, 0x3f078, BIT(2), BIT(2)); in gcc_ipq6018_probe()
4598 regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); in gcc_ipq6018_probe()