Lines Matching +full:0 +full:x0210
45 { P_PXO, 0 },
57 { P_PXO, 0 },
71 { P_PXO, 0 },
85 { P_PXO, 0 },
97 { P_PXO, 0 },
109 .l_reg = 0x320,
110 .m_reg = 0x324,
111 .n_reg = 0x328,
112 .config_reg = 0x32c,
113 .mode_reg = 0x31c,
114 .status_reg = 0x334,
125 .l_reg = 0x33c,
126 .m_reg = 0x340,
127 .n_reg = 0x344,
128 .config_reg = 0x348,
129 .mode_reg = 0x338,
130 .status_reg = 0x350,
144 .vco_val = 0x2 << 16,
145 .vco_mask = 0x3 << 16,
146 .pre_div_val = 0x0,
148 .post_div_val = 0x0,
149 .post_div_mask = 0x3 << 20,
164 { 96000000, P_PLL8, 4, 0, 0 },
165 { 128000000, P_PLL8, 3, 0, 0 },
170 .ns_reg = 0x0148,
171 .md_reg = 0x0144,
186 .src_sel_shift = 0,
191 .enable_reg = 0x0140,
203 .halt_reg = 0x01e8,
206 .enable_reg = 0x0140,
207 .enable_mask = BIT(0),
219 .ns_reg = 0x015c,
220 .md_reg = 0x0158,
235 .src_sel_shift = 0,
240 .enable_reg = 0x0154,
252 .halt_reg = 0x01e8,
255 .enable_reg = 0x0154,
256 .enable_mask = BIT(0),
268 .ns_reg = 0x0228,
269 .md_reg = 0x0224,
284 .src_sel_shift = 0,
289 .enable_reg = 0x0220,
301 .halt_reg = 0x01e8,
304 .enable_reg = 0x0220,
305 .enable_mask = BIT(0),
317 { 27000000, P_PXO, 1, 0, 0 },
324 .ns_reg = 0x0048,
325 .md_reg = 0x0044,
339 .src_sel_shift = 0,
344 .enable_reg = 0x0040,
356 .halt_reg = 0x01cc,
359 .enable_reg = 0x0040,
360 .enable_mask = BIT(0),
372 .halt_reg = 0x01e8,
375 .enable_reg = 0x0040,
388 .ns_reg = 0x0010,
389 .md_reg = 0x0028,
403 .src_sel_shift = 0,
408 .enable_reg = 0x0024,
420 .halt_reg = 0x01cc,
423 .enable_reg = 0x0024,
424 .enable_mask = BIT(0),
436 .halt_reg = 0x01e8,
439 .enable_reg = 0x0024,
452 .ns_reg = 0x0234,
453 .md_reg = 0x022c,
467 .src_sel_shift = 0,
472 .enable_reg = 0x022c,
484 .halt_reg = 0x01cc,
487 .enable_reg = 0x022c,
488 .enable_mask = BIT(0),
500 .halt_reg = 0x01e8,
503 .enable_reg = 0x022c,
529 int ret = 0; in pix_rdi_set_parent()
542 for (i = 0; i < num_parents; i++) { in pix_rdi_set_parent()
552 val = 0; in pix_rdi_set_parent()
563 val = 0; in pix_rdi_set_parent()
572 for (i--; i >= 0; i--) { in pix_rdi_set_parent()
594 return 0; in pix_rdi_get_parent()
612 .s_reg = 0x0058,
614 .s2_reg = 0x0238,
617 .enable_reg = 0x0058,
629 .s_reg = 0x0238,
631 .s2_reg = 0x0238,
634 .enable_reg = 0x0238,
646 .s_reg = 0x0058,
648 .s2_reg = 0x0238,
651 .enable_reg = 0x0058,
663 .s_reg = 0x0238,
664 .s_mask = BIT(0),
665 .s2_reg = 0x0238,
668 .enable_reg = 0x0238,
680 .s_reg = 0x0238,
682 .s2_reg = 0x0238,
685 .enable_reg = 0x0238,
703 .ns_reg = 0x0168,
704 .md_reg = 0x0164,
719 .src_sel_shift = 0,
724 .enable_reg = 0x0160,
738 .halt_reg = 0x01e8,
741 .enable_reg = 0x0160,
742 .enable_mask = BIT(0),
754 .halt_reg = 0x01e8,
757 .enable_reg = 0x0160,
770 .halt_reg = 0x01e8,
773 .enable_reg = 0x0160,
786 F_MN( 27000000, P_PXO, 1, 0),
802 .ns_reg[0] = 0x0070,
803 .ns_reg[1] = 0x0070,
804 .md_reg[0] = 0x0064,
805 .md_reg[1] = 0x0068,
806 .bank_reg = 0x0060,
807 .mn[0] = {
823 .s[0] = {
828 .src_sel_shift = 0,
834 .enable_reg = 0x0060,
846 .halt_reg = 0x01c8,
849 .enable_reg = 0x0060,
850 .enable_mask = BIT(0),
862 .ns_reg[0] = 0x007c,
863 .ns_reg[1] = 0x007c,
864 .md_reg[0] = 0x0078,
865 .md_reg[1] = 0x006c,
866 .bank_reg = 0x0074,
867 .mn[0] = {
883 .s[0] = {
888 .src_sel_shift = 0,
894 .enable_reg = 0x0074,
906 .halt_reg = 0x01c8,
909 .enable_reg = 0x0074,
910 .enable_mask = BIT(0),
922 F_MN( 27000000, P_PXO, 1, 0),
942 F_MN( 27000000, P_PXO, 0, 0),
963 .ns_reg[0] = 0x008c,
964 .ns_reg[1] = 0x008c,
965 .md_reg[0] = 0x0084,
966 .md_reg[1] = 0x0088,
967 .bank_reg = 0x0080,
968 .mn[0] = {
984 .s[0] = {
989 .src_sel_shift = 0,
995 .enable_reg = 0x0080,
1014 .halt_reg = 0x01c8,
1017 .enable_reg = 0x0080,
1018 .enable_mask = BIT(0),
1030 F_MN( 27000000, P_PXO, 0, 0),
1041 .ns_reg[0] = 0x021c,
1042 .ns_reg[1] = 0x021c,
1043 .md_reg[0] = 0x01ec,
1044 .md_reg[1] = 0x0218,
1045 .bank_reg = 0x0178,
1046 .mn[0] = {
1062 .s[0] = {
1067 .src_sel_shift = 0,
1073 .enable_reg = 0x0178,
1085 .halt_reg = 0x0240,
1088 .enable_reg = 0x0178,
1089 .enable_mask = BIT(0),
1101 .halt_reg = 0x0240,
1104 .enable_reg = 0x0178,
1117 { 27000000, P_PXO, 1, 0, 0 },
1119 { 54860000, P_PLL8, 7, 0, 0 },
1120 { 96000000, P_PLL8, 4, 0, 0 },
1122 { 128000000, P_PLL8, 3, 0, 0 },
1124 { 200000000, P_PLL2, 4, 0, 0 },
1132 .ns_reg = 0x00a0,
1133 .md_reg = 0x009c,
1147 .src_sel_shift = 0,
1152 .enable_reg = 0x0098,
1164 .halt_reg = 0x01c8,
1167 .enable_reg = 0x0098,
1168 .enable_mask = BIT(0),
1189 .ns_reg = 0x00ac,
1195 .src_sel_shift = 0,
1200 .enable_reg = 0x00a4,
1212 .halt_reg = 0x01c8,
1215 .enable_reg = 0x00a4,
1216 .enable_mask = BIT(0),
1230 { 27000000, P_PXO, 1, 0, 0 },
1248 .ns_reg[0] = 0x00d0,
1249 .ns_reg[1] = 0x00d0,
1250 .md_reg[0] = 0x00c4,
1251 .md_reg[1] = 0x00c8,
1252 .bank_reg = 0x00c0,
1253 .mn[0] = {
1269 .s[0] = {
1274 .src_sel_shift = 0,
1280 .enable_reg = 0x00c0,
1292 .halt_reg = 0x01d0,
1295 .enable_reg = 0x00c0,
1296 .enable_mask = BIT(0),
1308 .halt_reg = 0x01e8,
1311 .enable_reg = 0x016c,
1312 .enable_mask = BIT(0),
1324 .halt_reg = 0x01cc,
1327 .enable_reg = 0x0058,
1357 .ns_reg[0] = 0x00e8,
1358 .ns_reg[1] = 0x00e8,
1359 .bank_reg = 0x00e8,
1360 .p[0] = {
1368 .s[0] = {
1379 .enable_reg = 0x00e0,
1391 .halt_reg = 0x01d0,
1394 .enable_reg = 0x00e0,
1395 .enable_mask = BIT(0),
1407 { P_PXO, 0 },
1422 .ns_reg = 0x00f4,
1423 .md_reg = 0x00f0,
1437 .src_sel_shift = 0,
1442 .enable_reg = 0x00ec,
1457 .halt_reg = 0x01d4,
1460 .enable_reg = 0x00ec,
1473 .halt_reg = 0x01d4,
1476 .enable_reg = 0x00ec,
1489 .halt_reg = 0x01d4,
1492 .enable_reg = 0x00ec,
1493 .enable_mask = BIT(0),
1505 .halt_reg = 0x01d4,
1508 .enable_reg = 0x00ec,
1521 .halt_reg = 0x0240,
1524 .enable_reg = 0x0124,
1537 .halt_reg = 0x0240,
1540 .enable_reg = 0x0124,
1553 .halt_reg = 0x01cc,
1556 .enable_reg = 0x005c,
1568 F_MN( 27000000, P_PXO, 1, 0),
1581 .ns_reg[0] = 0x0100,
1582 .ns_reg[1] = 0x0100,
1583 .md_reg[0] = 0x00fc,
1584 .md_reg[1] = 0x0128,
1585 .bank_reg = 0x00f8,
1586 .mn[0] = {
1602 .s[0] = {
1607 .src_sel_shift = 0,
1613 .enable_reg = 0x00f8,
1625 .halt_reg = 0x01d0,
1628 .enable_reg = 0x00f8,
1629 .enable_mask = BIT(0),
1653 .ns_reg = 0x0118,
1659 .src_sel_shift = 0,
1664 .enable_reg = 0x0110,
1676 .halt_reg = 0x01c8,
1679 .enable_reg = 0x0110,
1680 .enable_mask = BIT(0),
1693 { 27000000, P_PXO, 1, 0, 0 },
1713 .ns_reg = 0x0108,
1727 .src_sel_shift = 0,
1732 .enable_reg = 0x0104,
1744 .halt_reg = 0x01cc,
1747 .enable_reg = 0x0104,
1748 .enable_mask = BIT(0),
1760 .halt_reg = 0x01cc,
1763 .enable_reg = 0x0104,
1776 .halt_reg = 0x01d8,
1779 .enable_reg = 0x0018,
1789 .hwcg_reg = 0x0018,
1791 .halt_reg = 0x01d8,
1794 .enable_reg = 0x0018,
1804 .hwcg_reg = 0x0018,
1806 .halt_reg = 0x01d8,
1809 .enable_reg = 0x0018,
1819 .halt_reg = 0x01d8,
1822 .enable_reg = 0x0018,
1832 .hwcg_reg = 0x0114,
1834 .halt_reg = 0x01e8,
1837 .enable_reg = 0x0114,
1847 .hwcg_reg = 0x0114,
1849 .halt_reg = 0x01e8,
1852 .enable_reg = 0x0114,
1862 .hwcg_reg = 0x0018,
1864 .halt_reg = 0x01d8,
1867 .enable_reg = 0x0018,
1877 .halt_reg = 0x01d8,
1878 .halt_bit = 0,
1880 .enable_reg = 0x0018,
1890 .hwcg_reg = 0x0018,
1892 .halt_reg = 0x01d8,
1895 .enable_reg = 0x0018,
1905 .hwcg_reg = 0x0020,
1907 .halt_reg = 0x01d8,
1910 .enable_reg = 0x0020,
1920 .halt_reg = 0x0240,
1922 .hwcg_reg = 0x0244,
1925 .enable_reg = 0x0244,
1935 .hwcg_reg = 0x0020,
1937 .halt_reg = 0x01d8,
1940 .enable_reg = 0x0020,
1950 .hwcg_reg = 0x0244,
1952 .halt_reg = 0x0240,
1955 .enable_reg = 0x0244,
1965 .halt_reg = 0x01dc,
1968 .enable_reg = 0x0008,
1978 .halt_reg = 0x01dc,
1981 .enable_reg = 0x0008,
1991 .halt_reg = 0x01dc,
1994 .enable_reg = 0x0008,
2004 .hwcg_reg = 0x0038,
2006 .halt_reg = 0x01dc,
2009 .enable_reg = 0x0008,
2019 .halt_reg = 0x01d8,
2022 .enable_reg = 0x0008,
2032 .hwcg_reg = 0x0038,
2034 .halt_reg = 0x01dc,
2037 .enable_reg = 0x0008,
2047 .ns_reg = 0x0054,
2048 .md_reg = 0x0050,
2062 .src_sel_shift = 0,
2066 .enable_reg = 0x004c,
2079 .halt_reg = 0x01d0,
2082 .enable_reg = 0x004c,
2083 .enable_mask = BIT(0),
2095 .ns_reg = 0x012c,
2096 .md_reg = 0x00a8,
2110 .src_sel_shift = 0,
2114 .enable_reg = 0x003c,
2127 .halt_reg = 0x01d0,
2130 .enable_reg = 0x003c,
2131 .enable_mask = BIT(0),
2143 .ns_reg = 0x00b0,
2149 .src_sel_shift = 0,
2153 .enable_reg = 0x0090,
2166 .halt_reg = 0x01cc,
2169 .enable_reg = 0x0090,
2170 .enable_mask = BIT(0),
2182 .ns_reg = 0x012c,
2188 .src_sel_shift = 0,
2192 .enable_reg = 0x0130,
2205 .halt_reg = 0x01cc,
2208 .enable_reg = 0x00b4,
2209 .enable_mask = BIT(0),
2221 .ns_reg = 0x0011c,
2227 .src_sel_shift = 0,
2231 .enable_reg = 0x00cc,
2243 .halt_reg = 0x01e8,
2246 .enable_reg = 0x00cc,
2247 .enable_mask = BIT(0),
2259 .ns_reg = 0x0150,
2265 .src_sel_shift = 0,
2269 .enable_reg = 0x013c,
2281 .halt_reg = 0x01e8,
2284 .enable_reg = 0x013c,
2285 .enable_mask = BIT(0),
2297 .ns_reg = 0x0138,
2298 .md_reg = 0x0134,
2312 .src_sel_shift = 0,
2316 .enable_reg = 0x0130,
2328 .halt_reg = 0x01d0,
2331 .enable_reg = 0x0130,
2332 .enable_mask = BIT(0),
2344 .ns_reg = 0x00e4,
2345 .md_reg = 0x00b8,
2359 .src_sel_shift = 0,
2363 .enable_reg = 0x0094,
2375 .halt_reg = 0x01d0,
2378 .enable_reg = 0x0094,
2379 .enable_mask = BIT(0),
2391 .hwcg_reg = 0x0038,
2393 .halt_reg = 0x01dc,
2396 .enable_reg = 0x0008,
2406 .hwcg_reg = 0x0038,
2408 .halt_reg = 0x01dc,
2411 .enable_reg = 0x0008,
2421 .hwcg_reg = 0x0038,
2423 .halt_reg = 0x01dc,
2426 .enable_reg = 0x0008,
2436 .hwcg_reg = 0x0038,
2438 .halt_reg = 0x01dc,
2441 .enable_reg = 0x0008,
2451 .hwcg_reg = 0x0038,
2453 .halt_reg = 0x01dc,
2456 .enable_reg = 0x0008,
2466 .halt_reg = 0x01dc,
2469 .enable_reg = 0x0008,
2479 .hwcg_reg = 0x0038,
2481 .halt_reg = 0x01dc,
2484 .enable_reg = 0x0008,
2494 .halt_reg = 0x01dc,
2497 .enable_reg = 0x0008,
2507 .halt_reg = 0x01dc,
2510 .enable_reg = 0x0008,
2520 .halt_reg = 0x01dc,
2523 .enable_reg = 0x0008,
2533 .hwcg_reg = 0x0008,
2535 .halt_reg = 0x01dc,
2538 .enable_reg = 0x0008,
2548 .halt_reg = 0x01dc,
2551 .enable_reg = 0x0008,
2561 .halt_reg = 0x0240,
2564 .enable_reg = 0x0248,
2574 .hwcg_reg = 0x0038,
2576 .halt_reg = 0x01dc,
2579 .enable_reg = 0x0008,
2589 .halt_reg = 0x01dc,
2592 .enable_reg = 0x0008,
2602 .halt_reg = 0x01dc,
2605 .enable_reg = 0x0008,
2721 [VPE_AXI_RESET] = { 0x0208, 15 },
2722 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2723 [MPD_AXI_RESET] = { 0x0208, 13 },
2724 [VFE_AXI_RESET] = { 0x0208, 9 },
2725 [SP_AXI_RESET] = { 0x0208, 8 },
2726 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2727 [ROT_AXI_RESET] = { 0x0208, 6 },
2728 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2729 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2730 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2731 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2732 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2733 [FAB_S0_AXI_RESET] = { 0x0208 },
2734 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2735 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2736 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2737 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2738 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2739 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2740 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2741 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2742 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2743 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2744 [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2745 [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2746 [APU_AHB_RESET] = { 0x020c, 18 },
2747 [CSI_AHB_RESET] = { 0x020c, 17 },
2748 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2749 [VPE_AHB_RESET] = { 0x020c, 14 },
2750 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2751 [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2752 [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2753 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2754 [HDMI_AHB_RESET] = { 0x020c, 9 },
2755 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2756 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2757 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2758 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2759 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2760 [MDP_AHB_RESET] = { 0x020c, 3 },
2761 [ROT_AHB_RESET] = { 0x020c, 2 },
2762 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2763 [VFE_AHB_RESET] = { 0x020c, 0 },
2764 [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2765 [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2766 [CSIPHY2_RESET] = { 0x0210, 29 },
2767 [CSI_PIX1_RESET] = { 0x0210, 28 },
2768 [CSIPHY0_RESET] = { 0x0210, 27 },
2769 [CSIPHY1_RESET] = { 0x0210, 26 },
2770 [DSI2_RESET] = { 0x0210, 25 },
2771 [VFE_CSI_RESET] = { 0x0210, 24 },
2772 [MDP_RESET] = { 0x0210, 21 },
2773 [AMP_RESET] = { 0x0210, 20 },
2774 [JPEGD_RESET] = { 0x0210, 19 },
2775 [CSI1_RESET] = { 0x0210, 18 },
2776 [VPE_RESET] = { 0x0210, 17 },
2777 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2778 [VFE_RESET] = { 0x0210, 15 },
2779 [GFX2D0_RESET] = { 0x0210, 14 },
2780 [GFX2D1_RESET] = { 0x0210, 13 },
2781 [GFX3D_RESET] = { 0x0210, 12 },
2782 [HDMI_RESET] = { 0x0210, 11 },
2783 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2784 [IJPEG_RESET] = { 0x0210, 9 },
2785 [CSI0_RESET] = { 0x0210, 8 },
2786 [DSI_RESET] = { 0x0210, 7 },
2787 [VCODEC_RESET] = { 0x0210, 6 },
2788 [MDP_TV_RESET] = { 0x0210, 4 },
2789 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2790 [ROT_RESET] = { 0x0210, 2 },
2791 [TV_HDMI_RESET] = { 0x0210, 1 },
2792 [TV_ENC_RESET] = { 0x0210 },
2793 [CSI2_RESET] = { 0x0214, 2 },
2794 [CSI_RDI1_RESET] = { 0x0214, 1 },
2795 [CSI_RDI2_RESET] = { 0x0214 },
2905 [GFX3D_AXI_RESET] = { 0x0208, 17 },
2906 [VCAP_AXI_RESET] = { 0x0208, 16 },
2907 [VPE_AXI_RESET] = { 0x0208, 15 },
2908 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2909 [MPD_AXI_RESET] = { 0x0208, 13 },
2910 [VFE_AXI_RESET] = { 0x0208, 9 },
2911 [SP_AXI_RESET] = { 0x0208, 8 },
2912 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2913 [ROT_AXI_RESET] = { 0x0208, 6 },
2914 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2915 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2916 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2917 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2918 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2919 [FAB_S0_AXI_RESET] = { 0x0208 },
2920 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2921 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2922 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2923 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2924 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2925 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2926 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2927 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2928 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2929 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2930 [APU_AHB_RESET] = { 0x020c, 18 },
2931 [CSI_AHB_RESET] = { 0x020c, 17 },
2932 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2933 [VPE_AHB_RESET] = { 0x020c, 14 },
2934 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2935 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2936 [HDMI_AHB_RESET] = { 0x020c, 9 },
2937 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2938 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2939 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2940 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2941 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2942 [MDP_AHB_RESET] = { 0x020c, 3 },
2943 [ROT_AHB_RESET] = { 0x020c, 2 },
2944 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2945 [VFE_AHB_RESET] = { 0x020c, 0 },
2946 [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 },
2947 [VCAP_AHB_RESET] = { 0x0200, 2 },
2948 [DSI2_M_AHB_RESET] = { 0x0200, 1 },
2949 [DSI2_S_AHB_RESET] = { 0x0200, 0 },
2950 [CSIPHY2_RESET] = { 0x0210, 31 },
2951 [CSI_PIX1_RESET] = { 0x0210, 30 },
2952 [CSIPHY0_RESET] = { 0x0210, 29 },
2953 [CSIPHY1_RESET] = { 0x0210, 28 },
2954 [CSI_RDI_RESET] = { 0x0210, 27 },
2955 [CSI_PIX_RESET] = { 0x0210, 26 },
2956 [DSI2_RESET] = { 0x0210, 25 },
2957 [VFE_CSI_RESET] = { 0x0210, 24 },
2958 [MDP_RESET] = { 0x0210, 21 },
2959 [AMP_RESET] = { 0x0210, 20 },
2960 [JPEGD_RESET] = { 0x0210, 19 },
2961 [CSI1_RESET] = { 0x0210, 18 },
2962 [VPE_RESET] = { 0x0210, 17 },
2963 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2964 [VFE_RESET] = { 0x0210, 15 },
2965 [GFX3D_RESET] = { 0x0210, 12 },
2966 [HDMI_RESET] = { 0x0210, 11 },
2967 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2968 [IJPEG_RESET] = { 0x0210, 9 },
2969 [CSI0_RESET] = { 0x0210, 8 },
2970 [DSI_RESET] = { 0x0210, 7 },
2971 [VCODEC_RESET] = { 0x0210, 6 },
2972 [MDP_TV_RESET] = { 0x0210, 4 },
2973 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2974 [ROT_RESET] = { 0x0210, 2 },
2975 [TV_HDMI_RESET] = { 0x0210, 1 },
2976 [VCAP_NPL_RESET] = { 0x0214, 4 },
2977 [VCAP_RESET] = { 0x0214, 3 },
2978 [CSI2_RESET] = { 0x0214, 2 },
2979 [CSI_RDI1_RESET] = { 0x0214, 1 },
2980 [CSI_RDI2_RESET] = { 0x0214 },
2987 .max_register = 0x334,
2995 .max_register = 0x350,
3037 gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map; in mmcc_msm8960_probe()