Lines Matching +full:0 +full:x2104
25 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
33 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0)
39 UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
42 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
45 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
48 UNIPHIER_CLK_GATE("hsc", (idx), NULL, 0x210c, 9)
51 UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
54 UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
58 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
62 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
66 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0)
70 UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
74 UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
77 UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x2104, 12)
80 UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x210c, 6)
87 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
104 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
112 UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5),
114 UNIPHIER_CLK_GATE("ether-phy", 10, "ref", 0x2260, 0),
116 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
121 UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 18),
122 UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x2104, 19),
131 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
146 UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
154 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
156 UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x2108, 2),
163 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),
171 /* GIO is always clock-enabled: no function for 0x2104 bit6 */
172 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
174 /* The document mentions 0x2104 bit 18, but not functional */
175 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x2104, 19),
178 UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x2104, 20),
180 UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 22),
190 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
209 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
212 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
225 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
236 /* GIO is always clock-enabled: no function for 0x210c bit5 */
241 UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
242 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 12),
243 UNIPHIER_CLK_GATE("usb30-hsphy1", 17, NULL, 0x210c, 13),
246 UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 4),
254 UNIPHIER_CLK_CPUGEAR("cpu-ca72", 32, 0x8000, 0xf, 8,
257 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
260 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
270 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
277 UNIPHIER_CLK_GATE("ether0", 6, NULL, 0x210c, 9),
278 UNIPHIER_CLK_GATE("ether1", 7, NULL, 0x210c, 10),
279 UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4), /* =GIO0 */
280 UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5), /* =GIO1 */
281 UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6), /* =GIO1-1 */
282 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 16),
283 UNIPHIER_CLK_GATE("usb30-ssphy0", 17, NULL, 0x210c, 18),
284 UNIPHIER_CLK_GATE("usb30-ssphy1", 18, NULL, 0x210c, 20),
285 UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x210c, 17),
286 UNIPHIER_CLK_GATE("usb31-ssphy0", 21, NULL, 0x210c, 19),
287 UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 3),
288 UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7),
289 UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8),
290 UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21),
295 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
298 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,