Lines Matching +full:0 +full:x4800

20 #define REVISION_MASK				0xF
23 #define AM33XX_800M_ARM_MPU_MAX_FREQ		0x1E2F
24 #define AM43XX_600M_ARM_MPU_MAX_FREQ		0xFFA
32 #define DRA7_EFUSE_NOM_MPU_OPP			BIT(0)
37 #define OMAP3_CONTROL_DEVICE_STATUS		0x4800244C
38 #define OMAP3_CONTROL_IDCODE			0x4830A204
39 #define OMAP34xx_ProdID_SKUID			0x4830A20C
40 #define OMAP3_SYSCON_BASE	(0x48000000 + 0x2000 + 0x270)
111 	.efuse_offset = 0x07fc,
112 	.efuse_mask = 0x1fff,
113 	.rev_offset = 0x600,
120 	.efuse_offset = 0x0610,
121 	.efuse_mask = 0x3f,
122 	.rev_offset = 0x600,
128 	.efuse_offset = 0x020c,
129 	.efuse_mask = 0xf80000,
131 	.rev_offset = 0x204,
137  *  CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
138  *  Control OMAP Status Register 15:0 (Address 0x4800 244C)
146  *  Register 0x4830A20C [ProdID.SKUID] [0:3]
147  *    0x0 for normal 600/430MHz device.
148  *    0x8 for 720/520MHz device.
163  *  CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
164  *  Control Device Status Register 15:0 (Address 0x4800 244C)
168  *     0 800/600 MHz
172  *  There is no 0x4830A20C [ProdID.SKUID] register (exists but
173  *    seems to always read as 0).
196 	.efuse_shift = 0,
197 	.efuse_mask = 0,
241 	return 0;  in ti_cpufreq_get_efuse()
279 	return 0;  in ti_cpufreq_get_rev()
295 	return 0;  in ti_cpufreq_setup_syscon_register()
342 	opp_data->cpu_dev = get_cpu_device(0);  in ti_cpufreq_probe()
362 	 *	0 - SoC Revision  in ti_cpufreq_probe()
365 	ret = ti_cpufreq_get_rev(opp_data, &version[0]);  in ti_cpufreq_probe()
401 	platform_device_register_simple("cpufreq-dt", -1, NULL, 0);  in ti_cpufreq_probe()
403 	return 0;  in ti_cpufreq_probe()
421 	return 0;  in ti_cpufreq_init()