Lines Matching +full:co +full:- +full:processors
1 # SPDX-License-Identifier: GPL-2.0-only
8 processors. This option alone does not add any kernel code.
20 Some VIA processors come with an integrated crypto engine
39 called padlock-aes.
50 Available in VIA C7 and newer processors.
53 called padlock-sha.
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
65 will be called geode-aes.
142 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
152 SHA256 secure hash standard (DFIPS 180-2).
194 DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
206 AES cipher algorithms (FIPS-197).
223 and uses triple-DES to generate secure random numbers like the
224 ANSI X9.17 standard. User-space programs access the
225 pseudo-random-number device through the char device /dev/prandom.
240 tristate "CRC-32 algorithms"
247 can optimize the computation of CRC-32 (IEEE 802.3 Ethernet)
248 and CRC-32C (Castagnoli).
264 sub-units. One set provides the Modular Arithmetic Unit,
301 The Freescale SEC is present on PowerQUICC 'E' processors, such
354 This option provides the kernel-side support for the TRNG hardware
361 OMAP processors have various crypto HW accelerators. Select this if
376 OMAP processors have MD5/SHA1/SHA2 hw accelerator. Select this if you
390 OMAP processors have AES module accelerator. Select this if you
400 OMAP processors have DES/3DES module accelerator. Select this if you
441 This driver provides kernel-side support through the
446 module will be called exynos-rng.
471 needed for small and zero-size messages.
480 coprocessor that is in IBM PowerPC P7+ or later processors. This
489 tristate "Driver for ST-Ericsson UX500 crypto hardware acceleration"
492 Driver for ST-Ericsson UX500 crypto engine.
503 Some Atmel processors can combine the AES and SHA hw accelerators
517 Some Atmel processors have AES hw accelerator.
522 will be called atmel-aes.
530 Some Atmel processors have DES/TDES hw accelerator.
535 will be called atmel-tdes.
542 Some Atmel processors have SHA1/SHA224/SHA256/SHA384/SHA512
548 will be called atmel-sha.
566 will be called atmel-ecc.
581 will be called atmel-sha204a.
605 co-processor on the die.
608 will be called mxs-dcp.
654 (default), hashes-only, or skciphers-only.
657 multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the
661 algorithms, sharing the load with the CPU. Enabling skciphers-only
670 - AES (CBC, CTR, ECB, XTS)
671 - 3DES (CBC, ECB)
672 - DES (CBC, ECB)
673 - SHA1, HMAC-SHA1
674 - SHA256, HMAC-SHA256
677 bool "Symmetric-key ciphers only"
680 Enable symmetric-key ciphers only:
681 - AES (CBC, CTR, ECB, XTS)
682 - 3DES (ECB, CBC)
683 - DES (ECB, CBC)
690 - SHA1, HMAC-SHA1
691 - SHA256, HMAC-SHA256
705 Considering the 256-bit ciphers, software is 2-3 times faster than
706 qce at 256-bytes, 30% faster at 512, and about even at 768-bytes.
707 With 128-bit keys, the break-even point would be around 1024-bytes.
710 cost in CPU usage. The minimum recommended setting is 16-bytes
711 (1 AES block), since AES-GCM will fail if you set it lower.
714 Note that 192-bit keys are not supported by the hardware and are
727 module will be called qcom-rng. If unsure, say N.
776 Xilinx ZynqMP has AES-GCM engine used for symmetric key
834 This driver interfaces with the SafeXcel EIP-97 and EIP-197 cryptographic
838 Additionally, it accelerates combined AES-CBC/HMAC-SHA AEAD operations.
841 tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration."
854 Enables the driver for the on-chip crypto accelerator
860 tristate "Support for ARM TrustZone CryptoCell family of security processors"
882 TrustZone CryptoCell family of processors. Currently the