Lines Matching +full:hardware +full:- +full:protected
1 # SPDX-License-Identifier: GPL-2.0-only
4 bool "Hardware crypto devices"
7 Say Y here to get to see options for hardware crypto devices and
39 called padlock-aes.
53 called padlock-sha.
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
65 will be called geode-aes.
104 down the use of the available crypto hardware.
107 tristate "Kernel API for protected key handling"
112 for creation and handling of protected keys. Other parts of the
118 Please note that creation of protected keys from secure keys
130 This is the s390 hardware accelerated implementation of the
131 AES cipher algorithms for use with protected key.
134 for example to use protected key encrypted devices.
141 This is the s390 hardware accelerated implementation of the
142 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
151 This is the s390 hardware accelerated implementation of the
152 SHA256 secure hash standard (DFIPS 180-2).
161 This is the s390 hardware accelerated implementation of the
171 This is the s390 hardware accelerated implementation of the
181 This is the s390 hardware accelerated implementation of the
193 This is the s390 hardware accelerated implementation of the
194 DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
196 As of z990 the ECB and CBC mode are hardware accelerated.
197 As of z196 the CTR mode is hardware accelerated.
205 This is the s390 hardware accelerated implementation of the
206 AES cipher algorithms (FIPS-197).
208 As of z9 the ECB and CBC modes are hardware accelerated
210 As of z10 the ECB and CBC modes are hardware accelerated
212 As of z196 the CTR mode is hardware accelerated for all AES
213 key sizes and XTS mode is hardware accelerated for 256 and
223 and uses triple-DES to generate secure random numbers like the
224 ANSI X9.17 standard. User-space programs access the
225 pseudo-random-number device through the char device /dev/prandom.
234 This is the s390 hardware accelerated implementation of GHASH,
240 tristate "CRC-32 algorithms"
245 Select this option if you want to use hardware accelerated
247 can optimize the computation of CRC-32 (IEEE 802.3 Ethernet)
248 and CRC-32C (Castagnoli).
264 sub-units. One set provides the Modular Arithmetic Unit,
326 tristate "Driver for IXP4xx crypto hardware acceleration"
354 This option provides the kernel-side support for the TRNG hardware
419 This option enables support for the hardware offload engines in the
441 This driver provides kernel-side support through the
442 cryptographic API for the pseudo random number generator hardware
446 module will be called exynos-rng.
471 needed for small and zero-size messages.
479 This enables support for the NX hardware cryptographic accelerator
489 tristate "Driver for ST-Ericsson UX500 crypto hardware acceleration"
492 Driver for ST-Ericsson UX500 crypto engine.
522 will be called atmel-aes.
535 will be called atmel-tdes.
548 will be called atmel-sha.
566 will be called atmel-ecc.
581 will be called atmel-sha204a.
605 co-processor on the die.
608 will be called mxs-dcp.
628 hardware. To compile this driver as a module, choose M here. The
654 (default), hashes-only, or skciphers-only.
657 multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the
661 algorithms, sharing the load with the CPU. Enabling skciphers-only
670 - AES (CBC, CTR, ECB, XTS)
671 - 3DES (CBC, ECB)
672 - DES (CBC, ECB)
673 - SHA1, HMAC-SHA1
674 - SHA256, HMAC-SHA256
677 bool "Symmetric-key ciphers only"
680 Enable symmetric-key ciphers only:
681 - AES (CBC, CTR, ECB, XTS)
682 - 3DES (ECB, CBC)
683 - DES (ECB, CBC)
690 - SHA1, HMAC-SHA1
691 - SHA256, HMAC-SHA256
704 Small blocks are processed faster in software than hardware.
705 Considering the 256-bit ciphers, software is 2-3 times faster than
706 qce at 256-bytes, 30% faster at 512, and about even at 768-bytes.
707 With 128-bit keys, the break-even point would be around 1024-bytes.
710 cost in CPU usage. The minimum recommended setting is 16-bytes
711 (1 AES block), since AES-GCM will fail if you set it lower.
712 Setting this to zero will send all requests to the hardware.
714 Note that 192-bit keys are not supported by the hardware and are
716 are done by the hardware.
724 Generator hardware found on Qualcomm SoCs.
727 module will be called qcom-rng. If unsure, say N.
738 tristate "Imagination Technologies hardware hash accelerator"
746 hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256
766 This driver interfaces with the hardware crypto accelerator.
776 Xilinx ZynqMP has AES-GCM engine used for symmetric key
792 This driver allows you to utilize the hardware crypto accelerator
834 This driver interfaces with the SafeXcel EIP-97 and EIP-197 cryptographic
838 Additionally, it accelerates combined AES-CBC/HMAC-SHA AEAD operations.
841 tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration."
854 Enables the driver for the on-chip crypto accelerator
884 Choose this if you wish to use hardware acceleration of
908 used for crypto offload. Select this if you want to use hardware