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Lines Matching full:dividers

44 	struct atom_clock_dividers dividers;  in rv730_populate_sclk_value()  local
57 engine_clock, false, &dividers); in rv730_populate_sclk_value()
61 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()
63 if (dividers.enable_post_div) in rv730_populate_sclk_value()
64 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
65 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value()
74 if (dividers.enable_post_div) in rv730_populate_sclk_value()
79 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv730_populate_sclk_value()
80 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value()
81 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_sclk_value()
130 struct atom_clock_dividers dividers; in rv730_populate_mclk_value() local
135 memory_clock, false, &dividers); in rv730_populate_mclk_value()
139 reference_divider = dividers.ref_div + 1; in rv730_populate_mclk_value()
141 if (dividers.enable_post_div) in rv730_populate_mclk_value()
142 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_mclk_value()
143 (dividers.post_div & 0xf) + 2; in rv730_populate_mclk_value()
148 if (dividers.enable_post_div) in rv730_populate_mclk_value()
154 mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div); in rv730_populate_mclk_value()
155 mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_mclk_value()
156 mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_mclk_value()
159 mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div); in rv730_populate_mclk_value()
160 if (dividers.enable_dithen) in rv730_populate_mclk_value()
173 u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000); in rv730_populate_mclk_value()