Lines Matching +full:master +full:- +full:dsi
1 // SPDX-License-Identifier: GPL-2.0+
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
40 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
92 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
95 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
96 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
230 /* dual-channel */
306 return -EINVAL; in max_mbps_to_parameter()
309 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) in dsi_write() argument
311 writel(val, dsi->base + reg); in dsi_write()
314 static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg) in dsi_read() argument
316 return readl(dsi->base + reg); in dsi_read()
319 static inline void dsi_set(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 mask) in dsi_set() argument
321 dsi_write(dsi, reg, dsi_read(dsi, reg) | mask); in dsi_set()
324 static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg, in dsi_update_bits() argument
327 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); in dsi_update_bits()
330 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, in dw_mipi_dsi_phy_write() argument
339 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
341 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | in dw_mipi_dsi_phy_write()
344 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
346 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | in dw_mipi_dsi_phy_write()
349 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
353 * ns2bc - Nanoseconds to byte clock cycles
355 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) in ns2bc() argument
357 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); in ns2bc()
361 * ns2ui - Nanoseconds to UI time periods
363 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) in ns2ui() argument
365 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); in ns2ui()
370 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_init() local
373 if (dsi->phy) in dw_mipi_dsi_phy_init()
379 * 000 - between 80 and 200 MHz in dw_mipi_dsi_phy_init()
380 * 001 - between 200 and 300 MHz in dw_mipi_dsi_phy_init()
381 * 010 - between 300 and 500 MHz in dw_mipi_dsi_phy_init()
382 * 011 - between 500 and 700 MHz in dw_mipi_dsi_phy_init()
383 * 100 - between 700 and 900 MHz in dw_mipi_dsi_phy_init()
384 * 101 - between 900 and 1100 MHz in dw_mipi_dsi_phy_init()
385 * 110 - between 1100 and 1300 MHz in dw_mipi_dsi_phy_init()
386 * 111 - between 1300 and 1500 MHz in dw_mipi_dsi_phy_init()
388 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; in dw_mipi_dsi_phy_init()
390 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_phy_init()
392 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_phy_init()
394 dsi->lane_mbps); in dw_mipi_dsi_phy_init()
398 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
400 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); in dw_mipi_dsi_phy_init()
404 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL, in dw_mipi_dsi_phy_init()
410 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS, in dw_mipi_dsi_phy_init()
412 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL, in dw_mipi_dsi_phy_init()
416 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, in dw_mipi_dsi_phy_init()
419 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
420 INPUT_DIVIDER(dsi->input_div)); in dw_mipi_dsi_phy_init()
421 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
422 LOOP_DIV_LOW_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
430 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, in dw_mipi_dsi_phy_init()
432 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
433 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
435 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, in dw_mipi_dsi_phy_init()
438 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, in dw_mipi_dsi_phy_init()
440 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, in dw_mipi_dsi_phy_init()
443 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL, in dw_mipi_dsi_phy_init()
447 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, in dw_mipi_dsi_phy_init()
450 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, in dw_mipi_dsi_phy_init()
455 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
456 TLP_PROGRAM_EN | ns2bc(dsi, 500)); in dw_mipi_dsi_phy_init()
457 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
458 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); in dw_mipi_dsi_phy_init()
459 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
460 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); in dw_mipi_dsi_phy_init()
461 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
462 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); in dw_mipi_dsi_phy_init()
463 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
464 BIT(5) | ns2bc(dsi, 100)); in dw_mipi_dsi_phy_init()
465 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL, in dw_mipi_dsi_phy_init()
466 BIT(5) | (ns2bc(dsi, 60) + 7)); in dw_mipi_dsi_phy_init()
468 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
469 TLP_PROGRAM_EN | ns2bc(dsi, 500)); in dw_mipi_dsi_phy_init()
470 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
471 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20)); in dw_mipi_dsi_phy_init()
472 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
473 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); in dw_mipi_dsi_phy_init()
474 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
475 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); in dw_mipi_dsi_phy_init()
476 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
477 BIT(5) | ns2bc(dsi, 100)); in dw_mipi_dsi_phy_init()
479 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
486 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_power_on() local
489 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); in dw_mipi_dsi_phy_power_on()
491 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); in dw_mipi_dsi_phy_power_on()
495 phy_configure(dsi->phy, &dsi->phy_opts); in dw_mipi_dsi_phy_power_on()
496 phy_power_on(dsi->phy); in dw_mipi_dsi_phy_power_on()
501 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_power_off() local
503 phy_power_off(dsi->phy); in dw_mipi_dsi_phy_power_off()
511 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_get_lane_mbps() local
515 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; in dw_mipi_dsi_get_lane_mbps()
523 dsi->format = format; in dw_mipi_dsi_get_lane_mbps()
524 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in dw_mipi_dsi_get_lane_mbps()
526 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
528 dsi->format); in dw_mipi_dsi_get_lane_mbps()
532 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); in dw_mipi_dsi_get_lane_mbps()
539 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
544 if (dsi->phy) { in dw_mipi_dsi_get_lane_mbps()
545 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, in dw_mipi_dsi_get_lane_mbps()
547 &dsi->phy_opts.mipi_dphy); in dw_mipi_dsi_get_lane_mbps()
548 dsi->lane_mbps = target_mbps; in dw_mipi_dsi_get_lane_mbps()
549 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
554 fin = clk_get_rate(dsi->pllref_clk); in dw_mipi_dsi_get_lane_mbps()
573 * Due to the use of a "by 2 pre-scaler," the range of the in dw_mipi_dsi_get_lane_mbps()
587 delta = abs(fout - tmp); in dw_mipi_dsi_get_lane_mbps()
597 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); in dw_mipi_dsi_get_lane_mbps()
598 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
599 dsi->input_div = best_prediv; in dw_mipi_dsi_get_lane_mbps()
600 dsi->feedback_div = best_fbdiv; in dw_mipi_dsi_get_lane_mbps()
602 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); in dw_mipi_dsi_get_lane_mbps()
603 return -EINVAL; in dw_mipi_dsi_get_lane_mbps()
625 /* Table A-3 High-Speed Transition Times */
679 i--; in dw_mipi_dsi_phy_get_timing()
694 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) in dw_mipi_dsi_rockchip_config() argument
696 if (dsi->cdata->lanecfg1_grf_reg) in dw_mipi_dsi_rockchip_config()
697 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, in dw_mipi_dsi_rockchip_config()
698 dsi->cdata->lanecfg1); in dw_mipi_dsi_rockchip_config()
700 if (dsi->cdata->lanecfg2_grf_reg) in dw_mipi_dsi_rockchip_config()
701 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, in dw_mipi_dsi_rockchip_config()
702 dsi->cdata->lanecfg2); in dw_mipi_dsi_rockchip_config()
704 if (dsi->cdata->enable_grf_reg) in dw_mipi_dsi_rockchip_config()
705 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, in dw_mipi_dsi_rockchip_config()
706 dsi->cdata->enable); in dw_mipi_dsi_rockchip_config()
709 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, in dw_mipi_dsi_rockchip_set_lcdsel() argument
712 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, in dw_mipi_dsi_rockchip_set_lcdsel()
713 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); in dw_mipi_dsi_rockchip_set_lcdsel()
722 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); in dw_mipi_dsi_encoder_atomic_check() local
724 switch (dsi->format) { in dw_mipi_dsi_encoder_atomic_check()
726 s->output_mode = ROCKCHIP_OUT_MODE_P888; in dw_mipi_dsi_encoder_atomic_check()
729 s->output_mode = ROCKCHIP_OUT_MODE_P666; in dw_mipi_dsi_encoder_atomic_check()
732 s->output_mode = ROCKCHIP_OUT_MODE_P565; in dw_mipi_dsi_encoder_atomic_check()
736 return -EINVAL; in dw_mipi_dsi_encoder_atomic_check()
739 s->output_type = DRM_MODE_CONNECTOR_DSI; in dw_mipi_dsi_encoder_atomic_check()
740 if (dsi->slave) in dw_mipi_dsi_encoder_atomic_check()
741 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL; in dw_mipi_dsi_encoder_atomic_check()
748 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); in dw_mipi_dsi_encoder_enable() local
751 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, in dw_mipi_dsi_encoder_enable()
752 &dsi->encoder); in dw_mipi_dsi_encoder_enable()
756 pm_runtime_get_sync(dsi->dev); in dw_mipi_dsi_encoder_enable()
757 if (dsi->slave) in dw_mipi_dsi_encoder_enable()
758 pm_runtime_get_sync(dsi->slave->dev); in dw_mipi_dsi_encoder_enable()
765 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
767 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_encoder_enable()
771 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux); in dw_mipi_dsi_encoder_enable()
772 if (dsi->slave) in dw_mipi_dsi_encoder_enable()
773 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); in dw_mipi_dsi_encoder_enable()
775 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
780 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); in dw_mipi_dsi_encoder_disable() local
782 if (dsi->slave) in dw_mipi_dsi_encoder_disable()
783 pm_runtime_put(dsi->slave->dev); in dw_mipi_dsi_encoder_disable()
784 pm_runtime_put(dsi->dev); in dw_mipi_dsi_encoder_disable()
794 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, in rockchip_dsi_drm_create_encoder() argument
797 struct drm_encoder *encoder = &dsi->encoder; in rockchip_dsi_drm_create_encoder()
800 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, in rockchip_dsi_drm_create_encoder()
801 dsi->dev->of_node); in rockchip_dsi_drm_create_encoder()
815 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) in dw_mipi_dsi_rockchip_find_second() argument
820 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); in dw_mipi_dsi_rockchip_find_second()
822 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); in dw_mipi_dsi_rockchip_find_second()
827 match->compatible))) { in dw_mipi_dsi_rockchip_find_second()
831 if (node == dsi->dev->of_node) in dw_mipi_dsi_rockchip_find_second()
838 /* same display device in port1-ep0 for both */ in dw_mipi_dsi_rockchip_find_second()
855 return ERR_PTR(-EPROBE_DEFER); in dw_mipi_dsi_rockchip_find_second()
860 return ERR_PTR(-EPROBE_DEFER); in dw_mipi_dsi_rockchip_find_second()
863 return &pdev->dev; in dw_mipi_dsi_rockchip_find_second()
875 struct device *master, in dw_mipi_dsi_rockchip_bind() argument
878 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); in dw_mipi_dsi_rockchip_bind() local
884 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_bind()
889 master1 = of_property_read_bool(dsi->dev->of_node, in dw_mipi_dsi_rockchip_bind()
890 "clock-master"); in dw_mipi_dsi_rockchip_bind()
891 master2 = of_property_read_bool(second->of_node, in dw_mipi_dsi_rockchip_bind()
892 "clock-master"); in dw_mipi_dsi_rockchip_bind()
895 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); in dw_mipi_dsi_rockchip_bind()
896 return -EINVAL; in dw_mipi_dsi_rockchip_bind()
900 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); in dw_mipi_dsi_rockchip_bind()
901 return -EINVAL; in dw_mipi_dsi_rockchip_bind()
904 /* we are the slave in dual-DSI */ in dw_mipi_dsi_rockchip_bind()
906 dsi->is_slave = true; in dw_mipi_dsi_rockchip_bind()
910 dsi->slave = dev_get_drvdata(second); in dw_mipi_dsi_rockchip_bind()
911 if (!dsi->slave) { in dw_mipi_dsi_rockchip_bind()
913 return -ENODEV; in dw_mipi_dsi_rockchip_bind()
916 dsi->slave->is_slave = true; in dw_mipi_dsi_rockchip_bind()
917 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); in dw_mipi_dsi_rockchip_bind()
921 ret = clk_prepare_enable(dsi->pllref_clk); in dw_mipi_dsi_rockchip_bind()
928 * With the GRF clock running, write lane and dual-mode configurations in dw_mipi_dsi_rockchip_bind()
931 * commands over DSI. in dw_mipi_dsi_rockchip_bind()
933 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
935 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_rockchip_bind()
939 dw_mipi_dsi_rockchip_config(dsi); in dw_mipi_dsi_rockchip_bind()
940 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
941 dw_mipi_dsi_rockchip_config(dsi->slave); in dw_mipi_dsi_rockchip_bind()
943 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
945 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev); in dw_mipi_dsi_rockchip_bind()
951 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder); in dw_mipi_dsi_rockchip_bind()
961 struct device *master, in dw_mipi_dsi_rockchip_unbind() argument
964 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); in dw_mipi_dsi_rockchip_unbind() local
966 if (dsi->is_slave) in dw_mipi_dsi_rockchip_unbind()
969 dw_mipi_dsi_unbind(dsi->dmd); in dw_mipi_dsi_rockchip_unbind()
971 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_unbind()
982 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_rockchip_host_attach() local
986 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_attach()
988 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", in dw_mipi_dsi_rockchip_host_attach()
993 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_host_attach()
1012 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_rockchip_host_detach() local
1015 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_host_detach()
1019 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_detach()
1031 struct device *dev = &pdev->dev; in dw_mipi_dsi_rockchip_probe()
1032 struct device_node *np = dev->of_node; in dw_mipi_dsi_rockchip_probe()
1033 struct dw_mipi_dsi_rockchip *dsi; in dw_mipi_dsi_rockchip_probe() local
1039 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); in dw_mipi_dsi_rockchip_probe()
1040 if (!dsi) in dw_mipi_dsi_rockchip_probe()
1041 return -ENOMEM; in dw_mipi_dsi_rockchip_probe()
1044 dsi->base = devm_ioremap_resource(dev, res); in dw_mipi_dsi_rockchip_probe()
1045 if (IS_ERR(dsi->base)) { in dw_mipi_dsi_rockchip_probe()
1046 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); in dw_mipi_dsi_rockchip_probe()
1047 return PTR_ERR(dsi->base); in dw_mipi_dsi_rockchip_probe()
1052 if (cdata[i].reg == res->start) { in dw_mipi_dsi_rockchip_probe()
1053 dsi->cdata = &cdata[i]; in dw_mipi_dsi_rockchip_probe()
1060 if (!dsi->cdata) { in dw_mipi_dsi_rockchip_probe()
1061 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); in dw_mipi_dsi_rockchip_probe()
1062 return -EINVAL; in dw_mipi_dsi_rockchip_probe()
1066 dsi->phy = devm_phy_optional_get(dev, "dphy"); in dw_mipi_dsi_rockchip_probe()
1067 if (IS_ERR(dsi->phy)) { in dw_mipi_dsi_rockchip_probe()
1068 ret = PTR_ERR(dsi->phy); in dw_mipi_dsi_rockchip_probe()
1073 dsi->pllref_clk = devm_clk_get(dev, "ref"); in dw_mipi_dsi_rockchip_probe()
1074 if (IS_ERR(dsi->pllref_clk)) { in dw_mipi_dsi_rockchip_probe()
1075 if (dsi->phy) { in dw_mipi_dsi_rockchip_probe()
1080 dsi->pllref_clk = NULL; in dw_mipi_dsi_rockchip_probe()
1082 ret = PTR_ERR(dsi->pllref_clk); in dw_mipi_dsi_rockchip_probe()
1090 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { in dw_mipi_dsi_rockchip_probe()
1091 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); in dw_mipi_dsi_rockchip_probe()
1092 if (IS_ERR(dsi->phy_cfg_clk)) { in dw_mipi_dsi_rockchip_probe()
1093 ret = PTR_ERR(dsi->phy_cfg_clk); in dw_mipi_dsi_rockchip_probe()
1100 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { in dw_mipi_dsi_rockchip_probe()
1101 dsi->grf_clk = devm_clk_get(dev, "grf"); in dw_mipi_dsi_rockchip_probe()
1102 if (IS_ERR(dsi->grf_clk)) { in dw_mipi_dsi_rockchip_probe()
1103 ret = PTR_ERR(dsi->grf_clk); in dw_mipi_dsi_rockchip_probe()
1109 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in dw_mipi_dsi_rockchip_probe()
1110 if (IS_ERR(dsi->grf_regmap)) { in dw_mipi_dsi_rockchip_probe()
1111 DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n"); in dw_mipi_dsi_rockchip_probe()
1112 return PTR_ERR(dsi->grf_regmap); in dw_mipi_dsi_rockchip_probe()
1115 dsi->dev = dev; in dw_mipi_dsi_rockchip_probe()
1116 dsi->pdata.base = dsi->base; in dw_mipi_dsi_rockchip_probe()
1117 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; in dw_mipi_dsi_rockchip_probe()
1118 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; in dw_mipi_dsi_rockchip_probe()
1119 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; in dw_mipi_dsi_rockchip_probe()
1120 dsi->pdata.priv_data = dsi; in dw_mipi_dsi_rockchip_probe()
1121 platform_set_drvdata(pdev, dsi); in dw_mipi_dsi_rockchip_probe()
1123 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); in dw_mipi_dsi_rockchip_probe()
1124 if (IS_ERR(dsi->dmd)) { in dw_mipi_dsi_rockchip_probe()
1125 ret = PTR_ERR(dsi->dmd); in dw_mipi_dsi_rockchip_probe()
1126 if (ret != -EPROBE_DEFER) in dw_mipi_dsi_rockchip_probe()
1135 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_probe()
1141 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev); in dw_mipi_dsi_rockchip_remove() local
1143 dw_mipi_dsi_remove(dsi->dmd); in dw_mipi_dsi_rockchip_remove()
1234 .compatible = "rockchip,px30-mipi-dsi",
1237 .compatible = "rockchip,rk3288-mipi-dsi",
1240 .compatible = "rockchip,rk3399-mipi-dsi",
1252 .name = "dw-mipi-dsi-rockchip",
1254 * For dual-DSI display, one DSI pokes at the other DSI's