Lines Matching +full:i2c +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
14 #include <linux/i2c.h>
33 #define I2C_TRANSAC_COMP (1 << 0)
34 #define I2C_TRANSAC_START (1 << 0)
37 #define I2C_DCM_DISABLE 0x0000
38 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
39 #define I2C_IO_CONFIG_PUSH_PULL 0x0000
40 #define I2C_SOFT_RST 0x0001
41 #define I2C_HANDSHAKE_RST 0x0020
42 #define I2C_FIFO_ADDR_CLR 0x0001
43 #define I2C_DELAY_LEN 0x0002
44 #define I2C_ST_START_CON 0x8001
45 #define I2C_FS_START_CON 0x1800
46 #define I2C_TIME_CLR_VALUE 0x0000
47 #define I2C_TIME_DEFAULT_VALUE 0x0003
48 #define I2C_WRRD_TRANAC_VALUE 0x0002
49 #define I2C_RD_TRANAC_VALUE 0x0001
50 #define I2C_SCL_MIS_COMP_VALUE 0x0000
51 #define I2C_CHN_CLR_FLAG 0x0000
53 #define I2C_DMA_CON_TX 0x0000
54 #define I2C_DMA_CON_RX 0x0001
55 #define I2C_DMA_ASYNC_MODE 0x0004
56 #define I2C_DMA_SKIP_CONFIG 0x0010
57 #define I2C_DMA_DIR_CHANGE 0x0200
58 #define I2C_DMA_START_EN 0x0001
59 #define I2C_DMA_INT_FLAG_NONE 0x0000
60 #define I2C_DMA_CLR_FLAG 0x0000
61 #define I2C_DMA_WARM_RST 0x0001
62 #define I2C_DMA_HARD_RST 0x0002
63 #define I2C_DMA_HANDSHAKE_RST 0x0004
73 #define I2C_CONTROL_RS (0x1 << 1)
74 #define I2C_CONTROL_DMA_EN (0x1 << 2)
75 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
76 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
77 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
78 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
79 #define I2C_CONTROL_DMAACK_EN (0x1 << 8)
80 #define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
81 #define I2C_CONTROL_WRAPPER (0x1 << 0)
83 #define I2C_DRV_NAME "i2c-mt65xx"
86 OFFSET_INT_FLAG = 0x0,
87 OFFSET_INT_EN = 0x04,
88 OFFSET_EN = 0x08,
89 OFFSET_RST = 0x0c,
90 OFFSET_CON = 0x18,
91 OFFSET_TX_MEM_ADDR = 0x1c,
92 OFFSET_RX_MEM_ADDR = 0x20,
93 OFFSET_TX_LEN = 0x24,
94 OFFSET_RX_LEN = 0x28,
95 OFFSET_TX_4G_MODE = 0x54,
96 OFFSET_RX_4G_MODE = 0x58,
100 I2C_TRANS_STOP = 0,
145 [OFFSET_DATA_PORT] = 0x0,
146 [OFFSET_SLAVE_ADDR] = 0x4,
147 [OFFSET_INTR_MASK] = 0x8,
148 [OFFSET_INTR_STAT] = 0xc,
149 [OFFSET_CONTROL] = 0x10,
150 [OFFSET_TRANSFER_LEN] = 0x14,
151 [OFFSET_TRANSAC_LEN] = 0x18,
152 [OFFSET_DELAY_LEN] = 0x1c,
153 [OFFSET_TIMING] = 0x20,
154 [OFFSET_START] = 0x24,
155 [OFFSET_EXT_CONF] = 0x28,
156 [OFFSET_FIFO_STAT] = 0x30,
157 [OFFSET_FIFO_THRESH] = 0x34,
158 [OFFSET_FIFO_ADDR_CLR] = 0x38,
159 [OFFSET_IO_CONFIG] = 0x40,
160 [OFFSET_RSV_DEBUG] = 0x44,
161 [OFFSET_HS] = 0x48,
162 [OFFSET_SOFTRESET] = 0x50,
163 [OFFSET_DCM_EN] = 0x54,
164 [OFFSET_PATH_DIR] = 0x60,
165 [OFFSET_DEBUGSTAT] = 0x64,
166 [OFFSET_DEBUGCTRL] = 0x68,
167 [OFFSET_TRANSFER_LEN_AUX] = 0x6c,
168 [OFFSET_CLOCK_DIV] = 0x70,
169 [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74,
170 [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78,
171 [OFFSET_SCL_MIS_COMP_POINT] = 0x7C,
172 [OFFSET_STA_STO_AC_TIMING] = 0x80,
173 [OFFSET_HS_STA_STO_AC_TIMING] = 0x84,
174 [OFFSET_SDA_TIMING] = 0x88,
178 [OFFSET_DATA_PORT] = 0x0,
179 [OFFSET_SLAVE_ADDR] = 0x4,
180 [OFFSET_INTR_MASK] = 0x8,
181 [OFFSET_INTR_STAT] = 0xc,
182 [OFFSET_CONTROL] = 0x10,
183 [OFFSET_TRANSFER_LEN] = 0x14,
184 [OFFSET_TRANSAC_LEN] = 0x18,
185 [OFFSET_DELAY_LEN] = 0x1c,
186 [OFFSET_TIMING] = 0x20,
187 [OFFSET_START] = 0x24,
188 [OFFSET_EXT_CONF] = 0x28,
189 [OFFSET_LTIMING] = 0x2c,
190 [OFFSET_HS] = 0x30,
191 [OFFSET_IO_CONFIG] = 0x34,
192 [OFFSET_FIFO_ADDR_CLR] = 0x38,
193 [OFFSET_SDA_TIMING] = 0x3c,
194 [OFFSET_TRANSFER_LEN_AUX] = 0x44,
195 [OFFSET_CLOCK_DIV] = 0x48,
196 [OFFSET_SOFTRESET] = 0x50,
197 [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
198 [OFFSET_DEBUGSTAT] = 0xe4,
199 [OFFSET_DEBUGCTRL] = 0xe8,
200 [OFFSET_FIFO_STAT] = 0xf4,
201 [OFFSET_FIFO_THRESH] = 0xf8,
202 [OFFSET_DCM_EN] = 0xf88,
233 struct i2c_adapter adap; /* i2c host adapter */
237 /* set in i2c probe */
238 void __iomem *base; /* i2c base addr */
240 struct clk *clk_main; /* main clock for i2c bus */
241 struct clk *clk_dma; /* DMA clock for i2c via DMA */
242 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
243 struct clk *clk_arb; /* Arbitrator clock for i2c */
244 bool have_pmic; /* can use i2c pins from PMIC */
245 bool use_push_pull; /* IO config push-pull mode */
263 * @min_su_sta_ns: min set-up time for a repeated START condition
265 * @min_su_dat_ns: min data set-up time
277 .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER,
284 .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER,
291 .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER,
314 .pmic_i2c = 0,
319 .dma_sync = 0,
320 .ltiming_adjust = 0,
321 .apdma_sync = 0,
328 .pmic_i2c = 0,
330 .auto_restart = 0,
331 .aux_len_reg = 0,
332 .timing_adjust = 0,
333 .dma_sync = 0,
334 .ltiming_adjust = 0,
335 .apdma_sync = 0,
343 .dcm = 0,
344 .auto_restart = 0,
345 .aux_len_reg = 0,
346 .timing_adjust = 0,
347 .dma_sync = 0,
348 .ltiming_adjust = 0,
349 .apdma_sync = 0,
356 .pmic_i2c = 0,
360 .timing_adjust = 0,
361 .dma_sync = 0,
362 .ltiming_adjust = 0,
363 .apdma_sync = 0,
369 .pmic_i2c = 0,
373 .timing_adjust = 0,
374 .dma_sync = 0,
375 .ltiming_adjust = 0,
376 .apdma_sync = 0,
383 .pmic_i2c = 0,
384 .dcm = 0,
390 .apdma_sync = 0,
397 .pmic_i2c = 0,
398 .dcm = 0,
409 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
410 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
411 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
412 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
413 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
414 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
415 { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
420 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg) in mtk_i2c_readw() argument
422 return readw(i2c->base + i2c->dev_comp->regs[reg]); in mtk_i2c_readw()
425 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val, in mtk_i2c_writew() argument
428 writew(val, i2c->base + i2c->dev_comp->regs[reg]); in mtk_i2c_writew()
431 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c) in mtk_i2c_clock_enable() argument
435 ret = clk_prepare_enable(i2c->clk_dma); in mtk_i2c_clock_enable()
439 ret = clk_prepare_enable(i2c->clk_main); in mtk_i2c_clock_enable()
443 if (i2c->have_pmic) { in mtk_i2c_clock_enable()
444 ret = clk_prepare_enable(i2c->clk_pmic); in mtk_i2c_clock_enable()
449 if (i2c->clk_arb) { in mtk_i2c_clock_enable()
450 ret = clk_prepare_enable(i2c->clk_arb); in mtk_i2c_clock_enable()
455 return 0; in mtk_i2c_clock_enable()
458 if (i2c->have_pmic) in mtk_i2c_clock_enable()
459 clk_disable_unprepare(i2c->clk_pmic); in mtk_i2c_clock_enable()
461 clk_disable_unprepare(i2c->clk_main); in mtk_i2c_clock_enable()
463 clk_disable_unprepare(i2c->clk_dma); in mtk_i2c_clock_enable()
468 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) in mtk_i2c_clock_disable() argument
470 if (i2c->clk_arb) in mtk_i2c_clock_disable()
471 clk_disable_unprepare(i2c->clk_arb); in mtk_i2c_clock_disable()
473 if (i2c->have_pmic) in mtk_i2c_clock_disable()
474 clk_disable_unprepare(i2c->clk_pmic); in mtk_i2c_clock_disable()
476 clk_disable_unprepare(i2c->clk_main); in mtk_i2c_clock_disable()
477 clk_disable_unprepare(i2c->clk_dma); in mtk_i2c_clock_disable()
480 static void mtk_i2c_init_hw(struct mtk_i2c *i2c) in mtk_i2c_init_hw() argument
486 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START); in mtk_i2c_init_hw()
487 intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); in mtk_i2c_init_hw()
488 mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT); in mtk_i2c_init_hw()
490 if (i2c->dev_comp->apdma_sync) { in mtk_i2c_init_hw()
491 writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
493 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
496 i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
497 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST, in mtk_i2c_init_hw()
500 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
501 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET); in mtk_i2c_init_hw()
503 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
505 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); in mtk_i2c_init_hw()
506 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET); in mtk_i2c_init_hw()
510 if (i2c->use_push_pull) in mtk_i2c_init_hw()
511 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG); in mtk_i2c_init_hw()
513 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG); in mtk_i2c_init_hw()
515 if (i2c->dev_comp->dcm) in mtk_i2c_init_hw()
516 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN); in mtk_i2c_init_hw()
518 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING); in mtk_i2c_init_hw()
519 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS); in mtk_i2c_init_hw()
520 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_init_hw()
521 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING); in mtk_i2c_init_hw()
523 if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ) in mtk_i2c_init_hw()
528 if (i2c->dev_comp->timing_adjust) { in mtk_i2c_init_hw()
529 ext_conf_val = i2c->ac_timing.ext; in mtk_i2c_init_hw()
530 mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div, in mtk_i2c_init_hw()
532 mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE, in mtk_i2c_init_hw()
534 mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing, in mtk_i2c_init_hw()
537 if (i2c->dev_comp->ltiming_adjust) { in mtk_i2c_init_hw()
538 mtk_i2c_writew(i2c, i2c->ac_timing.htiming, in mtk_i2c_init_hw()
540 mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS); in mtk_i2c_init_hw()
541 mtk_i2c_writew(i2c, i2c->ac_timing.ltiming, in mtk_i2c_init_hw()
544 mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio, in mtk_i2c_init_hw()
546 mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio, in mtk_i2c_init_hw()
548 mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop, in mtk_i2c_init_hw()
550 mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop, in mtk_i2c_init_hw()
554 mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF); in mtk_i2c_init_hw()
556 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ in mtk_i2c_init_hw()
557 if (i2c->have_pmic) in mtk_i2c_init_hw()
558 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR); in mtk_i2c_init_hw()
562 if (i2c->dev_comp->dma_sync) in mtk_i2c_init_hw()
565 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); in mtk_i2c_init_hw()
566 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN); in mtk_i2c_init_hw()
588 * Check and Calculate i2c ac-timing
592 * xxx_cnt_div = spec->min_xxx_ns / sample_ns
599 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c, in mtk_i2c_check_ac_timing() argument
607 unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f; in mtk_i2c_check_ac_timing()
611 if (!i2c->dev_comp->timing_adjust) in mtk_i2c_check_ac_timing()
612 return 0; in mtk_i2c_check_ac_timing()
614 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_check_ac_timing()
615 max_sta_cnt = 0x100; in mtk_i2c_check_ac_timing()
619 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_check_ac_timing()
624 su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns); in mtk_i2c_check_ac_timing()
626 return -1; in mtk_i2c_check_ac_timing()
628 low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); in mtk_i2c_check_ac_timing()
632 high_cnt = 2 * step_cnt - low_cnt; in mtk_i2c_check_ac_timing()
638 return -2; in mtk_i2c_check_ac_timing()
641 sda_max = spec->max_hd_dat_ns / sample_ns; in mtk_i2c_check_ac_timing()
643 sda_max = 0; in mtk_i2c_check_ac_timing()
645 sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); in mtk_i2c_check_ac_timing()
647 sda_min = 0; in mtk_i2c_check_ac_timing()
650 return -3; in mtk_i2c_check_ac_timing()
653 if (i2c->dev_comp->ltiming_adjust) { in mtk_i2c_check_ac_timing()
654 i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE | in mtk_i2c_check_ac_timing()
656 i2c->ac_timing.ltiming &= ~GENMASK(15, 9); in mtk_i2c_check_ac_timing()
657 i2c->ac_timing.ltiming |= (sample_cnt << 12) | in mtk_i2c_check_ac_timing()
659 i2c->ac_timing.ext &= ~GENMASK(7, 1); in mtk_i2c_check_ac_timing()
660 i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0); in mtk_i2c_check_ac_timing()
662 i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) | in mtk_i2c_check_ac_timing()
664 i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) | in mtk_i2c_check_ac_timing()
667 i2c->ac_timing.sda_timing &= ~GENMASK(11, 6); in mtk_i2c_check_ac_timing()
668 i2c->ac_timing.sda_timing |= (1 << 12) | in mtk_i2c_check_ac_timing()
671 if (i2c->dev_comp->ltiming_adjust) { in mtk_i2c_check_ac_timing()
672 i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt); in mtk_i2c_check_ac_timing()
673 i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt); in mtk_i2c_check_ac_timing()
674 i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0); in mtk_i2c_check_ac_timing()
676 i2c->ac_timing.scl_hl_ratio = (1 << 12) | in mtk_i2c_check_ac_timing()
678 i2c->ac_timing.sta_stop = (su_sta_cnt << 8) | in mtk_i2c_check_ac_timing()
682 i2c->ac_timing.sda_timing = (1 << 12) | in mtk_i2c_check_ac_timing()
686 return 0; in mtk_i2c_check_ac_timing()
690 * Calculate i2c port speed
697 * less than or equal to i2c->speed_hz. The calculation try to get
700 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, in mtk_i2c_calculate_speed() argument
713 int ret = -EINVAL; in mtk_i2c_calculate_speed()
725 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV in mtk_i2c_calculate_speed()
726 * 0 < step_cnt < max_step_cnt in mtk_i2c_calculate_speed()
737 ret = mtk_i2c_check_ac_timing(i2c, clk_src, in mtk_i2c_calculate_speed()
738 target_speed, step_cnt - 1, sample_cnt - 1); in mtk_i2c_calculate_speed()
751 return -EINVAL; in mtk_i2c_calculate_speed()
760 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed); in mtk_i2c_calculate_speed()
761 return -EINVAL; in mtk_i2c_calculate_speed()
764 *timing_step_cnt = step_cnt - 1; in mtk_i2c_calculate_speed()
765 *timing_sample_cnt = sample_cnt - 1; in mtk_i2c_calculate_speed()
767 return 0; in mtk_i2c_calculate_speed()
770 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) in mtk_i2c_set_speed() argument
782 target_speed = i2c->speed_hz; in mtk_i2c_set_speed()
783 parent_clk /= i2c->clk_src_div; in mtk_i2c_set_speed()
785 if (i2c->dev_comp->timing_adjust) in mtk_i2c_set_speed()
795 ret = mtk_i2c_calculate_speed(i2c, clk_src, in mtk_i2c_set_speed()
799 if (ret < 0) in mtk_i2c_set_speed()
802 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; in mtk_i2c_set_speed()
805 ret = mtk_i2c_calculate_speed(i2c, clk_src, in mtk_i2c_set_speed()
808 if (ret < 0) in mtk_i2c_set_speed()
811 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | in mtk_i2c_set_speed()
814 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_set_speed()
815 i2c->ltiming_reg = in mtk_i2c_set_speed()
819 ret = mtk_i2c_calculate_speed(i2c, clk_src, in mtk_i2c_set_speed()
822 if (ret < 0) in mtk_i2c_set_speed()
825 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; in mtk_i2c_set_speed()
828 i2c->high_speed_reg = I2C_TIME_CLR_VALUE; in mtk_i2c_set_speed()
830 if (i2c->dev_comp->ltiming_adjust) in mtk_i2c_set_speed()
831 i2c->ltiming_reg = in mtk_i2c_set_speed()
838 i2c->ac_timing.inter_clk_div = clk_div - 1; in mtk_i2c_set_speed()
840 return 0; in mtk_i2c_set_speed()
843 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, in mtk_i2c_do_transfer() argument
849 u16 restart_flag = 0; in mtk_i2c_do_transfer()
850 u16 dma_sync = 0; in mtk_i2c_do_transfer()
854 dma_addr_t rpaddr = 0; in mtk_i2c_do_transfer()
855 dma_addr_t wpaddr = 0; in mtk_i2c_do_transfer()
858 i2c->irq_stat = 0; in mtk_i2c_do_transfer()
860 if (i2c->auto_restart) in mtk_i2c_do_transfer()
863 reinit_completion(&i2c->msg_complete); in mtk_i2c_do_transfer()
865 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & in mtk_i2c_do_transfer()
867 if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1)) in mtk_i2c_do_transfer()
870 if (i2c->op == I2C_MASTER_WRRD) in mtk_i2c_do_transfer()
873 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); in mtk_i2c_do_transfer()
876 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR); in mtk_i2c_do_transfer()
879 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | in mtk_i2c_do_transfer()
882 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR); in mtk_i2c_do_transfer()
885 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR | in mtk_i2c_do_transfer()
889 if (i2c->op == I2C_MASTER_WRRD) { in mtk_i2c_do_transfer()
890 if (i2c->dev_comp->aux_len_reg) { in mtk_i2c_do_transfer()
891 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); in mtk_i2c_do_transfer()
892 mtk_i2c_writew(i2c, (msgs + 1)->len, in mtk_i2c_do_transfer()
895 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8, in mtk_i2c_do_transfer()
898 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN); in mtk_i2c_do_transfer()
900 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN); in mtk_i2c_do_transfer()
901 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN); in mtk_i2c_do_transfer()
904 if (i2c->dev_comp->apdma_sync) { in mtk_i2c_do_transfer()
906 if (i2c->op == I2C_MASTER_WRRD) in mtk_i2c_do_transfer()
911 if (i2c->op == I2C_MASTER_RD) { in mtk_i2c_do_transfer()
912 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); in mtk_i2c_do_transfer()
913 writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON); in mtk_i2c_do_transfer()
917 return -ENOMEM; in mtk_i2c_do_transfer()
919 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, in mtk_i2c_do_transfer()
920 msgs->len, DMA_FROM_DEVICE); in mtk_i2c_do_transfer()
921 if (dma_mapping_error(i2c->dev, rpaddr)) { in mtk_i2c_do_transfer()
924 return -ENOMEM; in mtk_i2c_do_transfer()
927 if (i2c->dev_comp->max_dma_support > 32) { in mtk_i2c_do_transfer()
929 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); in mtk_i2c_do_transfer()
932 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); in mtk_i2c_do_transfer()
933 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); in mtk_i2c_do_transfer()
934 } else if (i2c->op == I2C_MASTER_WR) { in mtk_i2c_do_transfer()
935 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); in mtk_i2c_do_transfer()
936 writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON); in mtk_i2c_do_transfer()
940 return -ENOMEM; in mtk_i2c_do_transfer()
942 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, in mtk_i2c_do_transfer()
943 msgs->len, DMA_TO_DEVICE); in mtk_i2c_do_transfer()
944 if (dma_mapping_error(i2c->dev, wpaddr)) { in mtk_i2c_do_transfer()
947 return -ENOMEM; in mtk_i2c_do_transfer()
950 if (i2c->dev_comp->max_dma_support > 32) { in mtk_i2c_do_transfer()
952 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); in mtk_i2c_do_transfer()
955 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); in mtk_i2c_do_transfer()
956 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); in mtk_i2c_do_transfer()
958 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG); in mtk_i2c_do_transfer()
959 writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON); in mtk_i2c_do_transfer()
963 return -ENOMEM; in mtk_i2c_do_transfer()
965 wpaddr = dma_map_single(i2c->dev, dma_wr_buf, in mtk_i2c_do_transfer()
966 msgs->len, DMA_TO_DEVICE); in mtk_i2c_do_transfer()
967 if (dma_mapping_error(i2c->dev, wpaddr)) { in mtk_i2c_do_transfer()
970 return -ENOMEM; in mtk_i2c_do_transfer()
975 dma_unmap_single(i2c->dev, wpaddr, in mtk_i2c_do_transfer()
976 msgs->len, DMA_TO_DEVICE); in mtk_i2c_do_transfer()
980 return -ENOMEM; in mtk_i2c_do_transfer()
983 rpaddr = dma_map_single(i2c->dev, dma_rd_buf, in mtk_i2c_do_transfer()
984 (msgs + 1)->len, in mtk_i2c_do_transfer()
986 if (dma_mapping_error(i2c->dev, rpaddr)) { in mtk_i2c_do_transfer()
987 dma_unmap_single(i2c->dev, wpaddr, in mtk_i2c_do_transfer()
988 msgs->len, DMA_TO_DEVICE); in mtk_i2c_do_transfer()
993 return -ENOMEM; in mtk_i2c_do_transfer()
996 if (i2c->dev_comp->max_dma_support > 32) { in mtk_i2c_do_transfer()
998 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); in mtk_i2c_do_transfer()
1001 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); in mtk_i2c_do_transfer()
1004 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); in mtk_i2c_do_transfer()
1005 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); in mtk_i2c_do_transfer()
1006 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); in mtk_i2c_do_transfer()
1007 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); in mtk_i2c_do_transfer()
1010 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); in mtk_i2c_do_transfer()
1012 if (!i2c->auto_restart) { in mtk_i2c_do_transfer()
1019 mtk_i2c_writew(i2c, start_reg, OFFSET_START); in mtk_i2c_do_transfer()
1021 ret = wait_for_completion_timeout(&i2c->msg_complete, in mtk_i2c_do_transfer()
1022 i2c->adap.timeout); in mtk_i2c_do_transfer()
1025 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | in mtk_i2c_do_transfer()
1028 if (i2c->op == I2C_MASTER_WR) { in mtk_i2c_do_transfer()
1029 dma_unmap_single(i2c->dev, wpaddr, in mtk_i2c_do_transfer()
1030 msgs->len, DMA_TO_DEVICE); in mtk_i2c_do_transfer()
1033 } else if (i2c->op == I2C_MASTER_RD) { in mtk_i2c_do_transfer()
1034 dma_unmap_single(i2c->dev, rpaddr, in mtk_i2c_do_transfer()
1035 msgs->len, DMA_FROM_DEVICE); in mtk_i2c_do_transfer()
1039 dma_unmap_single(i2c->dev, wpaddr, msgs->len, in mtk_i2c_do_transfer()
1041 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, in mtk_i2c_do_transfer()
1048 if (ret == 0) { in mtk_i2c_do_transfer()
1049 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); in mtk_i2c_do_transfer()
1050 mtk_i2c_init_hw(i2c); in mtk_i2c_do_transfer()
1051 return -ETIMEDOUT; in mtk_i2c_do_transfer()
1054 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { in mtk_i2c_do_transfer()
1055 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); in mtk_i2c_do_transfer()
1056 mtk_i2c_init_hw(i2c); in mtk_i2c_do_transfer()
1057 return -ENXIO; in mtk_i2c_do_transfer()
1060 return 0; in mtk_i2c_do_transfer()
1068 struct mtk_i2c *i2c = i2c_get_adapdata(adap); in mtk_i2c_transfer() local
1070 ret = mtk_i2c_clock_enable(i2c); in mtk_i2c_transfer()
1074 i2c->auto_restart = i2c->dev_comp->auto_restart; in mtk_i2c_transfer()
1077 if (i2c->auto_restart && num == 2) { in mtk_i2c_transfer()
1078 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) && in mtk_i2c_transfer()
1079 msgs[0].addr == msgs[1].addr) { in mtk_i2c_transfer()
1080 i2c->auto_restart = 0; in mtk_i2c_transfer()
1084 if (i2c->auto_restart && num >= 2 && in mtk_i2c_transfer()
1085 i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) in mtk_i2c_transfer()
1089 i2c->ignore_restart_irq = true; in mtk_i2c_transfer()
1091 i2c->ignore_restart_irq = false; in mtk_i2c_transfer()
1093 while (left_num--) { in mtk_i2c_transfer()
1094 if (!msgs->buf) { in mtk_i2c_transfer()
1095 dev_dbg(i2c->dev, "data buffer is NULL.\n"); in mtk_i2c_transfer()
1096 ret = -EINVAL; in mtk_i2c_transfer()
1100 if (msgs->flags & I2C_M_RD) in mtk_i2c_transfer()
1101 i2c->op = I2C_MASTER_RD; in mtk_i2c_transfer()
1103 i2c->op = I2C_MASTER_WR; in mtk_i2c_transfer()
1105 if (!i2c->auto_restart) { in mtk_i2c_transfer()
1108 i2c->op = I2C_MASTER_WRRD; in mtk_i2c_transfer()
1109 left_num--; in mtk_i2c_transfer()
1114 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); in mtk_i2c_transfer()
1115 if (ret < 0) in mtk_i2c_transfer()
1124 mtk_i2c_clock_disable(i2c); in mtk_i2c_transfer()
1130 struct mtk_i2c *i2c = dev_id; in mtk_i2c_irq() local
1131 u16 restart_flag = 0; in mtk_i2c_irq()
1134 if (i2c->auto_restart) in mtk_i2c_irq()
1137 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); in mtk_i2c_irq()
1138 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT); in mtk_i2c_irq()
1141 * when occurs ack error, i2c controller generate two interrupts in mtk_i2c_irq()
1143 * i2c->irq_stat need keep the two interrupt value. in mtk_i2c_irq()
1145 i2c->irq_stat |= intr_stat; in mtk_i2c_irq()
1147 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) { in mtk_i2c_irq()
1148 i2c->ignore_restart_irq = false; in mtk_i2c_irq()
1149 i2c->irq_stat = 0; in mtk_i2c_irq()
1150 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | in mtk_i2c_irq()
1153 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag)) in mtk_i2c_irq()
1154 complete(&i2c->msg_complete); in mtk_i2c_irq()
1174 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) in mtk_i2c_parse_dt() argument
1178 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); in mtk_i2c_parse_dt()
1179 if (ret < 0) in mtk_i2c_parse_dt()
1180 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ; in mtk_i2c_parse_dt()
1182 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div); in mtk_i2c_parse_dt()
1183 if (ret < 0) in mtk_i2c_parse_dt()
1186 if (i2c->clk_src_div == 0) in mtk_i2c_parse_dt()
1187 return -EINVAL; in mtk_i2c_parse_dt()
1189 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); in mtk_i2c_parse_dt()
1190 i2c->use_push_pull = in mtk_i2c_parse_dt()
1191 of_property_read_bool(np, "mediatek,use-push-pull"); in mtk_i2c_parse_dt()
1193 return 0; in mtk_i2c_parse_dt()
1198 int ret = 0; in mtk_i2c_probe()
1199 struct mtk_i2c *i2c; in mtk_i2c_probe() local
1204 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); in mtk_i2c_probe()
1205 if (!i2c) in mtk_i2c_probe()
1206 return -ENOMEM; in mtk_i2c_probe()
1208 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); in mtk_i2c_probe()
1209 i2c->base = devm_ioremap_resource(&pdev->dev, res); in mtk_i2c_probe()
1210 if (IS_ERR(i2c->base)) in mtk_i2c_probe()
1211 return PTR_ERR(i2c->base); in mtk_i2c_probe()
1214 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); in mtk_i2c_probe()
1215 if (IS_ERR(i2c->pdmabase)) in mtk_i2c_probe()
1216 return PTR_ERR(i2c->pdmabase); in mtk_i2c_probe()
1218 irq = platform_get_irq(pdev, 0); in mtk_i2c_probe()
1219 if (irq < 0) in mtk_i2c_probe()
1222 init_completion(&i2c->msg_complete); in mtk_i2c_probe()
1224 i2c->dev_comp = of_device_get_match_data(&pdev->dev); in mtk_i2c_probe()
1225 i2c->adap.dev.of_node = pdev->dev.of_node; in mtk_i2c_probe()
1226 i2c->dev = &pdev->dev; in mtk_i2c_probe()
1227 i2c->adap.dev.parent = &pdev->dev; in mtk_i2c_probe()
1228 i2c->adap.owner = THIS_MODULE; in mtk_i2c_probe()
1229 i2c->adap.algo = &mtk_i2c_algorithm; in mtk_i2c_probe()
1230 i2c->adap.quirks = i2c->dev_comp->quirks; in mtk_i2c_probe()
1231 i2c->adap.timeout = 2 * HZ; in mtk_i2c_probe()
1232 i2c->adap.retries = 1; in mtk_i2c_probe()
1234 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c); in mtk_i2c_probe()
1236 return -EINVAL; in mtk_i2c_probe()
1238 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) in mtk_i2c_probe()
1239 return -EINVAL; in mtk_i2c_probe()
1241 i2c->clk_main = devm_clk_get(&pdev->dev, "main"); in mtk_i2c_probe()
1242 if (IS_ERR(i2c->clk_main)) { in mtk_i2c_probe()
1243 dev_err(&pdev->dev, "cannot get main clock\n"); in mtk_i2c_probe()
1244 return PTR_ERR(i2c->clk_main); in mtk_i2c_probe()
1247 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma"); in mtk_i2c_probe()
1248 if (IS_ERR(i2c->clk_dma)) { in mtk_i2c_probe()
1249 dev_err(&pdev->dev, "cannot get dma clock\n"); in mtk_i2c_probe()
1250 return PTR_ERR(i2c->clk_dma); in mtk_i2c_probe()
1253 i2c->clk_arb = devm_clk_get(&pdev->dev, "arb"); in mtk_i2c_probe()
1254 if (IS_ERR(i2c->clk_arb)) in mtk_i2c_probe()
1255 i2c->clk_arb = NULL; in mtk_i2c_probe()
1257 clk = i2c->clk_main; in mtk_i2c_probe()
1258 if (i2c->have_pmic) { in mtk_i2c_probe()
1259 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic"); in mtk_i2c_probe()
1260 if (IS_ERR(i2c->clk_pmic)) { in mtk_i2c_probe()
1261 dev_err(&pdev->dev, "cannot get pmic clock\n"); in mtk_i2c_probe()
1262 return PTR_ERR(i2c->clk_pmic); in mtk_i2c_probe()
1264 clk = i2c->clk_pmic; in mtk_i2c_probe()
1267 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); in mtk_i2c_probe()
1269 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk)); in mtk_i2c_probe()
1271 dev_err(&pdev->dev, "Failed to set the speed.\n"); in mtk_i2c_probe()
1272 return -EINVAL; in mtk_i2c_probe()
1275 if (i2c->dev_comp->max_dma_support > 32) { in mtk_i2c_probe()
1276 ret = dma_set_mask(&pdev->dev, in mtk_i2c_probe()
1277 DMA_BIT_MASK(i2c->dev_comp->max_dma_support)); in mtk_i2c_probe()
1279 dev_err(&pdev->dev, "dma_set_mask return error.\n"); in mtk_i2c_probe()
1284 ret = mtk_i2c_clock_enable(i2c); in mtk_i2c_probe()
1286 dev_err(&pdev->dev, "clock enable failed!\n"); in mtk_i2c_probe()
1289 mtk_i2c_init_hw(i2c); in mtk_i2c_probe()
1290 mtk_i2c_clock_disable(i2c); in mtk_i2c_probe()
1292 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, in mtk_i2c_probe()
1294 I2C_DRV_NAME, i2c); in mtk_i2c_probe()
1295 if (ret < 0) { in mtk_i2c_probe()
1296 dev_err(&pdev->dev, in mtk_i2c_probe()
1297 "Request I2C IRQ %d fail\n", irq); in mtk_i2c_probe()
1301 i2c_set_adapdata(&i2c->adap, i2c); in mtk_i2c_probe()
1302 ret = i2c_add_adapter(&i2c->adap); in mtk_i2c_probe()
1306 platform_set_drvdata(pdev, i2c); in mtk_i2c_probe()
1308 return 0; in mtk_i2c_probe()
1313 struct mtk_i2c *i2c = platform_get_drvdata(pdev); in mtk_i2c_remove() local
1315 i2c_del_adapter(&i2c->adap); in mtk_i2c_remove()
1317 return 0; in mtk_i2c_remove()
1323 struct mtk_i2c *i2c = dev_get_drvdata(dev); in mtk_i2c_suspend_noirq() local
1325 i2c_mark_adapter_suspended(&i2c->adap); in mtk_i2c_suspend_noirq()
1327 return 0; in mtk_i2c_suspend_noirq()
1333 struct mtk_i2c *i2c = dev_get_drvdata(dev); in mtk_i2c_resume_noirq() local
1335 ret = mtk_i2c_clock_enable(i2c); in mtk_i2c_resume_noirq()
1341 mtk_i2c_init_hw(i2c); in mtk_i2c_resume_noirq()
1343 mtk_i2c_clock_disable(i2c); in mtk_i2c_resume_noirq()
1345 i2c_mark_adapter_resumed(&i2c->adap); in mtk_i2c_resume_noirq()
1347 return 0; in mtk_i2c_resume_noirq()
1369 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");