19  *  o	Rev 0x10 also requires master/slave hold the same DMA timings and
76 		timing10:1;		/* Rev 0x10 */
77 	u8	clock_mode;		/* 0, ATA_50 or ATA_66 */
87 #define ATA_66		0
91 #define UDMA_OFF	0
92 #define MWDMA_OFF	0
124 		conf = timing & 0xFF;  in it821x_program()
126 	pci_write_config_byte(dev, 0x54 + 4 * channel, conf);  in it821x_program()
150 		conf = timing & 0xFF;  in it821x_program_udma()
152 	if (itdev->timing10 == 0)  in it821x_program_udma()
153 		pci_write_config_byte(dev, 0x56 + 4 * channel + unit, conf);  in it821x_program_udma()
155 		pci_write_config_byte(dev, 0x56 + 4 * channel, conf);  in it821x_program_udma()
156 		pci_write_config_byte(dev, 0x56 + 4 * channel + 1, conf);  in it821x_program_udma()
174 	int clock, altclock, sel = 0;  in it821x_clock_strategy()
177 	if(itdev->want[0][0] > itdev->want[1][0]) {  in it821x_clock_strategy()
178 		clock = itdev->want[0][1];  in it821x_clock_strategy()
182 		altclock = itdev->want[0][1];  in it821x_clock_strategy()
207 	pci_read_config_byte(dev, 0x50, &v);  in it821x_clock_strategy()
210 	pci_write_config_byte(dev, 0x50, v);  in it821x_clock_strategy()
247 	static u16 pio_timings[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };  in it821x_set_pio_mode()
262 	/* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */  in it821x_set_pio_mode()
264 	itdev->want[unit][0] = 1;	/* PIO is lowest priority */  in it821x_set_pio_mode()
288 	static u16 dma[]	= { 0x8866, 0x3222, 0x3121 };  in it821x_tune_mwdma()
292 	itdev->want[unit][0] = 2;	/* MWDMA is low priority */  in it821x_tune_mwdma()
296 	/* UDMA bits off - Revision 0x10 do them in pairs */  in it821x_tune_mwdma()
297 	pci_read_config_byte(dev, 0x50, &conf);  in it821x_tune_mwdma()
299 		conf |= channel ? 0x60: 0x18;  in it821x_tune_mwdma()
302 	pci_write_config_byte(dev, 0x50, conf);  in it821x_tune_mwdma()
325 	static u16 udma[]	= { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };  in it821x_tune_udma()
329 	itdev->want[unit][0] = 3;	/* UDMA is high priority */  in it821x_tune_udma()
333 		itdev->udma[unit] |= 0x8080;	/* UDMA 5/6 select on */  in it821x_tune_udma()
335 	/* UDMA on. Again revision 0x10 must do the pair */  in it821x_tune_udma()
336 	pci_read_config_byte(dev, 0x50, &conf);  in it821x_tune_udma()
338 		conf &= channel ? 0x9F: 0xE7;  in it821x_tune_udma()
341 	pci_write_config_byte(dev, 0x50, conf);  in it821x_tune_udma()
354  *	clock. In addition the rev 0x10 device only works if the same
451 		 *	IRQ mask as we may well be in PIO (eg rev 0x10)  in it821x_quirkproc()
470 			id[ATA_ID_COMMAND_SET_2] |= 0x0400;   /* LBA48 valid */  in it821x_quirkproc()
471 			id[ATA_ID_CFS_ENABLE_2]  |= 0x0400;   /* LBA48 on */  in it821x_quirkproc()
483 			id[ATA_ID_QUEUE_DEPTH]	  = 0;  in it821x_quirkproc()
484 			id[ATA_ID_COMMAND_SET_1]  = 0;  in it821x_quirkproc()
485 			id[ATA_ID_COMMAND_SET_2] &= 0xC400;  in it821x_quirkproc()
486 			id[ATA_ID_CFSSE]	 &= 0xC000;  in it821x_quirkproc()
487 			id[ATA_ID_CFS_ENABLE_1]	  = 0;  in it821x_quirkproc()
488 			id[ATA_ID_CFS_ENABLE_2]	 &= 0xC400;  in it821x_quirkproc()
489 			id[ATA_ID_CSF_DEFAULT]	 &= 0xC000;  in it821x_quirkproc()
490 			id[127]			  = 0;  in it821x_quirkproc()
491 			id[ATA_ID_DLF]		  = 0;  in it821x_quirkproc()
492 			id[ATA_ID_CSFO]		  = 0;  in it821x_quirkproc()
493 			id[ATA_ID_CFA_POWER]	  = 0;  in it821x_quirkproc()
504 			id[ATA_ID_MWDMA_MODES] |= 0x0101;  in it821x_quirkproc()
541 	pci_read_config_byte(dev, 0x50, &conf);  in init_hwif_it821x()
550 	/* Pull the current clocks from 0x50 also */  in init_hwif_it821x()
556 	idev->want[0][1] = ATA_ANY;  in init_hwif_it821x()
564 	if (dev->revision == 0x10) {  in init_hwif_it821x()
567 		if (idev->smart == 0)  in init_hwif_it821x()
568 			printk(KERN_WARNING DRV_NAME " %s: revision 0x10, "  in init_hwif_it821x()
572 	if (idev->smart == 0) {  in init_hwif_it821x()
578 	if (hwif->dma_base == 0)  in init_hwif_it821x()
586 		if (dev->revision == 0x11)  in init_hwif_it821x()
587 			hwif->ultra_mask = 0;  in init_hwif_it821x()
594 	pci_write_config_byte(dev, 0x5E, 0x01);  in it8212_disable_raid()
597 	pci_write_config_byte(dev, 0x50, 0x00);  in it8212_disable_raid()
601 	pci_write_config_word(dev, 0x40, 0xA0F3);  in it8212_disable_raid()
603 	pci_write_config_dword(dev,0x4C, 0x02040204);  in it8212_disable_raid()
604 	pci_write_config_byte(dev, 0x42, 0x36);  in it8212_disable_raid()
605 	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);  in it8212_disable_raid()
619 	pci_read_config_byte(dev, 0x50, &conf);  in init_chipset_it821x()
622 	return 0;  in init_chipset_it821x()
680 	{ PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), 0 },
681 	{ PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), 0 },
683 	{ 0, },