Lines Matching +full:0 +full:x5300
40 #define W5300_MR 0x0000 /* Mode Register */
49 #define MR_IND (1 << 0) /* Indirect mode */
50 #define W5300_IR 0x0002 /* Interrupt Register */
51 #define W5300_IMR 0x0004 /* Interrupt Mask Register */
52 #define IR_S0 0x0001 /* S0 interrupt */
53 #define W5300_SHARL 0x0008 /* Source MAC address (0123) */
54 #define W5300_SHARH 0x000c /* Source MAC address (45) */
55 #define W5300_TMSRL 0x0020 /* Transmit Memory Size (0123) */
56 #define W5300_TMSRH 0x0024 /* Transmit Memory Size (4567) */
57 #define W5300_RMSRL 0x0028 /* Receive Memory Size (0123) */
58 #define W5300_RMSRH 0x002c /* Receive Memory Size (4567) */
59 #define W5300_MTYPE 0x0030 /* Memory Type */
60 #define W5300_IDR 0x00fe /* Chip ID register */
61 #define IDR_W5300 0x5300 /* =0x5300 for WIZnet W5300 */
62 #define W5300_S0_MR 0x0200 /* S0 Mode Register */
63 #define S0_MR_CLOSED 0x0000 /* Close mode */
64 #define S0_MR_MACRAW 0x0004 /* MAC RAW mode (promiscuous) */
65 #define S0_MR_MACRAW_MF 0x0044 /* MAC RAW mode (filtered) */
66 #define W5300_S0_CR 0x0202 /* S0 Command Register */
67 #define S0_CR_OPEN 0x0001 /* OPEN command */
68 #define S0_CR_CLOSE 0x0010 /* CLOSE command */
69 #define S0_CR_SEND 0x0020 /* SEND command */
70 #define S0_CR_RECV 0x0040 /* RECV command */
71 #define W5300_S0_IMR 0x0204 /* S0 Interrupt Mask Register */
72 #define W5300_S0_IR 0x0206 /* S0 Interrupt Register */
73 #define S0_IR_RECV 0x0004 /* Receive interrupt */
74 #define S0_IR_SENDOK 0x0010 /* Send OK interrupt */
75 #define W5300_S0_SSR 0x0208 /* S0 Socket Status Register */
76 #define W5300_S0_TX_WRSR 0x0220 /* S0 TX Write Size Register */
77 #define W5300_S0_TX_FSR 0x0224 /* S0 TX Free Size Register */
78 #define W5300_S0_RX_RSR 0x0228 /* S0 Received data Size */
79 #define W5300_S0_TX_FIFO 0x022e /* S0 Transmit FIFO */
80 #define W5300_S0_RX_FIFO 0x0230 /* S0 Receive FIFO */
81 #define W5300_REGS_LEN 0x0400
112 * 0x400 bytes are required for memory space.
131 * Only 0x06 bytes are required for memory space.
133 #define W5300_IDM_AR 0x0002 /* Indirect Mode Address */
134 #define W5300_IDM_DR 0x0004 /* Indirect Mode Data */
192 while (w5300_read(priv, W5300_S0_CR) != 0) { in w5300_command()
198 return 0; in w5300_command()
206 for (i = 0; i < len; i += 2) { in w5300_read_frame()
220 for (i = 0; i < len; i += 2) { in w5300_write_frame()
232 ndev->dev_addr[0] << 24 | in w5300_write_macaddr()
248 w5300_write(priv, W5300_IMR, 0); in w5300_hw_reset()
255 w5300_write32(priv, W5300_RMSRH, 0); in w5300_hw_reset()
257 w5300_write32(priv, W5300_TMSRH, 0); in w5300_hw_reset()
258 w5300_write(priv, W5300_MTYPE, 0x00ff); in w5300_hw_reset()
272 w5300_write(priv, W5300_IMR, 0); in w5300_hw_close()
329 for (addr = 0; addr < W5300_REGS_LEN; addr += 2) { in w5300_get_regs()
330 switch (addr & 0x23f) { in w5300_get_regs()
333 data = 0xffff; in w5300_get_regs()
381 for (rx_count = 0; rx_count < budget; rx_count++) { in w5300_napi_poll()
383 if (rx_fifo_len == 0) in w5300_napi_poll()
391 for (i = 0; i < rx_fifo_len; i += 2) in w5300_napi_poll()
431 w5300_write(priv, W5300_IMR, 0); in w5300_interrupt()
445 if (gpio_get_value(priv->link_gpio) != 0) { in w5300_detect_link()
460 bool set_promisc = (ndev->flags & IFF_PROMISC) != 0; in w5300_set_rx_mode()
477 return 0; in w5300_set_macaddr()
489 gpio_get_value(priv->link_gpio) != 0) in w5300_open()
491 return 0; in w5300_open()
503 return 0; in w5300_stop()
542 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); in w5300_hw_probe()
563 irq = platform_get_irq(pdev, 0); in w5300_hw_probe()
564 if (irq < 0) in w5300_hw_probe()
568 if (ret < 0) in w5300_hw_probe()
581 link_name, priv->ndev) < 0) in w5300_hw_probe()
585 netdev_info(ndev, "at 0x%llx irq %d\n", (u64)mem->start, irq); in w5300_hw_probe()
586 return 0; in w5300_hw_probe()
614 if (err < 0) in w5300_probe()
618 if (err < 0) in w5300_probe()
621 return 0; in w5300_probe()
642 return 0; in w5300_remove()
657 return 0; in w5300_suspend()
671 gpio_get_value(priv->link_gpio) != 0) in w5300_resume()
674 return 0; in w5300_resume()