18 #define PHY_ID_AQ1202	0x03a1b445
19 #define PHY_ID_AQ2104	0x03a1b460
20 #define PHY_ID_AQR105	0x03a1b4a2
21 #define PHY_ID_AQR106	0x03a1b4d0
22 #define PHY_ID_AQR107	0x03a1b4e0
23 #define PHY_ID_AQCS109	0x03a1b5c2
24 #define PHY_ID_AQR405	0x03a1b4b0
26 #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
28 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR	0
34 #define MDIO_AN_VEND_PROV			0xc400
40 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK	GENMASK(3, 0)
43 #define MDIO_AN_TX_VEND_STATUS1			0xc800
45 #define MDIO_AN_TX_VEND_STATUS1_10BASET		0
51 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX	BIT(0)
53 #define MDIO_AN_TX_VEND_INT_STATUS1		0xcc00
56 #define MDIO_AN_TX_VEND_INT_STATUS2		0xcc01
58 #define MDIO_AN_TX_VEND_INT_MASK2		0xd401
59 #define MDIO_AN_TX_VEND_INT_MASK2_LINK		BIT(0)
61 #define MDIO_AN_RX_LP_STAT1			0xe820
68 #define MDIO_AN_RX_LP_STAT4			0xe823
70 #define MDIO_AN_RX_LP_STAT4_FW_MINOR		GENMASK(7, 0)
72 #define MDIO_AN_RX_VEND_STAT3			0xe832
73 #define MDIO_AN_RX_VEND_STAT3_AFR		BIT(0)
76 #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES		0xd292
77 #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES		0xd294
78 #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER		0xd297
79 #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES		0xd313
80 #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES		0xd315
81 #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER		0xd317
82 #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS		0xd318
83 #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS	0xd319
84 #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR	0xd31a
85 #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES		0xd31b
88 #define VEND1_GLOBAL_FW_ID			0x0020
90 #define VEND1_GLOBAL_FW_ID_MINOR		GENMASK(7, 0)
92 #define VEND1_GLOBAL_GEN_STAT2			0xc831
95 #define VEND1_GLOBAL_RSVD_STAT1			0xc885
97 #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID		GENMASK(3, 0)
99 #define VEND1_GLOBAL_RSVD_STAT9			0xc88d
100 #define VEND1_GLOBAL_RSVD_STAT9_MODE		GENMASK(7, 0)
101 #define VEND1_GLOBAL_RSVD_STAT9_1000BT2		0x23
103 #define VEND1_GLOBAL_INT_STD_STATUS		0xfc00
104 #define VEND1_GLOBAL_INT_VEND_STATUS		0xfc01
106 #define VEND1_GLOBAL_INT_STD_MASK		0xff00
117 #define VEND1_GLOBAL_INT_STD_MASK_ALL		BIT(0)
119 #define VEND1_GLOBAL_INT_VEND_MASK		0xff01
127 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3	BIT(0)
169 	for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)  in aqr107_get_strings()
183 	if (val < 0)  in aqr107_get_stat()
186 	ret = val & GENMASK(len_l - 1, 0);  in aqr107_get_stat()
189 		if (val < 0)  in aqr107_get_stat()
192 		ret += (val & GENMASK(len_h - 1, 0)) << 16;  in aqr107_get_stat()
205 	for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {  in aqr107_get_stats()
227 	if (ret < 0)  in aqr_config_aneg()
229 	if (ret > 0)  in aqr_config_aneg()
235 	reg = 0;  in aqr_config_aneg()
258 	if (ret < 0)  in aqr_config_aneg()
260 	if (ret > 0)  in aqr_config_aneg()
272 			    en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);  in aqr_config_intr()
273 	if (err < 0)  in aqr_config_intr()
277 			    en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);  in aqr_config_intr()
278 	if (err < 0)  in aqr_config_intr()
283 			     VEND1_GLOBAL_INT_VEND_MASK_AN : 0);  in aqr_config_intr()
292 	return (reg < 0) ? reg : 0;  in aqr_ack_interrupt()
301 		if (val < 0)  in aqr_read_status()
320 	if (val < 0)  in aqr107_read_rate()
352 	return 0;  in aqr107_read_rate()
364 		return 0;  in aqr107_read_status()
367 	if (val < 0)  in aqr107_read_status()
400 	if (val < 0)  in aqr107_get_downshift()
408 	return 0;  in aqr107_get_downshift()
413 	int val = 0;  in aqr107_set_downshift()
462 					 VEND1_GLOBAL_FW_ID, val, val != 0,  in aqr107_wait_reset_complete()
472 	if (val < 0)  in aqr107_chip_info()
479 	if (val < 0)  in aqr107_chip_info()
547 	if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))  in aqr107_link_change_notify()
554 	if (val < 0)  in aqr107_link_change_notify()
561 	if (val < 0)  in aqr107_link_change_notify()
573 	if (val < 0)  in aqr107_link_change_notify()
602 	return 0;  in aqr107_wait_processor_intensive_op()