Lines Matching +full:0 +full:xfffffff0
20 #define MII_BCM7XXX_100TX_AUX_CTL 0x10
21 #define MII_BCM7XXX_100TX_FALSE_CAR 0x13
22 #define MII_BCM7XXX_100TX_DISC 0x14
23 #define MII_BCM7XXX_AUX_MODE 0x1d
25 #define MII_BCM7XXX_TEST 0x1f
27 #define MII_BCM7XXX_SHD_2_ADDR_CTRL 0xe
28 #define MII_BCM7XXX_SHD_2_CTRL_STAT 0xf
29 #define MII_BCM7XXX_SHD_2_BIAS_TRIM 0x1a
30 #define MII_BCM7XXX_SHD_3_PCS_CTRL 0x0
31 #define MII_BCM7XXX_SHD_3_PCS_STATUS 0x1
32 #define MII_BCM7XXX_SHD_3_EEE_CAP 0x2
33 #define MII_BCM7XXX_SHD_3_AN_EEE_ADV 0x3
34 #define MII_BCM7XXX_SHD_3_EEE_LP 0x4
35 #define MII_BCM7XXX_SHD_3_EEE_WK_ERR 0x5
36 #define MII_BCM7XXX_SHD_3_PCS_CTRL_2 0x6
37 #define MII_BCM7XXX_PCS_CTRL_2_DEF 0x4400
38 #define MII_BCM7XXX_SHD_3_AN_STAT 0xb
39 #define MII_BCM7XXX_AN_NULL_MSG_EN BIT(0)
41 #define MII_BCM7XXX_SHD_3_EEE_THRESH 0xe
42 #define MII_BCM7XXX_EEE_THRESH_DEF 0x50
43 #define MII_BCM7XXX_SHD_3_TL4 0x23
54 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15); in bcm7xxx_28nm_d0_afe_config_init()
57 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); in bcm7xxx_28nm_d0_afe_config_init()
59 /* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */ in bcm7xxx_28nm_d0_afe_config_init()
60 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003); in bcm7xxx_28nm_d0_afe_config_init()
63 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0); in bcm7xxx_28nm_d0_afe_config_init()
66 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); in bcm7xxx_28nm_d0_afe_config_init()
69 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); in bcm7xxx_28nm_d0_afe_config_init()
72 bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020); in bcm7xxx_28nm_d0_afe_config_init()
75 * offset for HT=0 code in bcm7xxx_28nm_d0_afe_config_init()
77 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); in bcm7xxx_28nm_d0_afe_config_init()
80 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
82 /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */ in bcm7xxx_28nm_d0_afe_config_init()
83 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); in bcm7xxx_28nm_d0_afe_config_init()
88 return 0; in bcm7xxx_28nm_d0_afe_config_init()
94 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); in bcm7xxx_28nm_e0_plus_afe_config_init()
97 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); in bcm7xxx_28nm_e0_plus_afe_config_init()
100 bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); in bcm7xxx_28nm_e0_plus_afe_config_init()
103 * offset for HT=0 code in bcm7xxx_28nm_e0_plus_afe_config_init()
105 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); in bcm7xxx_28nm_e0_plus_afe_config_init()
108 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
110 /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */ in bcm7xxx_28nm_e0_plus_afe_config_init()
111 bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); in bcm7xxx_28nm_e0_plus_afe_config_init()
116 return 0; in bcm7xxx_28nm_e0_plus_afe_config_init()
122 bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003); in bcm7xxx_28nm_a0_patch_afe_config_init()
125 bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b); in bcm7xxx_28nm_a0_patch_afe_config_init()
128 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3); in bcm7xxx_28nm_a0_patch_afe_config_init()
130 /* Change rx_on_tune 8 to 0xf */ in bcm7xxx_28nm_a0_patch_afe_config_init()
131 bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6); in bcm7xxx_28nm_a0_patch_afe_config_init()
134 bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d); in bcm7xxx_28nm_a0_patch_afe_config_init()
137 bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015); in bcm7xxx_28nm_a0_patch_afe_config_init()
141 return 0; in bcm7xxx_28nm_a0_patch_afe_config_init()
149 int ret = 0; in bcm7xxx_28nm_config_init()
154 if (rev == 0) in bcm7xxx_28nm_config_init()
157 pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n", in bcm7xxx_28nm_config_init()
162 * the MDIO management controller and make us return 0xffff for such in bcm7xxx_28nm_config_init()
168 case 0xa0: in bcm7xxx_28nm_config_init()
169 case 0xb0: in bcm7xxx_28nm_config_init()
172 case 0xd0: in bcm7xxx_28nm_config_init()
175 case 0xe0: in bcm7xxx_28nm_config_init()
176 case 0xf0: in bcm7xxx_28nm_config_init()
178 case 0x10: in bcm7xxx_28nm_config_init()
181 case 0x01: in bcm7xxx_28nm_config_init()
230 if (v < 0) in __phy_set_clr_bits()
237 if (ret < 0) in __phy_set_clr_bits()
261 MII_BCM7XXX_SHD_MODE_2, 0); in bcm7xxx_28nm_ephy_01_afe_config_init()
262 if (ret < 0) in bcm7xxx_28nm_ephy_01_afe_config_init()
265 /* Set current trim values INT_trim = -1, Ext_trim =0 */ in bcm7xxx_28nm_ephy_01_afe_config_init()
266 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0); in bcm7xxx_28nm_ephy_01_afe_config_init()
267 if (ret < 0) in bcm7xxx_28nm_ephy_01_afe_config_init()
273 if (ret < 0) in bcm7xxx_28nm_ephy_01_afe_config_init()
276 MII_BCM7XXX_TL4_RST_MSK, 0); in bcm7xxx_28nm_ephy_01_afe_config_init()
277 if (ret < 0) in bcm7xxx_28nm_ephy_01_afe_config_init()
283 if (ret < 0) in bcm7xxx_28nm_ephy_01_afe_config_init()
286 0, MII_BCM7XXX_TL4_RST_MSK); in bcm7xxx_28nm_ephy_01_afe_config_init()
287 if (ret < 0) in bcm7xxx_28nm_ephy_01_afe_config_init()
292 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_01_afe_config_init()
294 if (ret < 0) in bcm7xxx_28nm_ephy_01_afe_config_init()
297 return 0; in bcm7xxx_28nm_ephy_01_afe_config_init()
307 MII_BRCM_FET_BT_SRE, 0); in bcm7xxx_28nm_ephy_apd_enable()
308 if (ret < 0) in bcm7xxx_28nm_ephy_apd_enable()
313 MII_BRCM_FET_SHDW_AS2_APDE, 0); in bcm7xxx_28nm_ephy_apd_enable()
314 if (ret < 0) in bcm7xxx_28nm_ephy_apd_enable()
318 ret = phy_set_clr_bits(phydev, MII_BRCM_FET_BRCMTEST, 0, in bcm7xxx_28nm_ephy_apd_enable()
320 if (ret < 0) in bcm7xxx_28nm_ephy_apd_enable()
323 return 0; in bcm7xxx_28nm_ephy_apd_enable()
332 MII_BCM7XXX_SHD_MODE_2, 0); in bcm7xxx_28nm_ephy_eee_enable()
333 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
339 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
343 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
349 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
353 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
358 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
362 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
368 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
372 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
377 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_eee_enable()
379 if (ret < 0) in bcm7xxx_28nm_ephy_eee_enable()
386 return 0; in bcm7xxx_28nm_ephy_eee_enable()
392 int ret = 0; in bcm7xxx_28nm_ephy_config_init()
394 pr_info_once("%s: %s PHY revision: 0x%02x\n", in bcm7xxx_28nm_ephy_config_init()
399 * to pass the MDIO management controller and make us return 0xffff for in bcm7xxx_28nm_ephy_config_init()
405 if (rev == 0x01) { in bcm7xxx_28nm_ephy_config_init()
418 #define MII_BCM7XXX_REG_INVALID 0xff
457 MII_BCM7XXX_SHD_MODE_2, 0); in bcm7xxx_28nm_ephy_read_mmd()
458 if (ret < 0) in bcm7xxx_28nm_ephy_read_mmd()
463 if (ret < 0) in bcm7xxx_28nm_ephy_read_mmd()
470 __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_read_mmd()
487 MII_BCM7XXX_SHD_MODE_2, 0); in bcm7xxx_28nm_ephy_write_mmd()
488 if (ret < 0) in bcm7xxx_28nm_ephy_write_mmd()
493 if (ret < 0) in bcm7xxx_28nm_ephy_write_mmd()
501 return __phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, in bcm7xxx_28nm_ephy_write_mmd()
528 if (ret < 0) in bcm7xxx_config_init()
532 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00); in bcm7xxx_config_init()
536 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00); in bcm7xxx_config_init()
538 phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555); in bcm7xxx_config_init()
541 ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2); in bcm7xxx_config_init()
542 if (ret < 0) in bcm7xxx_config_init()
545 return 0; in bcm7xxx_config_init()
558 { MII_BCM7XXX_TEST, 0x008b }, in bcm7xxx_suspend()
559 { MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 }, in bcm7xxx_suspend()
560 { MII_BCM7XXX_100TX_DISC, 0x7000 }, in bcm7xxx_suspend()
561 { MII_BCM7XXX_TEST, 0x000f }, in bcm7xxx_suspend()
562 { MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 }, in bcm7xxx_suspend()
563 { MII_BCM7XXX_TEST, 0x000b }, in bcm7xxx_suspend()
567 for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) { in bcm7xxx_suspend()
575 return 0; in bcm7xxx_suspend()
630 int ret = 0; in bcm7xxx_28nm_probe()
654 * the MDIO management controller and make us return 0xffff for such in bcm7xxx_28nm_probe()
673 .phy_id_mask = 0xfffffff0, \
691 .phy_id_mask = 0xfffffff0, \
709 .phy_id_mask = 0xfffffff0, \
741 { PHY_ID_BCM72113, 0xfffffff0 },
742 { PHY_ID_BCM7250, 0xfffffff0, },
743 { PHY_ID_BCM7255, 0xfffffff0, },
744 { PHY_ID_BCM7260, 0xfffffff0, },
745 { PHY_ID_BCM7268, 0xfffffff0, },
746 { PHY_ID_BCM7271, 0xfffffff0, },
747 { PHY_ID_BCM7278, 0xfffffff0, },
748 { PHY_ID_BCM7364, 0xfffffff0, },
749 { PHY_ID_BCM7366, 0xfffffff0, },
750 { PHY_ID_BCM7346, 0xfffffff0, },
751 { PHY_ID_BCM7362, 0xfffffff0, },
752 { PHY_ID_BCM7425, 0xfffffff0, },
753 { PHY_ID_BCM7429, 0xfffffff0, },
754 { PHY_ID_BCM74371, 0xfffffff0, },
755 { PHY_ID_BCM7439, 0xfffffff0, },
756 { PHY_ID_BCM7435, 0xfffffff0, },
757 { PHY_ID_BCM7445, 0xfffffff0, },