Lines Matching full:phydev
110 static int vsc85xx_phy_read_page(struct phy_device *phydev) in vsc85xx_phy_read_page() argument
112 return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS); in vsc85xx_phy_read_page()
115 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page) in vsc85xx_phy_write_page() argument
117 return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page); in vsc85xx_phy_write_page()
120 static int vsc85xx_get_sset_count(struct phy_device *phydev) in vsc85xx_get_sset_count() argument
122 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_sset_count()
130 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data) in vsc85xx_get_strings() argument
132 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_strings()
143 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i) in vsc85xx_get_stat() argument
145 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_stat()
148 val = phy_read_paged(phydev, priv->hw_stats[i].page, in vsc85xx_get_stat()
159 static void vsc85xx_get_stats(struct phy_device *phydev, in vsc85xx_get_stats() argument
162 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_stats()
169 data[i] = vsc85xx_get_stat(phydev, i); in vsc85xx_get_stats()
172 static int vsc85xx_led_cntl_set(struct phy_device *phydev, in vsc85xx_led_cntl_set() argument
179 mutex_lock(&phydev->lock); in vsc85xx_led_cntl_set()
180 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL); in vsc85xx_led_cntl_set()
183 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val); in vsc85xx_led_cntl_set()
184 mutex_unlock(&phydev->lock); in vsc85xx_led_cntl_set()
189 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix) in vsc85xx_mdix_get() argument
193 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL); in vsc85xx_mdix_get()
202 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix) in vsc85xx_mdix_set() argument
207 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL); in vsc85xx_mdix_set()
217 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val); in vsc85xx_mdix_set()
228 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_mdix_set()
234 return genphy_restart_aneg(phydev); in vsc85xx_mdix_set()
237 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count) in vsc85xx_downshift_get() argument
241 reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_downshift_get()
255 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count) in vsc85xx_downshift_set() argument
261 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n"); in vsc85xx_downshift_set()
268 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_downshift_set()
273 static int vsc85xx_wol_set(struct phy_device *phydev, in vsc85xx_wol_set() argument
281 u8 *mac_addr = phydev->attached_dev->dev_addr; in vsc85xx_wol_set()
283 mutex_lock(&phydev->lock); in vsc85xx_wol_set()
284 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); in vsc85xx_wol_set()
286 rc = phy_restore_page(phydev, rc, rc); in vsc85xx_wol_set()
295 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]); in vsc85xx_wol_set()
296 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]); in vsc85xx_wol_set()
297 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]); in vsc85xx_wol_set()
299 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0); in vsc85xx_wol_set()
300 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0); in vsc85xx_wol_set()
301 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0); in vsc85xx_wol_set()
308 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]); in vsc85xx_wol_set()
309 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]); in vsc85xx_wol_set()
310 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]); in vsc85xx_wol_set()
312 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0); in vsc85xx_wol_set()
313 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0); in vsc85xx_wol_set()
314 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0); in vsc85xx_wol_set()
317 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); in vsc85xx_wol_set()
322 __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val); in vsc85xx_wol_set()
324 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); in vsc85xx_wol_set()
330 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); in vsc85xx_wol_set()
332 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); in vsc85xx_wol_set()
337 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); in vsc85xx_wol_set()
339 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); in vsc85xx_wol_set()
344 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_wol_set()
347 mutex_unlock(&phydev->lock); in vsc85xx_wol_set()
352 static void vsc85xx_wol_get(struct phy_device *phydev, in vsc85xx_wol_get() argument
361 mutex_lock(&phydev->lock); in vsc85xx_wol_get()
362 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); in vsc85xx_wol_get()
366 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); in vsc85xx_wol_get()
370 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD); in vsc85xx_wol_get()
371 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD); in vsc85xx_wol_get()
372 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD); in vsc85xx_wol_get()
381 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); in vsc85xx_wol_get()
382 mutex_unlock(&phydev->lock); in vsc85xx_wol_get()
386 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) in vsc85xx_edge_rate_magic_get() argument
390 struct device *dev = &phydev->mdio.dev; in vsc85xx_edge_rate_magic_get()
412 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, in vsc85xx_dt_led_mode_get() argument
416 struct vsc8531_private *priv = phydev->priv; in vsc85xx_dt_led_mode_get()
417 struct device *dev = &phydev->mdio.dev; in vsc85xx_dt_led_mode_get()
428 phydev_err(phydev, "DT %s invalid\n", led); in vsc85xx_dt_led_mode_get()
436 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) in vsc85xx_edge_rate_magic_get() argument
441 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, in vsc85xx_dt_led_mode_get() argument
449 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev, in vsc85xx_dt_led_modes_get() argument
452 struct vsc8531_private *priv = phydev->priv; in vsc85xx_dt_led_modes_get()
461 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop, in vsc85xx_dt_led_modes_get()
471 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate) in vsc85xx_edge_rate_cntl_set() argument
475 mutex_lock(&phydev->lock); in vsc85xx_edge_rate_cntl_set()
476 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, in vsc85xx_edge_rate_cntl_set()
479 mutex_unlock(&phydev->lock); in vsc85xx_edge_rate_cntl_set()
484 static int vsc85xx_mac_if_set(struct phy_device *phydev, in vsc85xx_mac_if_set() argument
490 mutex_lock(&phydev->lock); in vsc85xx_mac_if_set()
491 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); in vsc85xx_mac_if_set()
511 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val); in vsc85xx_mac_if_set()
515 rc = genphy_soft_reset(phydev); in vsc85xx_mac_if_set()
518 mutex_unlock(&phydev->lock); in vsc85xx_mac_if_set()
530 static int vsc85xx_update_rgmii_cntl(struct phy_device *phydev, u32 rgmii_cntl, in vsc85xx_update_rgmii_cntl() argument
549 if (phy_interface_is_rgmii(phydev)) in vsc85xx_update_rgmii_cntl()
552 mutex_lock(&phydev->lock); in vsc85xx_update_rgmii_cntl()
554 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || in vsc85xx_update_rgmii_cntl()
555 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in vsc85xx_update_rgmii_cntl()
557 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || in vsc85xx_update_rgmii_cntl()
558 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in vsc85xx_update_rgmii_cntl()
562 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, in vsc85xx_update_rgmii_cntl()
565 mutex_unlock(&phydev->lock); in vsc85xx_update_rgmii_cntl()
570 static int vsc85xx_default_config(struct phy_device *phydev) in vsc85xx_default_config() argument
572 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc85xx_default_config()
574 return vsc85xx_update_rgmii_cntl(phydev, VSC8502_RGMII_CNTL, in vsc85xx_default_config()
579 static int vsc85xx_get_tunable(struct phy_device *phydev, in vsc85xx_get_tunable() argument
584 return vsc85xx_downshift_get(phydev, (u8 *)data); in vsc85xx_get_tunable()
590 static int vsc85xx_set_tunable(struct phy_device *phydev, in vsc85xx_set_tunable() argument
596 return vsc85xx_downshift_set(phydev, *(u8 *)data); in vsc85xx_set_tunable()
603 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val) in vsc85xx_tr_write() argument
605 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16); in vsc85xx_tr_write()
606 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); in vsc85xx_tr_write()
607 __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); in vsc85xx_tr_write()
610 static int vsc8531_pre_init_seq_set(struct phy_device *phydev) in vsc8531_pre_init_seq_set() argument
622 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD, in vsc8531_pre_init_seq_set()
627 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
631 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
635 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
640 mutex_lock(&phydev->lock); in vsc8531_pre_init_seq_set()
641 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); in vsc8531_pre_init_seq_set()
646 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val); in vsc8531_pre_init_seq_set()
649 oldpage = phy_restore_page(phydev, oldpage, oldpage); in vsc8531_pre_init_seq_set()
650 mutex_unlock(&phydev->lock); in vsc8531_pre_init_seq_set()
655 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev) in vsc85xx_eee_init_seq_set() argument
680 mutex_lock(&phydev->lock); in vsc85xx_eee_init_seq_set()
681 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); in vsc85xx_eee_init_seq_set()
686 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val); in vsc85xx_eee_init_seq_set()
689 oldpage = phy_restore_page(phydev, oldpage, oldpage); in vsc85xx_eee_init_seq_set()
690 mutex_unlock(&phydev->lock); in vsc85xx_eee_init_seq_set()
695 /* phydev->bus->mdio_lock should be locked when using this function */
696 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val) in phy_base_write() argument
698 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { in phy_base_write()
699 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); in phy_base_write()
703 return __phy_package_write(phydev, regnum, val); in phy_base_write()
706 /* phydev->bus->mdio_lock should be locked when using this function */
707 static int phy_base_read(struct phy_device *phydev, u32 regnum) in phy_base_read() argument
709 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { in phy_base_read()
710 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); in phy_base_read()
714 return __phy_package_read(phydev, regnum); in phy_base_read()
717 static u32 vsc85xx_csr_read(struct phy_device *phydev, in vsc85xx_csr_read() argument
723 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); in vsc85xx_csr_read()
733 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, in vsc85xx_csr_read()
743 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, in vsc85xx_csr_read()
752 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); in vsc85xx_csr_read()
760 val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17); in vsc85xx_csr_read()
763 val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18); in vsc85xx_csr_read()
765 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc85xx_csr_read()
771 static int vsc85xx_csr_write(struct phy_device *phydev, in vsc85xx_csr_write() argument
776 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); in vsc85xx_csr_write()
786 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, in vsc85xx_csr_write()
790 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val); in vsc85xx_csr_write()
793 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16)); in vsc85xx_csr_write()
802 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, in vsc85xx_csr_write()
811 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); in vsc85xx_csr_write()
818 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc85xx_csr_write()
825 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val) in vsc8584_csr_write() argument
827 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16); in vsc8584_csr_write()
828 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); in vsc8584_csr_write()
829 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); in vsc8584_csr_write()
833 static int vsc8584_cmd(struct phy_device *phydev, u16 val) in vsc8584_cmd() argument
838 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_cmd()
841 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val); in vsc8584_cmd()
845 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD); in vsc8584_cmd()
850 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_cmd()
862 static int vsc8584_micro_deassert_reset(struct phy_device *phydev, in vsc8584_micro_deassert_reset() argument
867 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_deassert_reset()
879 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); in vsc8584_micro_deassert_reset()
885 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
887 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
889 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_micro_deassert_reset()
895 static int vsc8584_micro_assert_reset(struct phy_device *phydev) in vsc8584_micro_assert_reset() argument
900 ret = vsc8584_cmd(phydev, PROC_CMD_NOP); in vsc8584_micro_assert_reset()
904 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_assert_reset()
907 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
909 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
911 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
912 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
914 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
916 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
918 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP); in vsc8584_micro_assert_reset()
920 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
922 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
924 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF | in vsc8584_micro_assert_reset()
928 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
930 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
932 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_micro_assert_reset()
938 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size, in vsc8584_get_fw_crc() argument
943 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8584_get_fw_crc()
945 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start); in vsc8584_get_fw_crc()
946 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size); in vsc8584_get_fw_crc()
949 ret = vsc8584_cmd(phydev, PROC_CMD_CRC16); in vsc8584_get_fw_crc()
953 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8584_get_fw_crc()
955 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2); in vsc8584_get_fw_crc()
958 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_get_fw_crc()
964 static int vsc8584_patch_fw(struct phy_device *phydev, in vsc8584_patch_fw() argument
969 ret = vsc8584_micro_assert_reset(phydev); in vsc8584_patch_fw()
971 dev_err(&phydev->mdio.dev, in vsc8584_patch_fw()
976 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_patch_fw()
982 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM | in vsc8584_patch_fw()
985 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN | in vsc8584_patch_fw()
987 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000); in vsc8584_patch_fw()
990 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | in vsc8584_patch_fw()
994 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); in vsc8584_patch_fw()
996 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_patch_fw()
1002 static bool vsc8574_is_serdes_init(struct phy_device *phydev) in vsc8574_is_serdes_init() argument
1007 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_is_serdes_init()
1010 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1)); in vsc8574_is_serdes_init()
1016 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1)); in vsc8574_is_serdes_init()
1022 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8574_is_serdes_init()
1028 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
1037 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_is_serdes_init()
1043 static int vsc8574_config_pre_init(struct phy_device *phydev) in vsc8574_config_pre_init() argument
1109 struct device *dev = &phydev->mdio.dev; in vsc8574_config_pre_init()
1116 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1119 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8574_config_pre_init()
1121 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8574_config_pre_init()
1123 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc8574_config_pre_init()
1130 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040); in vsc8574_config_pre_init()
1132 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8574_config_pre_init()
1134 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320); in vsc8574_config_pre_init()
1135 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00); in vsc8574_config_pre_init()
1136 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca); in vsc8574_config_pre_init()
1137 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20); in vsc8574_config_pre_init()
1139 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8574_config_pre_init()
1141 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8574_config_pre_init()
1143 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8574_config_pre_init()
1146 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8574_config_pre_init()
1148 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); in vsc8574_config_pre_init()
1150 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8574_config_pre_init()
1152 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8574_config_pre_init()
1155 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); in vsc8574_config_pre_init()
1157 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8574_config_pre_init()
1159 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8574_config_pre_init()
1161 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8574_config_pre_init()
1163 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1166 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8574_config_pre_init()
1168 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8574_config_pre_init()
1178 ret = vsc8584_get_fw_crc(phydev, in vsc8574_config_pre_init()
1185 serdes_init = vsc8574_is_serdes_init(phydev); in vsc8574_config_pre_init()
1188 ret = vsc8584_micro_assert_reset(phydev); in vsc8574_config_pre_init()
1201 if (vsc8584_patch_fw(phydev, fw)) in vsc8574_config_pre_init()
1207 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
1210 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7); in vsc8574_config_pre_init()
1211 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012); in vsc8574_config_pre_init()
1212 phy_base_write(phydev, MSCC_INT_MEM_CNTL, in vsc8574_config_pre_init()
1215 vsc8584_micro_deassert_reset(phydev, false); in vsc8574_config_pre_init()
1220 ret = vsc8584_get_fw_crc(phydev, in vsc8574_config_pre_init()
1231 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
1234 ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT | in vsc8574_config_pre_init()
1238 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1246 static void vsc8584_pll5g_cfg2_wr(struct phy_device *phydev, in vsc8584_pll5g_cfg2_wr() argument
1251 rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2); in vsc8584_pll5g_cfg2_wr()
1254 vsc85xx_csr_write(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2, rd_dat); in vsc8584_pll5g_cfg2_wr()
1258 static int vsc8584_mcb_rd_trig(struct phy_device *phydev, in vsc8584_mcb_rd_trig() argument
1264 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr, in vsc8584_mcb_rd_trig()
1270 phydev, MACRO_CTRL, mcb_reg_addr); in vsc8584_mcb_rd_trig()
1274 static int vsc8584_mcb_wr_trig(struct phy_device *phydev, in vsc8584_mcb_wr_trig() argument
1281 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr, in vsc8584_mcb_wr_trig()
1287 phydev, MACRO_CTRL, mcb_reg_addr); in vsc8584_mcb_wr_trig()
1291 static int vsc8584_pll5g_reset(struct phy_device *phydev) in vsc8584_pll5g_reset() argument
1296 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1302 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm); in vsc8584_pll5g_reset()
1305 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1313 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1319 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm); in vsc8584_pll5g_reset()
1322 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1332 static int vsc8584_config_pre_init(struct phy_device *phydev) in vsc8584_config_pre_init() argument
1364 struct device *dev = &phydev->mdio.dev; in vsc8584_config_pre_init()
1369 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1372 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8584_config_pre_init()
1374 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8584_config_pre_init()
1376 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc8584_config_pre_init()
1378 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL); in vsc8584_config_pre_init()
1380 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg); in vsc8584_config_pre_init()
1387 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3); in vsc8584_config_pre_init()
1389 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000); in vsc8584_config_pre_init()
1391 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8584_config_pre_init()
1393 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20); in vsc8584_config_pre_init()
1395 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8584_config_pre_init()
1397 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8584_config_pre_init()
1399 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8584_config_pre_init()
1401 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4)); in vsc8584_config_pre_init()
1403 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB); in vsc8584_config_pre_init()
1406 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg); in vsc8584_config_pre_init()
1408 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4)); in vsc8584_config_pre_init()
1411 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8584_config_pre_init()
1413 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); in vsc8584_config_pre_init()
1415 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8584_config_pre_init()
1417 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8584_config_pre_init()
1420 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); in vsc8584_config_pre_init()
1422 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8584_config_pre_init()
1424 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8584_config_pre_init()
1426 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8584_config_pre_init()
1428 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1431 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8584_config_pre_init()
1433 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8584_config_pre_init()
1443 ret = vsc8584_get_fw_crc(phydev, in vsc8584_config_pre_init()
1451 if (vsc8584_patch_fw(phydev, fw)) in vsc8584_config_pre_init()
1456 vsc8584_micro_deassert_reset(phydev, false); in vsc8584_config_pre_init()
1459 ret = vsc8584_get_fw_crc(phydev, in vsc8584_config_pre_init()
1469 ret = vsc8584_micro_assert_reset(phydev); in vsc8584_config_pre_init()
1473 vsc8584_micro_deassert_reset(phydev, true); in vsc8584_config_pre_init()
1476 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1483 static void vsc8584_get_base_addr(struct phy_device *phydev) in vsc8584_get_base_addr() argument
1485 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_get_base_addr()
1488 phy_lock_mdio_bus(phydev); in vsc8584_get_base_addr()
1489 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8584_get_base_addr()
1491 addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4); in vsc8584_get_base_addr()
1494 val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL); in vsc8584_get_base_addr()
1496 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_get_base_addr()
1497 phy_unlock_mdio_bus(phydev); in vsc8584_get_base_addr()
1503 vsc8531->ts_base_addr = phydev->mdio.addr; in vsc8584_get_base_addr()
1507 vsc8531->base_addr = phydev->mdio.addr + addr; in vsc8584_get_base_addr()
1513 vsc8531->base_addr = phydev->mdio.addr - addr; in vsc8584_get_base_addr()
1523 static int vsc8584_config_init(struct phy_device *phydev) in vsc8584_config_init() argument
1525 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_config_init()
1529 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc8584_config_init()
1531 phy_lock_mdio_bus(phydev); in vsc8584_config_init()
1546 if (phy_package_init_once(phydev)) { in vsc8584_config_init()
1551 WARN_ON(phydev->drv->phy_id_mask & 0xf); in vsc8584_config_init()
1553 switch (phydev->phy_id & phydev->drv->phy_id_mask) { in vsc8584_config_init()
1558 ret = vsc8574_config_pre_init(phydev); in vsc8584_config_init()
1564 ret = vsc8584_config_pre_init(phydev); in vsc8584_config_init()
1575 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_init()
1580 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); in vsc8584_config_init()
1582 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { in vsc8584_config_init()
1584 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in vsc8584_config_init()
1586 } else if (phy_interface_is_rgmii(phydev)) { in vsc8584_config_init()
1593 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); in vsc8584_config_init()
1597 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_init()
1602 if (!phy_interface_is_rgmii(phydev)) { in vsc8584_config_init()
1605 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) in vsc8584_config_init()
1610 ret = vsc8584_cmd(phydev, val); in vsc8584_config_init()
1618 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | in vsc8584_config_init()
1627 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | in vsc8584_config_init()
1635 phy_unlock_mdio_bus(phydev); in vsc8584_config_init()
1637 ret = vsc8584_macsec_init(phydev); in vsc8584_config_init()
1641 ret = vsc8584_ptp_init(phydev); in vsc8584_config_init()
1645 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); in vsc8584_config_init()
1649 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val); in vsc8584_config_init()
1653 ret = vsc85xx_update_rgmii_cntl(phydev, VSC8572_RGMII_CNTL, in vsc8584_config_init()
1659 ret = genphy_soft_reset(phydev); in vsc8584_config_init()
1664 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc8584_config_init()
1672 phy_unlock_mdio_bus(phydev); in vsc8584_config_init()
1676 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev) in vsc8584_handle_interrupt() argument
1681 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc8584_handle_interrupt()
1688 ret = vsc8584_handle_ts_interrupt(phydev); in vsc8584_handle_interrupt()
1693 vsc8584_handle_macsec_interrupt(phydev); in vsc8584_handle_interrupt()
1696 phy_mac_interrupt(phydev); in vsc8584_handle_interrupt()
1701 static int vsc85xx_config_init(struct phy_device *phydev) in vsc85xx_config_init() argument
1704 struct vsc8531_private *vsc8531 = phydev->priv; in vsc85xx_config_init()
1706 rc = vsc85xx_default_config(phydev); in vsc85xx_config_init()
1710 rc = vsc85xx_mac_if_set(phydev, phydev->interface); in vsc85xx_config_init()
1714 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic); in vsc85xx_config_init()
1718 phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask; in vsc85xx_config_init()
1721 rc = vsc8531_pre_init_seq_set(phydev); in vsc85xx_config_init()
1726 rc = vsc85xx_eee_init_seq_set(phydev); in vsc85xx_config_init()
1731 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc85xx_config_init()
1739 static int vsc8584_did_interrupt(struct phy_device *phydev) in vsc8584_did_interrupt() argument
1743 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in vsc8584_did_interrupt()
1744 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc8584_did_interrupt()
1749 static int vsc8514_config_pre_init(struct phy_device *phydev) in vsc8514_config_pre_init() argument
1777 struct device *dev = &phydev->mdio.dev; in vsc8514_config_pre_init()
1782 ret = vsc8584_pll5g_reset(phydev); in vsc8514_config_pre_init()
1788 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8514_config_pre_init()
1791 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8514_config_pre_init()
1793 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8514_config_pre_init()
1795 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8514_config_pre_init()
1797 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8514_config_pre_init()
1799 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8514_config_pre_init()
1801 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8514_config_pre_init()
1804 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8514_config_pre_init()
1806 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8514_config_pre_init()
1808 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8514_config_pre_init()
1810 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8514_config_pre_init()
1812 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8514_config_pre_init()
1814 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8514_config_pre_init()
1816 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8514_config_pre_init()
1821 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb, in __phy_write_mcb_s6g() argument
1828 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, reg, in __phy_write_mcb_s6g()
1836 val = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, reg); in __phy_write_mcb_s6g()
1850 static int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) in phy_update_mcb_s6g() argument
1852 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ); in phy_update_mcb_s6g()
1856 static int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) in phy_commit_mcb_s6g() argument
1858 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE); in phy_commit_mcb_s6g()
1861 static int vsc8514_config_init(struct phy_device *phydev) in vsc8514_config_init() argument
1863 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8514_config_init()
1869 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc8514_config_init()
1871 phy_lock_mdio_bus(phydev); in vsc8514_config_init()
1884 if (phy_package_init_once(phydev)) in vsc8514_config_init()
1885 vsc8514_config_pre_init(phydev); in vsc8514_config_init()
1887 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8514_config_init()
1892 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); in vsc8514_config_init()
1896 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); in vsc8514_config_init()
1900 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8514_config_init()
1905 ret = vsc8584_cmd(phydev, in vsc8514_config_init()
1913 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc8514_config_init()
1915 phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); in vsc8514_config_init()
1917 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1922 phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); in vsc8514_config_init()
1924 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1933 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1944 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1950 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1955 phy_commit_mcb_s6g(phydev, PHY_S6G_DFT_CFG2, 0); in vsc8514_config_init()
1960 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, in vsc8514_config_init()
1962 reg = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1965 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
1972 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
1977 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1982 phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc8514_config_init()
1987 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, in vsc8514_config_init()
1989 reg = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1992 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
1999 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
2003 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
2005 ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK, in vsc8514_config_init()
2011 ret = genphy_soft_reset(phydev); in vsc8514_config_init()
2017 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc8514_config_init()
2025 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
2029 static int vsc85xx_ack_interrupt(struct phy_device *phydev) in vsc85xx_ack_interrupt() argument
2033 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in vsc85xx_ack_interrupt()
2034 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_ack_interrupt()
2039 static int vsc85xx_config_intr(struct phy_device *phydev) in vsc85xx_config_intr() argument
2043 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in vsc85xx_config_intr()
2044 vsc8584_config_macsec_intr(phydev); in vsc85xx_config_intr()
2045 vsc8584_config_ts_intr(phydev); in vsc85xx_config_intr()
2047 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, in vsc85xx_config_intr()
2050 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc85xx_config_intr()
2053 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_config_intr()
2059 static int vsc85xx_config_aneg(struct phy_device *phydev) in vsc85xx_config_aneg() argument
2063 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl); in vsc85xx_config_aneg()
2067 return genphy_config_aneg(phydev); in vsc85xx_config_aneg()
2070 static int vsc85xx_read_status(struct phy_device *phydev) in vsc85xx_read_status() argument
2074 rc = vsc85xx_mdix_get(phydev, &phydev->mdix); in vsc85xx_read_status()
2078 return genphy_read_status(phydev); in vsc85xx_read_status()
2081 static int vsc8514_probe(struct phy_device *phydev) in vsc8514_probe() argument
2088 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8514_probe()
2092 phydev->priv = vsc8531; in vsc8514_probe()
2094 vsc8584_get_base_addr(phydev); in vsc8514_probe()
2095 devm_phy_package_join(&phydev->mdio.dev, phydev, in vsc8514_probe()
2102 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8514_probe()
2107 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8514_probe()
2110 static int vsc8574_probe(struct phy_device *phydev) in vsc8574_probe() argument
2117 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8574_probe()
2121 phydev->priv = vsc8531; in vsc8574_probe()
2123 vsc8584_get_base_addr(phydev); in vsc8574_probe()
2124 devm_phy_package_join(&phydev->mdio.dev, phydev, in vsc8574_probe()
2131 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8574_probe()
2136 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8574_probe()
2139 static int vsc8584_probe(struct phy_device *phydev) in vsc8584_probe() argument
2147 if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) { in vsc8584_probe()
2148 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n"); in vsc8584_probe()
2152 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8584_probe()
2156 phydev->priv = vsc8531; in vsc8584_probe()
2158 vsc8584_get_base_addr(phydev); in vsc8584_probe()
2159 devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr, in vsc8584_probe()
2166 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8584_probe()
2171 if (phy_package_probe_once(phydev)) { in vsc8584_probe()
2172 ret = vsc8584_ptp_probe_once(phydev); in vsc8584_probe()
2177 ret = vsc8584_ptp_probe(phydev); in vsc8584_probe()
2181 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8584_probe()
2184 static int vsc85xx_probe(struct phy_device *phydev) in vsc85xx_probe() argument
2191 rate_magic = vsc85xx_edge_rate_magic_get(phydev); in vsc85xx_probe()
2195 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc85xx_probe()
2199 phydev->priv = vsc8531; in vsc85xx_probe()
2206 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc85xx_probe()
2211 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc85xx_probe()