1 // SPDX-License-Identifier: GPL-2.0
3  * Loongson PCI Host Controller Driver
30 #define FLAG_CFG1	BIT(1)
43 	dev->class = PCI_CLASS_BRIDGE_PCI << 8;  in bridge_class_quirk()
58 	pdev->mmio_always_on = 1;  in system_bus_quirk()
59 	pdev->non_compliant_bars = 1;  in system_bus_quirk()
69  * Some Loongson PCIe ports have hardware limitations on their Maximum Read
72  * bridges. However, some MIPS Loongson firmware doesn't set MRRS properly,
78 	struct pci_bus *bus = pdev->bus;  in loongson_set_min_mrrs_quirk()
81 		{ PCI_VDEVICE(LOONGSON, DEV_LS2K_PCIE_PORT0) },  in loongson_set_min_mrrs_quirk()
82 		{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT0) },  in loongson_set_min_mrrs_quirk()
83 		{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT1) },  in loongson_set_min_mrrs_quirk()
84 		{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT2) },  in loongson_set_min_mrrs_quirk()
85 		{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT3) },  in loongson_set_min_mrrs_quirk()
86 		{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT4) },  in loongson_set_min_mrrs_quirk()
87 		{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT5) },  in loongson_set_min_mrrs_quirk()
88 		{ PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT6) },  in loongson_set_min_mrrs_quirk()
94 		bridge = bus->self;  in loongson_set_min_mrrs_quirk()
95 		bus = bus->parent;  in loongson_set_min_mrrs_quirk()
111 	struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);  in loongson_mrrs_quirk()
113 	bridge->no_inc_mrrs = 1;  in loongson_mrrs_quirk()
138 		addroff |= BIT(28); /* Type 1 Access */  in cfg1_map()
141 	return priv->cfg1_base + addroff;  in cfg1_map()
150 		addroff |= BIT(24); /* Type 1 Access */  in cfg0_map()
152 	return priv->cfg0_base + addroff;  in cfg0_map()
158 	unsigned char busnum = bus->number;  in pci_loongson_map_bus()
166 	if (priv->flags & FLAG_DEV_FIX && busnum != 0 &&  in pci_loongson_map_bus()
171 	if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)  in pci_loongson_map_bus()
175 	if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)  in pci_loongson_map_bus()
199 /* H/w only accept 32-bit PCI operations */
207 	{ .compatible = "loongson,ls2k-pci",
209 	{ .compatible = "loongson,ls7a-pci",
211 	{ .compatible = "loongson,rs780e-pci",
219 	struct device *dev = &pdev->dev;  in loongson_pci_probe()
220 	struct device_node *node = dev->of_node;  in loongson_pci_probe()
225 		return -ENODEV;  in loongson_pci_probe()
229 		return -ENODEV;  in loongson_pci_probe()
232 	priv->pdev = pdev;  in loongson_pci_probe()
233 	priv->flags = (unsigned long)of_device_get_match_data(dev);  in loongson_pci_probe()
238 		return -EINVAL;  in loongson_pci_probe()
241 	priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);  in loongson_pci_probe()
242 	if (IS_ERR(priv->cfg0_base))  in loongson_pci_probe()
243 		return PTR_ERR(priv->cfg0_base);  in loongson_pci_probe()
246 	if (priv->flags & FLAG_CFG1) {  in loongson_pci_probe()
247 		regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);  in loongson_pci_probe()
251 			priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);  in loongson_pci_probe()
252 			if (IS_ERR(priv->cfg1_base))  in loongson_pci_probe()
253 				priv->cfg1_base = NULL;  in loongson_pci_probe()
257 	bridge->sysdata = priv;  in loongson_pci_probe()
258 	bridge->ops = &loongson_pci_ops;  in loongson_pci_probe()
259 	bridge->map_irq = loongson_map_irq;  in loongson_pci_probe()
266 		.name = "loongson-pci",