Lines Matching +full:hsic +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only
25 ((x) ? (11 + ((x) - 1) * 6) : 0)
26 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f
28 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf
30 #define FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT 0
31 #define FUSE_USB_CALIB_EXT_RPD_CTRL_MASK 0x1f
33 #define XUSB_PADCTL_USB2_PAD_MUX 0x004
35 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK 0x3
36 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB 0x1
38 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK 0x3
39 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB 0x1
41 #define XUSB_PADCTL_USB2_PORT_CAP 0x008
42 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(x) (0x0 << ((x) * 4))
43 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4))
44 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(x) (0x2 << ((x) * 4))
45 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(x) (0x3 << ((x) * 4))
46 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4))
48 #define XUSB_PADCTL_SS_PORT_MAP 0x014
51 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 5))
52 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 5))
53 #define XUSB_PADCTL_SS_PORT_MAP_PORT_DISABLED 0x7
55 #define XUSB_PADCTL_ELPG_PROGRAM1 0x024
64 #define XUSB_PADCTL_USB3_PAD_MUX 0x028
68 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(x) (0x080 + (x) * 0x40)
72 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x084 + (x) * 0x40)
74 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK 0x3
75 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL 0x1
78 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x088 + (x) * 0x40)
82 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT 0
83 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK 0x3f
85 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x08c + (x) * 0x40)
87 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK 0x1f
89 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK 0xf
92 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD (1 << 0)
94 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
97 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK 0x7
98 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL 0x7
99 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT 0
100 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK 0x7
101 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL 0x2
103 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
106 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK 0x7f
107 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL 0x0a
109 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK 0x7f
110 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL 0x1e
112 #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
129 #define XUSB_PADCTL_HSIC_PADX_CTL1(x) (0x304 + (x) * 0x20)
130 #define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT 0
131 #define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK 0xf
133 #define XUSB_PADCTL_HSIC_PADX_CTL2(x) (0x308 + (x) * 0x20)
135 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK 0xf
136 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT 0
137 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK 0xff
139 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL 0x340
142 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK 0x7f
143 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL 0x0a
145 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK 0x7f
146 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL 0x1e
148 #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL 0x344
150 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
152 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK 0xff
153 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL 0x19
154 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL 0x1e
156 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK 0x3
161 #define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK 0x3
162 #define XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ (1 << 0)
164 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
166 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK 0xffffff
167 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL 0x136
170 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN (1 << 0)
172 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
176 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK 0x3
177 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL 0x2
178 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL 0x0
181 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK 0xf
183 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
185 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK 0xff
186 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL 0x2a
188 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
194 #define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(x) (0x460 + (x) * 0x40)
196 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK 0x3
197 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL 0x1
201 #define XUSB_PADCTL_UPHY_PLL_S0_CTL1 0x860
203 #define XUSB_PADCTL_UPHY_PLL_S0_CTL2 0x864
205 #define XUSB_PADCTL_UPHY_PLL_S0_CTL4 0x86c
207 #define XUSB_PADCTL_UPHY_PLL_S0_CTL5 0x870
209 #define XUSB_PADCTL_UPHY_PLL_S0_CTL8 0x87c
211 #define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1 0x960
213 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(x) (0xa60 + (x) * 0x40)
215 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK 0x3
216 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL 0x2
218 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(x) (0xa64 + (x) * 0x40)
219 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT 0
220 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK 0xffff
221 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL 0x00fc
223 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(x) (0xa68 + (x) * 0x40)
224 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL 0xc0077f1f
226 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(x) (0xa6c + (x) * 0x40)
228 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK 0xffff
229 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL 0x01c7
231 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(x) (0xa74 + (x) * 0x40)
232 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL 0xfcf01368
234 #define XUSB_PADCTL_USB2_VBUS_ID 0xc60
237 #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK 0xf
239 #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_GROUNDED 0
259 /* must be called under padctl->lock */
262 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_enable()
267 if (pcie->enable > 0) { in tegra210_pex_uphy_enable()
268 pcie->enable++; in tegra210_pex_uphy_enable()
269 return 0; in tegra210_pex_uphy_enable()
272 err = clk_prepare_enable(pcie->pll); in tegra210_pex_uphy_enable()
273 if (err < 0) in tegra210_pex_uphy_enable()
276 err = reset_control_deassert(pcie->rst); in tegra210_pex_uphy_enable()
277 if (err < 0) in tegra210_pex_uphy_enable()
355 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
374 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
393 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
413 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
432 err = -ETIMEDOUT; in tegra210_pex_uphy_enable()
458 pcie->enable++; in tegra210_pex_uphy_enable()
460 return 0; in tegra210_pex_uphy_enable()
463 reset_control_assert(pcie->rst); in tegra210_pex_uphy_enable()
465 clk_disable_unprepare(pcie->pll); in tegra210_pex_uphy_enable()
471 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie); in tegra210_pex_uphy_disable()
473 mutex_lock(&padctl->lock); in tegra210_pex_uphy_disable()
475 if (WARN_ON(pcie->enable == 0)) in tegra210_pex_uphy_disable()
478 if (--pcie->enable > 0) in tegra210_pex_uphy_disable()
481 reset_control_assert(pcie->rst); in tegra210_pex_uphy_disable()
482 clk_disable_unprepare(pcie->pll); in tegra210_pex_uphy_disable()
485 mutex_unlock(&padctl->lock); in tegra210_pex_uphy_disable()
488 /* must be called under padctl->lock */
491 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata); in tegra210_sata_uphy_enable()
496 if (sata->enable > 0) { in tegra210_sata_uphy_enable()
497 sata->enable++; in tegra210_sata_uphy_enable()
498 return 0; in tegra210_sata_uphy_enable()
501 err = clk_prepare_enable(sata->pll); in tegra210_sata_uphy_enable()
502 if (err < 0) in tegra210_sata_uphy_enable()
505 err = reset_control_deassert(sata->rst); in tegra210_sata_uphy_enable()
506 if (err < 0) in tegra210_sata_uphy_enable()
597 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
616 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
635 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
655 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
674 err = -ETIMEDOUT; in tegra210_sata_uphy_enable()
700 sata->enable++; in tegra210_sata_uphy_enable()
702 return 0; in tegra210_sata_uphy_enable()
705 reset_control_assert(sata->rst); in tegra210_sata_uphy_enable()
707 clk_disable_unprepare(sata->pll); in tegra210_sata_uphy_enable()
713 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata); in tegra210_sata_uphy_disable()
715 mutex_lock(&padctl->lock); in tegra210_sata_uphy_disable()
717 if (WARN_ON(sata->enable == 0)) in tegra210_sata_uphy_disable()
720 if (--sata->enable > 0) in tegra210_sata_uphy_disable()
723 reset_control_assert(sata->rst); in tegra210_sata_uphy_disable()
724 clk_disable_unprepare(sata->pll); in tegra210_sata_uphy_disable()
727 mutex_unlock(&padctl->lock); in tegra210_sata_uphy_disable()
734 mutex_lock(&padctl->lock); in tegra210_xusb_padctl_enable()
736 if (padctl->enable++ > 0) in tegra210_xusb_padctl_enable()
756 mutex_unlock(&padctl->lock); in tegra210_xusb_padctl_enable()
757 return 0; in tegra210_xusb_padctl_enable()
764 mutex_lock(&padctl->lock); in tegra210_xusb_padctl_disable()
766 if (WARN_ON(padctl->enable == 0)) in tegra210_xusb_padctl_disable()
769 if (--padctl->enable > 0) in tegra210_xusb_padctl_disable()
789 mutex_unlock(&padctl->lock); in tegra210_xusb_padctl_disable()
790 return 0; in tegra210_xusb_padctl_disable()
815 return 0; in tegra210_hsic_set_idle()
827 return -ENODEV; in tegra210_usb3_set_lfps_detect()
829 lane = port->lane; in tegra210_usb3_set_lfps_detect()
831 if (lane->pad == padctl->pcie) in tegra210_usb3_set_lfps_detect()
832 offset = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(lane->index); in tegra210_usb3_set_lfps_detect()
852 return 0; in tegra210_usb3_set_lfps_detect()
872 TEGRA210_LANE("usb2-0", 0x004, 0, 0x3, usb2),
873 TEGRA210_LANE("usb2-1", 0x004, 2, 0x3, usb2),
874 TEGRA210_LANE("usb2-2", 0x004, 4, 0x3, usb2),
875 TEGRA210_LANE("usb2-3", 0x004, 6, 0x3, usb2),
887 return ERR_PTR(-ENOMEM); in tegra210_usb2_lane_probe()
889 INIT_LIST_HEAD(&usb2->base.list); in tegra210_usb2_lane_probe()
890 usb2->base.soc = &pad->soc->lanes[index]; in tegra210_usb2_lane_probe()
891 usb2->base.index = index; in tegra210_usb2_lane_probe()
892 usb2->base.pad = pad; in tegra210_usb2_lane_probe()
893 usb2->base.np = np; in tegra210_usb2_lane_probe()
895 err = tegra_xusb_lane_parse_dt(&usb2->base, np); in tegra210_usb2_lane_probe()
896 if (err < 0) { in tegra210_usb2_lane_probe()
901 return &usb2->base; in tegra210_usb2_lane_probe()
919 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_init()
936 return tegra210_xusb_padctl_disable(lane->pad->padctl); in tegra210_usb2_phy_exit()
944 dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear"); in tegra210_xusb_padctl_vbus_override()
960 return 0; in tegra210_xusb_padctl_vbus_override()
968 dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear"); in tegra210_xusb_padctl_id_override()
994 return 0; in tegra210_xusb_padctl_id_override()
1001 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_set_mode()
1003 lane->index); in tegra210_usb2_phy_set_mode()
1004 int err = 0; in tegra210_usb2_phy_set_mode()
1006 mutex_lock(&padctl->lock); in tegra210_usb2_phy_set_mode()
1008 dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode); in tegra210_usb2_phy_set_mode()
1014 err = regulator_enable(port->supply); in tegra210_usb2_phy_set_mode()
1023 if (regulator_is_enabled(port->supply)) in tegra210_usb2_phy_set_mode()
1024 regulator_disable(port->supply); in tegra210_usb2_phy_set_mode()
1031 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_set_mode()
1040 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); in tegra210_usb2_phy_power_on()
1041 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_power_on()
1044 unsigned int index = lane->index; in tegra210_usb2_phy_power_on()
1050 dev_err(&phy->dev, "no port found for USB2 lane %u\n", index); in tegra210_usb2_phy_power_on()
1051 return -ENODEV; in tegra210_usb2_phy_power_on()
1056 if (port->usb3_port_fake != -1) { in tegra210_usb2_phy_power_on()
1059 port->usb3_port_fake); in tegra210_usb2_phy_power_on()
1061 port->usb3_port_fake, index); in tegra210_usb2_phy_power_on()
1066 port->usb3_port_fake); in tegra210_usb2_phy_power_on()
1073 port->usb3_port_fake); in tegra210_usb2_phy_power_on()
1080 port->usb3_port_fake); in tegra210_usb2_phy_power_on()
1101 if (port->mode == USB_DR_MODE_UNKNOWN) in tegra210_usb2_phy_power_on()
1103 else if (port->mode == USB_DR_MODE_PERIPHERAL) in tegra210_usb2_phy_power_on()
1105 else if (port->mode == USB_DR_MODE_HOST) in tegra210_usb2_phy_power_on()
1107 else if (port->mode == USB_DR_MODE_OTG) in tegra210_usb2_phy_power_on()
1117 value |= (priv->fuse.hs_curr_level[index] + in tegra210_usb2_phy_power_on()
1118 usb2->hs_curr_level_offset) << in tegra210_usb2_phy_power_on()
1130 value |= (priv->fuse.hs_term_range_adj << in tegra210_usb2_phy_power_on()
1132 (priv->fuse.rpd_ctrl << in tegra210_usb2_phy_power_on()
1140 if (port->mode == USB_DR_MODE_HOST) in tegra210_usb2_phy_power_on()
1149 if (port->supply && port->mode == USB_DR_MODE_HOST) { in tegra210_usb2_phy_power_on()
1150 err = regulator_enable(port->supply); in tegra210_usb2_phy_power_on()
1155 mutex_lock(&padctl->lock); in tegra210_usb2_phy_power_on()
1157 if (pad->enable > 0) { in tegra210_usb2_phy_power_on()
1158 pad->enable++; in tegra210_usb2_phy_power_on()
1159 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_on()
1160 return 0; in tegra210_usb2_phy_power_on()
1163 err = clk_prepare_enable(pad->clk); in tegra210_usb2_phy_power_on()
1190 clk_disable_unprepare(pad->clk); in tegra210_usb2_phy_power_on()
1192 pad->enable++; in tegra210_usb2_phy_power_on()
1193 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_on()
1195 return 0; in tegra210_usb2_phy_power_on()
1198 regulator_disable(port->supply); in tegra210_usb2_phy_power_on()
1199 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_on()
1206 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); in tegra210_usb2_phy_power_off()
1207 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb2_phy_power_off()
1211 port = tegra_xusb_find_usb2_port(padctl, lane->index); in tegra210_usb2_phy_power_off()
1213 dev_err(&phy->dev, "no port found for USB2 lane %u\n", in tegra210_usb2_phy_power_off()
1214 lane->index); in tegra210_usb2_phy_power_off()
1215 return -ENODEV; in tegra210_usb2_phy_power_off()
1218 mutex_lock(&padctl->lock); in tegra210_usb2_phy_power_off()
1220 if (port->usb3_port_fake != -1) { in tegra210_usb2_phy_power_off()
1223 port->usb3_port_fake); in tegra210_usb2_phy_power_off()
1230 port->usb3_port_fake); in tegra210_usb2_phy_power_off()
1237 port->usb3_port_fake); in tegra210_usb2_phy_power_off()
1241 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(port->usb3_port_fake, in tegra210_usb2_phy_power_off()
1246 if (WARN_ON(pad->enable == 0)) in tegra210_usb2_phy_power_off()
1249 if (--pad->enable > 0) in tegra210_usb2_phy_power_off()
1257 regulator_disable(port->supply); in tegra210_usb2_phy_power_off()
1258 mutex_unlock(&padctl->lock); in tegra210_usb2_phy_power_off()
1259 return 0; in tegra210_usb2_phy_power_off()
1282 return ERR_PTR(-ENOMEM); in tegra210_usb2_pad_probe()
1284 pad = &usb2->base; in tegra210_usb2_pad_probe()
1285 pad->ops = &tegra210_usb2_lane_ops; in tegra210_usb2_pad_probe()
1286 pad->soc = soc; in tegra210_usb2_pad_probe()
1289 if (err < 0) { in tegra210_usb2_pad_probe()
1294 usb2->clk = devm_clk_get(&pad->dev, "trk"); in tegra210_usb2_pad_probe()
1295 if (IS_ERR(usb2->clk)) { in tegra210_usb2_pad_probe()
1296 err = PTR_ERR(usb2->clk); in tegra210_usb2_pad_probe()
1297 dev_err(&pad->dev, "failed to get trk clock: %d\n", err); in tegra210_usb2_pad_probe()
1302 if (err < 0) in tegra210_usb2_pad_probe()
1305 dev_set_drvdata(&pad->dev, pad); in tegra210_usb2_pad_probe()
1310 device_unregister(&pad->dev); in tegra210_usb2_pad_probe()
1340 TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, hsic),
1347 struct tegra_xusb_hsic_lane *hsic; in tegra210_hsic_lane_probe() local
1350 hsic = kzalloc(sizeof(*hsic), GFP_KERNEL); in tegra210_hsic_lane_probe()
1351 if (!hsic) in tegra210_hsic_lane_probe()
1352 return ERR_PTR(-ENOMEM); in tegra210_hsic_lane_probe()
1354 INIT_LIST_HEAD(&hsic->base.list); in tegra210_hsic_lane_probe()
1355 hsic->base.soc = &pad->soc->lanes[index]; in tegra210_hsic_lane_probe()
1356 hsic->base.index = index; in tegra210_hsic_lane_probe()
1357 hsic->base.pad = pad; in tegra210_hsic_lane_probe()
1358 hsic->base.np = np; in tegra210_hsic_lane_probe()
1360 err = tegra_xusb_lane_parse_dt(&hsic->base, np); in tegra210_hsic_lane_probe()
1361 if (err < 0) { in tegra210_hsic_lane_probe()
1362 kfree(hsic); in tegra210_hsic_lane_probe()
1366 return &hsic->base; in tegra210_hsic_lane_probe()
1371 struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane); in tegra210_hsic_lane_remove() local
1373 kfree(hsic); in tegra210_hsic_lane_remove()
1384 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_phy_init()
1401 return tegra210_xusb_padctl_disable(lane->pad->padctl); in tegra210_hsic_phy_exit()
1407 struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane); in tegra210_hsic_phy_power_on() local
1408 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); in tegra210_hsic_phy_power_on()
1409 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_phy_power_on()
1410 unsigned int index = lane->index; in tegra210_hsic_phy_power_on()
1414 err = regulator_enable(pad->supply); in tegra210_hsic_phy_power_on()
1418 padctl_writel(padctl, hsic->strobe_trim, in tegra210_hsic_phy_power_on()
1424 value |= (hsic->tx_rtune_p << in tegra210_hsic_phy_power_on()
1433 value |= (hsic->rx_strobe_trim << in tegra210_hsic_phy_power_on()
1435 (hsic->rx_data_trim << in tegra210_hsic_phy_power_on()
1457 err = clk_prepare_enable(pad->clk); in tegra210_hsic_phy_power_on()
1480 clk_disable_unprepare(pad->clk); in tegra210_hsic_phy_power_on()
1482 return 0; in tegra210_hsic_phy_power_on()
1485 regulator_disable(pad->supply); in tegra210_hsic_phy_power_on()
1492 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); in tegra210_hsic_phy_power_off()
1493 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_hsic_phy_power_off()
1494 unsigned int index = lane->index; in tegra210_hsic_phy_power_off()
1509 regulator_disable(pad->supply); in tegra210_hsic_phy_power_off()
1511 return 0; in tegra210_hsic_phy_power_off()
1527 struct tegra_xusb_hsic_pad *hsic; in tegra210_hsic_pad_probe() local
1531 hsic = kzalloc(sizeof(*hsic), GFP_KERNEL); in tegra210_hsic_pad_probe()
1532 if (!hsic) in tegra210_hsic_pad_probe()
1533 return ERR_PTR(-ENOMEM); in tegra210_hsic_pad_probe()
1535 pad = &hsic->base; in tegra210_hsic_pad_probe()
1536 pad->ops = &tegra210_hsic_lane_ops; in tegra210_hsic_pad_probe()
1537 pad->soc = soc; in tegra210_hsic_pad_probe()
1540 if (err < 0) { in tegra210_hsic_pad_probe()
1541 kfree(hsic); in tegra210_hsic_pad_probe()
1545 hsic->clk = devm_clk_get(&pad->dev, "trk"); in tegra210_hsic_pad_probe()
1546 if (IS_ERR(hsic->clk)) { in tegra210_hsic_pad_probe()
1547 err = PTR_ERR(hsic->clk); in tegra210_hsic_pad_probe()
1548 dev_err(&pad->dev, "failed to get trk clock: %d\n", err); in tegra210_hsic_pad_probe()
1553 if (err < 0) in tegra210_hsic_pad_probe()
1556 dev_set_drvdata(&pad->dev, pad); in tegra210_hsic_pad_probe()
1561 device_unregister(&pad->dev); in tegra210_hsic_pad_probe()
1568 struct tegra_xusb_hsic_pad *hsic = to_hsic_pad(pad); in tegra210_hsic_pad_remove() local
1570 kfree(hsic); in tegra210_hsic_pad_remove()
1579 .name = "hsic",
1586 "pcie-x1",
1587 "usb3-ss",
1589 "pcie-x4",
1593 TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, pcie),
1594 TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, pcie),
1595 TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, pcie),
1596 TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, pcie),
1597 TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, pcie),
1598 TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, pcie),
1599 TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, pcie),
1611 return ERR_PTR(-ENOMEM); in tegra210_pcie_lane_probe()
1613 INIT_LIST_HEAD(&pcie->base.list); in tegra210_pcie_lane_probe()
1614 pcie->base.soc = &pad->soc->lanes[index]; in tegra210_pcie_lane_probe()
1615 pcie->base.index = index; in tegra210_pcie_lane_probe()
1616 pcie->base.pad = pad; in tegra210_pcie_lane_probe()
1617 pcie->base.np = np; in tegra210_pcie_lane_probe()
1619 err = tegra_xusb_lane_parse_dt(&pcie->base, np); in tegra210_pcie_lane_probe()
1620 if (err < 0) { in tegra210_pcie_lane_probe()
1625 return &pcie->base; in tegra210_pcie_lane_probe()
1644 return tegra210_xusb_padctl_enable(lane->pad->padctl); in tegra210_pcie_phy_init()
1651 return tegra210_xusb_padctl_disable(lane->pad->padctl); in tegra210_pcie_phy_exit()
1657 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_pcie_phy_power_on()
1661 mutex_lock(&padctl->lock); in tegra210_pcie_phy_power_on()
1664 if (err < 0) in tegra210_pcie_phy_power_on()
1668 value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); in tegra210_pcie_phy_power_on()
1672 mutex_unlock(&padctl->lock); in tegra210_pcie_phy_power_on()
1679 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_pcie_phy_power_off()
1683 value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); in tegra210_pcie_phy_power_off()
1688 return 0; in tegra210_pcie_phy_power_off()
1710 return ERR_PTR(-ENOMEM); in tegra210_pcie_pad_probe()
1712 pad = &pcie->base; in tegra210_pcie_pad_probe()
1713 pad->ops = &tegra210_pcie_lane_ops; in tegra210_pcie_pad_probe()
1714 pad->soc = soc; in tegra210_pcie_pad_probe()
1717 if (err < 0) { in tegra210_pcie_pad_probe()
1722 pcie->pll = devm_clk_get(&pad->dev, "pll"); in tegra210_pcie_pad_probe()
1723 if (IS_ERR(pcie->pll)) { in tegra210_pcie_pad_probe()
1724 err = PTR_ERR(pcie->pll); in tegra210_pcie_pad_probe()
1725 dev_err(&pad->dev, "failed to get PLL: %d\n", err); in tegra210_pcie_pad_probe()
1729 pcie->rst = devm_reset_control_get(&pad->dev, "phy"); in tegra210_pcie_pad_probe()
1730 if (IS_ERR(pcie->rst)) { in tegra210_pcie_pad_probe()
1731 err = PTR_ERR(pcie->rst); in tegra210_pcie_pad_probe()
1732 dev_err(&pad->dev, "failed to get PCIe pad reset: %d\n", err); in tegra210_pcie_pad_probe()
1737 if (err < 0) in tegra210_pcie_pad_probe()
1740 dev_set_drvdata(&pad->dev, pad); in tegra210_pcie_pad_probe()
1745 device_unregister(&pad->dev); in tegra210_pcie_pad_probe()
1770 TEGRA210_LANE("sata-0", 0x028, 30, 0x3, pcie),
1782 return ERR_PTR(-ENOMEM); in tegra210_sata_lane_probe()
1784 INIT_LIST_HEAD(&sata->base.list); in tegra210_sata_lane_probe()
1785 sata->base.soc = &pad->soc->lanes[index]; in tegra210_sata_lane_probe()
1786 sata->base.index = index; in tegra210_sata_lane_probe()
1787 sata->base.pad = pad; in tegra210_sata_lane_probe()
1788 sata->base.np = np; in tegra210_sata_lane_probe()
1790 err = tegra_xusb_lane_parse_dt(&sata->base, np); in tegra210_sata_lane_probe()
1791 if (err < 0) { in tegra210_sata_lane_probe()
1796 return &sata->base; in tegra210_sata_lane_probe()
1815 return tegra210_xusb_padctl_enable(lane->pad->padctl); in tegra210_sata_phy_init()
1822 return tegra210_xusb_padctl_disable(lane->pad->padctl); in tegra210_sata_phy_exit()
1828 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_sata_phy_power_on()
1832 mutex_lock(&padctl->lock); in tegra210_sata_phy_power_on()
1835 if (err < 0) in tegra210_sata_phy_power_on()
1839 value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); in tegra210_sata_phy_power_on()
1843 mutex_unlock(&padctl->lock); in tegra210_sata_phy_power_on()
1850 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_sata_phy_power_off()
1854 value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); in tegra210_sata_phy_power_off()
1857 tegra210_sata_uphy_disable(lane->pad->padctl); in tegra210_sata_phy_power_off()
1859 return 0; in tegra210_sata_phy_power_off()
1881 return ERR_PTR(-ENOMEM); in tegra210_sata_pad_probe()
1883 pad = &sata->base; in tegra210_sata_pad_probe()
1884 pad->ops = &tegra210_sata_lane_ops; in tegra210_sata_pad_probe()
1885 pad->soc = soc; in tegra210_sata_pad_probe()
1888 if (err < 0) { in tegra210_sata_pad_probe()
1893 sata->rst = devm_reset_control_get(&pad->dev, "phy"); in tegra210_sata_pad_probe()
1894 if (IS_ERR(sata->rst)) { in tegra210_sata_pad_probe()
1895 err = PTR_ERR(sata->rst); in tegra210_sata_pad_probe()
1896 dev_err(&pad->dev, "failed to get SATA pad reset: %d\n", err); in tegra210_sata_pad_probe()
1901 if (err < 0) in tegra210_sata_pad_probe()
1904 dev_set_drvdata(&pad->dev, pad); in tegra210_sata_pad_probe()
1909 device_unregister(&pad->dev); in tegra210_sata_pad_probe()
1942 return 0; in tegra210_usb2_port_enable()
1952 return tegra_xusb_find_lane(port->padctl, "usb2", port->index); in tegra210_usb2_port_map()
1965 return 0; in tegra210_hsic_port_enable()
1975 return tegra_xusb_find_lane(port->padctl, "hsic", port->index); in tegra210_hsic_port_map()
1988 struct tegra_xusb_padctl *padctl = port->padctl; in tegra210_usb3_port_enable()
1989 struct tegra_xusb_lane *lane = usb3->base.lane; in tegra210_usb3_port_enable()
1990 unsigned int index = port->index; in tegra210_usb3_port_enable()
1996 if (!usb3->internal) in tegra210_usb3_port_enable()
2002 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port); in tegra210_usb3_port_enable()
2006 * TODO: move this code into the PCIe/SATA PHY ->power_on() callbacks in tegra210_usb3_port_enable()
2010 err = regulator_enable(usb3->supply); in tegra210_usb3_port_enable()
2011 if (err < 0) in tegra210_usb3_port_enable()
2041 if (lane->pad == padctl->sata) in tegra210_usb3_port_enable()
2047 dev_err(&port->dev, "%s: failed to enable UPHY: %d\n", in tegra210_usb3_port_enable()
2068 return 0; in tegra210_usb3_port_enable()
2074 struct tegra_xusb_padctl *padctl = port->padctl; in tegra210_usb3_port_disable()
2075 struct tegra_xusb_lane *lane = port->lane; in tegra210_usb3_port_disable()
2076 unsigned int index = port->index; in tegra210_usb3_port_disable()
2095 if (lane->pad == padctl->sata) in tegra210_usb3_port_disable()
2100 regulator_disable(usb3->supply); in tegra210_usb3_port_disable()
2104 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, 0x7); in tegra210_usb3_port_disable()
2109 { 0, "pcie", 6 },
2111 { 2, "pcie", 0 },
2115 { 0, NULL, 0 }
2121 return tegra_xusb_port_find_lane(port, tegra210_usb3_map, "usb3-ss"); in tegra210_usb3_port_map()
2139 padctl = lane->pad->padctl; in tegra210_utmi_port_reset()
2142 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(lane->index)); in tegra210_utmi_port_reset()
2151 return 0; in tegra210_utmi_port_reset()
2162 if (err < 0) in tegra210_xusb_read_fuse_calibration()
2165 for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) { in tegra210_xusb_read_fuse_calibration()
2166 fuse->hs_curr_level[i] = in tegra210_xusb_read_fuse_calibration()
2171 fuse->hs_term_range_adj = in tegra210_xusb_read_fuse_calibration()
2176 if (err < 0) in tegra210_xusb_read_fuse_calibration()
2179 fuse->rpd_ctrl = in tegra210_xusb_read_fuse_calibration()
2183 return 0; in tegra210_xusb_read_fuse_calibration()
2195 return ERR_PTR(-ENOMEM); in tegra210_xusb_padctl_probe()
2197 padctl->base.dev = dev; in tegra210_xusb_padctl_probe()
2198 padctl->base.soc = soc; in tegra210_xusb_padctl_probe()
2200 err = tegra210_xusb_read_fuse_calibration(&padctl->fuse); in tegra210_xusb_padctl_probe()
2201 if (err < 0) in tegra210_xusb_padctl_probe()
2204 return &padctl->base; in tegra210_xusb_padctl_probe()
2221 "avdd-pll-utmip",
2222 "avdd-pll-uerefe",
2223 "dvdd-pex-pll",
2224 "hvdd-pex-pll-e",
2235 .hsic = {