Lines Matching +full:pdm +full:- +full:clk +full:- +full:map
1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/clk.h>
34 #include <dt-bindings/pinctrl/rockchip.h>
88 * @offset: if initialized to -1 it will be autocalculated, by specifying
121 * @offset: if initialized to -1 it will be autocalculated, by specifying
136 * @clk: clock of the gpio bank
160 struct clk *clk; member
188 { .offset = -1 }, \
189 { .offset = -1 }, \
190 { .offset = -1 }, \
191 { .offset = -1 }, \
201 { .type = iom0, .offset = -1 }, \
202 { .type = iom1, .offset = -1 }, \
203 { .type = iom2, .offset = -1 }, \
204 { .type = iom3, .offset = -1 }, \
214 { .offset = -1 }, \
215 { .offset = -1 }, \
216 { .offset = -1 }, \
217 { .offset = -1 }, \
220 { .drv_type = type0, .offset = -1 }, \
221 { .drv_type = type1, .offset = -1 }, \
222 { .drv_type = type2, .offset = -1 }, \
223 { .drv_type = type3, .offset = -1 }, \
235 { .offset = -1 }, \
236 { .offset = -1 }, \
237 { .offset = -1 }, \
238 { .offset = -1 }, \
241 { .drv_type = drv0, .offset = -1 }, \
242 { .drv_type = drv1, .offset = -1 }, \
243 { .drv_type = drv2, .offset = -1 }, \
244 { .drv_type = drv3, .offset = -1 }, \
261 { .type = iom0, .offset = -1 }, \
262 { .type = iom1, .offset = -1 }, \
263 { .type = iom2, .offset = -1 }, \
264 { .type = iom3, .offset = -1 }, \
285 { .type = iom0, .offset = -1 }, \
286 { .type = iom1, .offset = -1 }, \
287 { .type = iom2, .offset = -1 }, \
288 { .type = iom3, .offset = -1 }, \
446 for (i = 0; i < info->ngroups; i++) { in pinctrl_name_to_group()
447 if (!strcmp(info->groups[i].name, name)) in pinctrl_name_to_group()
448 return &info->groups[i]; in pinctrl_name_to_group()
461 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in pin_to_bank()
463 while (pin >= (b->pin_base + b->nr_pins)) in pin_to_bank()
473 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in bank_num_to_bank()
476 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { in bank_num_to_bank()
477 if (b->bank_num == num) in bank_num_to_bank()
481 return ERR_PTR(-EINVAL); in bank_num_to_bank()
492 return info->ngroups; in rockchip_get_groups_count()
500 return info->groups[selector].name; in rockchip_get_group_name()
509 if (selector >= info->ngroups) in rockchip_get_group_pins()
510 return -EINVAL; in rockchip_get_group_pins()
512 *pins = info->groups[selector].pins; in rockchip_get_group_pins()
513 *npins = info->groups[selector].npins; in rockchip_get_group_pins()
520 struct pinctrl_map **map, unsigned *num_maps) in rockchip_dt_node_to_map() argument
533 grp = pinctrl_name_to_group(info, np->name); in rockchip_dt_node_to_map()
535 dev_err(info->dev, "unable to find group for node %pOFn\n", in rockchip_dt_node_to_map()
537 return -EINVAL; in rockchip_dt_node_to_map()
540 map_num += grp->npins; in rockchip_dt_node_to_map()
544 return -ENOMEM; in rockchip_dt_node_to_map()
546 *map = new_map; in rockchip_dt_node_to_map()
549 /* create mux map */ in rockchip_dt_node_to_map()
553 return -EINVAL; in rockchip_dt_node_to_map()
556 new_map[0].data.mux.function = parent->name; in rockchip_dt_node_to_map()
557 new_map[0].data.mux.group = np->name; in rockchip_dt_node_to_map()
560 /* create config map */ in rockchip_dt_node_to_map()
562 for (i = 0; i < grp->npins; i++) { in rockchip_dt_node_to_map()
565 pin_get_name(pctldev, grp->pins[i]); in rockchip_dt_node_to_map()
566 new_map[i].data.configs.configs = grp->data[i].configs; in rockchip_dt_node_to_map()
567 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; in rockchip_dt_node_to_map()
570 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", in rockchip_dt_node_to_map()
571 (*map)->data.mux.function, (*map)->data.mux.group, map_num); in rockchip_dt_node_to_map()
577 struct pinctrl_map *map, unsigned num_maps) in rockchip_dt_free_map() argument
579 kfree(map); in rockchip_dt_free_map()
826 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
827 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_recalced_mux()
831 for (i = 0; i < ctrl->niomux_recalced; i++) { in rockchip_get_recalced_mux()
832 data = &ctrl->iomux_recalced[i]; in rockchip_get_recalced_mux()
833 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
834 data->pin == pin) in rockchip_get_recalced_mux()
838 if (i >= ctrl->niomux_recalced) in rockchip_get_recalced_mux()
841 *reg = data->reg; in rockchip_get_recalced_mux()
842 *mask = data->mask; in rockchip_get_recalced_mux()
843 *bit = data->bit; in rockchip_get_recalced_mux()
847 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
848 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
849 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
850 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
851 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
852 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
853 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
854 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
858 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
859 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
860 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
861 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
862 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
863 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
864 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
868 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
869 …UTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
873 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
874 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
875 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
876 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
877 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
878 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
879 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
880 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
881 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
882 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
883 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
884 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
885 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
886 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
887 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
888 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
889 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
890 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
905 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
906 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
907 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
908 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
909 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
910 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
911 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
912 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
930 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
931 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
1030 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1031 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1032 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1033 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1034 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
1049 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
1050 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_mux_route()
1054 for (i = 0; i < ctrl->niomux_routes; i++) { in rockchip_get_mux_route()
1055 data = &ctrl->iomux_routes[i]; in rockchip_get_mux_route()
1056 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1057 (data->pin == pin) && (data->func == mux)) in rockchip_get_mux_route()
1061 if (i >= ctrl->niomux_routes) in rockchip_get_mux_route()
1064 *loc = data->route_location; in rockchip_get_mux_route()
1065 *reg = data->route_offset; in rockchip_get_mux_route()
1066 *value = data->route_val; in rockchip_get_mux_route()
1073 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux()
1081 return -EINVAL; in rockchip_get_mux()
1083 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux()
1084 dev_err(info->dev, "pin %d is unrouted\n", pin); in rockchip_get_mux()
1085 return -EINVAL; in rockchip_get_mux()
1088 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux()
1091 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_get_mux()
1092 ? info->regmap_pmu : info->regmap_base; in rockchip_get_mux()
1095 mux_type = bank->iomux[iomux_num].type; in rockchip_get_mux()
1096 reg = bank->iomux[iomux_num].offset; in rockchip_get_mux()
1112 if (bank->recalced_mask & BIT(pin)) in rockchip_get_mux()
1125 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_verify_mux()
1129 return -EINVAL; in rockchip_verify_mux()
1131 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_verify_mux()
1132 dev_err(info->dev, "pin %d is unrouted\n", pin); in rockchip_verify_mux()
1133 return -EINVAL; in rockchip_verify_mux()
1136 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { in rockchip_verify_mux()
1138 dev_err(info->dev, in rockchip_verify_mux()
1140 return -ENOTSUPP; in rockchip_verify_mux()
1162 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_mux()
1173 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_set_mux()
1176 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", in rockchip_set_mux()
1177 bank->bank_num, pin, mux); in rockchip_set_mux()
1179 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_set_mux()
1180 ? info->regmap_pmu : info->regmap_base; in rockchip_set_mux()
1183 mux_type = bank->iomux[iomux_num].type; in rockchip_set_mux()
1184 reg = bank->iomux[iomux_num].offset; in rockchip_set_mux()
1200 if (bank->recalced_mask & BIT(pin)) in rockchip_set_mux()
1203 if (bank->route_mask & BIT(pin)) { in rockchip_set_mux()
1211 route_regmap = info->regmap_pmu; in rockchip_set_mux()
1214 route_regmap = info->regmap_base; in rockchip_set_mux()
1242 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_pull_reg_and_bit()
1245 if (bank->bank_num == 0) { in px30_calc_pull_reg_and_bit()
1246 *regmap = info->regmap_pmu; in px30_calc_pull_reg_and_bit()
1249 *regmap = info->regmap_base; in px30_calc_pull_reg_and_bit()
1253 *reg -= 0x10; in px30_calc_pull_reg_and_bit()
1254 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; in px30_calc_pull_reg_and_bit()
1272 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_drv_reg_and_bit()
1275 if (bank->bank_num == 0) { in px30_calc_drv_reg_and_bit()
1276 *regmap = info->regmap_pmu; in px30_calc_drv_reg_and_bit()
1279 *regmap = info->regmap_base; in px30_calc_drv_reg_and_bit()
1283 *reg -= 0x10; in px30_calc_drv_reg_and_bit()
1284 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; in px30_calc_drv_reg_and_bit()
1303 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_schmitt_reg_and_bit()
1306 if (bank->bank_num == 0) { in px30_calc_schmitt_reg_and_bit()
1307 *regmap = info->regmap_pmu; in px30_calc_schmitt_reg_and_bit()
1311 *regmap = info->regmap_base; in px30_calc_schmitt_reg_and_bit()
1314 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; in px30_calc_schmitt_reg_and_bit()
1333 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_pull_reg_and_bit()
1336 if (bank->bank_num == 0) { in rv1108_calc_pull_reg_and_bit()
1337 *regmap = info->regmap_pmu; in rv1108_calc_pull_reg_and_bit()
1341 *regmap = info->regmap_base; in rv1108_calc_pull_reg_and_bit()
1343 *reg -= 0x10; in rv1108_calc_pull_reg_and_bit()
1344 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; in rv1108_calc_pull_reg_and_bit()
1362 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_drv_reg_and_bit()
1365 if (bank->bank_num == 0) { in rv1108_calc_drv_reg_and_bit()
1366 *regmap = info->regmap_pmu; in rv1108_calc_drv_reg_and_bit()
1369 *regmap = info->regmap_base; in rv1108_calc_drv_reg_and_bit()
1373 *reg -= 0x10; in rv1108_calc_drv_reg_and_bit()
1374 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; in rv1108_calc_drv_reg_and_bit()
1393 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_schmitt_reg_and_bit()
1396 if (bank->bank_num == 0) { in rv1108_calc_schmitt_reg_and_bit()
1397 *regmap = info->regmap_pmu; in rv1108_calc_schmitt_reg_and_bit()
1401 *regmap = info->regmap_base; in rv1108_calc_schmitt_reg_and_bit()
1404 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; in rv1108_calc_schmitt_reg_and_bit()
1420 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_schmitt_reg_and_bit()
1422 *regmap = info->regmap_base; in rk3308_calc_schmitt_reg_and_bit()
1425 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; in rk3308_calc_schmitt_reg_and_bit()
1440 struct rockchip_pinctrl *info = bank->drvdata; in rk2928_calc_pull_reg_and_bit()
1442 *regmap = info->regmap_base; in rk2928_calc_pull_reg_and_bit()
1444 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk2928_calc_pull_reg_and_bit()
1456 struct rockchip_pinctrl *info = bank->drvdata; in rk3128_calc_pull_reg_and_bit()
1458 *regmap = info->regmap_base; in rk3128_calc_pull_reg_and_bit()
1460 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk3128_calc_pull_reg_and_bit()
1476 struct rockchip_pinctrl *info = bank->drvdata; in rk3188_calc_pull_reg_and_bit()
1479 if (bank->bank_num == 0 && pin_num < 12) { in rk3188_calc_pull_reg_and_bit()
1480 *regmap = info->regmap_pmu ? info->regmap_pmu in rk3188_calc_pull_reg_and_bit()
1481 : bank->regmap_pull; in rk3188_calc_pull_reg_and_bit()
1482 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; in rk3188_calc_pull_reg_and_bit()
1487 *regmap = info->regmap_pull ? info->regmap_pull in rk3188_calc_pull_reg_and_bit()
1488 : info->regmap_base; in rk3188_calc_pull_reg_and_bit()
1489 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; in rk3188_calc_pull_reg_and_bit()
1492 *reg -= 4; in rk3188_calc_pull_reg_and_bit()
1493 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3188_calc_pull_reg_and_bit()
1501 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); in rk3188_calc_pull_reg_and_bit()
1511 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_pull_reg_and_bit()
1514 if (bank->bank_num == 0) { in rk3288_calc_pull_reg_and_bit()
1515 *regmap = info->regmap_pmu; in rk3288_calc_pull_reg_and_bit()
1522 *regmap = info->regmap_base; in rk3288_calc_pull_reg_and_bit()
1526 *reg -= 0x10; in rk3288_calc_pull_reg_and_bit()
1527 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3288_calc_pull_reg_and_bit()
1545 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_drv_reg_and_bit()
1548 if (bank->bank_num == 0) { in rk3288_calc_drv_reg_and_bit()
1549 *regmap = info->regmap_pmu; in rk3288_calc_drv_reg_and_bit()
1556 *regmap = info->regmap_base; in rk3288_calc_drv_reg_and_bit()
1560 *reg -= 0x10; in rk3288_calc_drv_reg_and_bit()
1561 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3288_calc_drv_reg_and_bit()
1575 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_pull_reg_and_bit()
1577 *regmap = info->regmap_base; in rk3228_calc_pull_reg_and_bit()
1579 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3228_calc_pull_reg_and_bit()
1592 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_drv_reg_and_bit()
1594 *regmap = info->regmap_base; in rk3228_calc_drv_reg_and_bit()
1596 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3228_calc_drv_reg_and_bit()
1609 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_pull_reg_and_bit()
1611 *regmap = info->regmap_base; in rk3308_calc_pull_reg_and_bit()
1613 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3308_calc_pull_reg_and_bit()
1626 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_drv_reg_and_bit()
1628 *regmap = info->regmap_base; in rk3308_calc_drv_reg_and_bit()
1630 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3308_calc_drv_reg_and_bit()
1644 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_pull_reg_and_bit()
1647 if (bank->bank_num == 0) { in rk3368_calc_pull_reg_and_bit()
1648 *regmap = info->regmap_pmu; in rk3368_calc_pull_reg_and_bit()
1655 *regmap = info->regmap_base; in rk3368_calc_pull_reg_and_bit()
1659 *reg -= 0x10; in rk3368_calc_pull_reg_and_bit()
1660 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3368_calc_pull_reg_and_bit()
1675 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_drv_reg_and_bit()
1678 if (bank->bank_num == 0) { in rk3368_calc_drv_reg_and_bit()
1679 *regmap = info->regmap_pmu; in rk3368_calc_drv_reg_and_bit()
1686 *regmap = info->regmap_base; in rk3368_calc_drv_reg_and_bit()
1690 *reg -= 0x10; in rk3368_calc_drv_reg_and_bit()
1691 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3368_calc_drv_reg_and_bit()
1707 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_pull_reg_and_bit()
1710 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { in rk3399_calc_pull_reg_and_bit()
1711 *regmap = info->regmap_pmu; in rk3399_calc_pull_reg_and_bit()
1714 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
1720 *regmap = info->regmap_base; in rk3399_calc_pull_reg_and_bit()
1724 *reg -= 0x20; in rk3399_calc_pull_reg_and_bit()
1725 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
1737 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_drv_reg_and_bit()
1741 if ((bank->bank_num == 0) || (bank->bank_num == 1)) in rk3399_calc_drv_reg_and_bit()
1742 *regmap = info->regmap_pmu; in rk3399_calc_drv_reg_and_bit()
1744 *regmap = info->regmap_base; in rk3399_calc_drv_reg_and_bit()
1746 *reg = bank->drv[drv_num].offset; in rk3399_calc_drv_reg_and_bit()
1747 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rk3399_calc_drv_reg_and_bit()
1748 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) in rk3399_calc_drv_reg_and_bit()
1764 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_pull_reg_and_bit()
1766 if (bank->bank_num == 0) { in rk3568_calc_pull_reg_and_bit()
1767 *regmap = info->regmap_pmu; in rk3568_calc_pull_reg_and_bit()
1769 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; in rk3568_calc_pull_reg_and_bit()
1775 *regmap = info->regmap_base; in rk3568_calc_pull_reg_and_bit()
1777 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; in rk3568_calc_pull_reg_and_bit()
1795 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_drv_reg_and_bit()
1798 if (bank->bank_num == 0) { in rk3568_calc_drv_reg_and_bit()
1799 *regmap = info->regmap_pmu; in rk3568_calc_drv_reg_and_bit()
1806 *regmap = info->regmap_base; in rk3568_calc_drv_reg_and_bit()
1808 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; in rk3568_calc_drv_reg_and_bit()
1817 { 2, 4, 8, 12, -1, -1, -1, -1 },
1818 { 3, 6, 9, 12, -1, -1, -1, -1 },
1819 { 5, 10, 15, 20, -1, -1, -1, -1 },
1827 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_drive_perpin()
1828 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_drive_perpin()
1833 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_get_drive_perpin()
1835 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_drive_perpin()
1847 * drive-strength offset is special, as it is in rockchip_get_drive_perpin()
1871 bit -= 16; in rockchip_get_drive_perpin()
1874 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", in rockchip_get_drive_perpin()
1876 return -EINVAL; in rockchip_get_drive_perpin()
1886 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", in rockchip_get_drive_perpin()
1888 return -EINVAL; in rockchip_get_drive_perpin()
1896 data &= (1 << rmask_bits) - 1; in rockchip_get_drive_perpin()
1904 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_drive_perpin()
1905 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_drive_perpin()
1910 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_set_drive_perpin()
1912 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", in rockchip_set_drive_perpin()
1913 bank->bank_num, pin_num, strength); in rockchip_set_drive_perpin()
1915 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_drive_perpin()
1916 if (ctrl->type == RK3568) { in rockchip_set_drive_perpin()
1918 ret = (1 << (strength + 1)) - 1; in rockchip_set_drive_perpin()
1922 ret = -EINVAL; in rockchip_set_drive_perpin()
1934 dev_err(info->dev, "unsupported driver strength %d\n", in rockchip_set_drive_perpin()
1949 * drive-strength offset is special, as it is spread in rockchip_set_drive_perpin()
1971 bit -= 16; in rockchip_set_drive_perpin()
1974 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", in rockchip_set_drive_perpin()
1976 return -EINVAL; in rockchip_set_drive_perpin()
1985 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", in rockchip_set_drive_perpin()
1987 return -EINVAL; in rockchip_set_drive_perpin()
1992 data = ((1 << rmask_bits) - 1) << (bit + 16); in rockchip_set_drive_perpin()
2018 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_pull()
2019 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_pull()
2026 if (ctrl->type == RK3066B) in rockchip_get_pull()
2029 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_pull()
2035 switch (ctrl->type) { in rockchip_get_pull()
2049 pull_type = bank->pull_type[pin_num / 8]; in rockchip_get_pull()
2051 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; in rockchip_get_pull()
2053 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, in rockchip_get_pull()
2056 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { in rockchip_get_pull()
2063 dev_err(info->dev, "unsupported pinctrl type\n"); in rockchip_get_pull()
2064 return -EINVAL; in rockchip_get_pull()
2071 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_pull()
2072 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_pull()
2078 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", in rockchip_set_pull()
2079 bank->bank_num, pin_num, pull); in rockchip_set_pull()
2082 if (ctrl->type == RK3066B) in rockchip_set_pull()
2083 return pull ? -EINVAL : 0; in rockchip_set_pull()
2085 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_pull()
2087 switch (ctrl->type) { in rockchip_set_pull()
2103 pull_type = bank->pull_type[pin_num / 8]; in rockchip_set_pull()
2104 ret = -EINVAL; in rockchip_set_pull()
2113 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, in rockchip_set_pull()
2116 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { in rockchip_set_pull()
2122 dev_err(info->dev, "unsupported pull setting %d\n", in rockchip_set_pull()
2128 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); in rockchip_set_pull()
2135 dev_err(info->dev, "unsupported pinctrl type\n"); in rockchip_set_pull()
2136 return -EINVAL; in rockchip_set_pull()
2152 struct rockchip_pinctrl *info = bank->drvdata; in rk3328_calc_schmitt_reg_and_bit()
2154 *regmap = info->regmap_base; in rk3328_calc_schmitt_reg_and_bit()
2157 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; in rk3328_calc_schmitt_reg_and_bit()
2175 struct rockchip_pinctrl *info = bank->drvdata; in rk3568_calc_schmitt_reg_and_bit()
2177 if (bank->bank_num == 0) { in rk3568_calc_schmitt_reg_and_bit()
2178 *regmap = info->regmap_pmu; in rk3568_calc_schmitt_reg_and_bit()
2181 *regmap = info->regmap_base; in rk3568_calc_schmitt_reg_and_bit()
2183 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; in rk3568_calc_schmitt_reg_and_bit()
2195 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_schmitt()
2196 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_schmitt()
2202 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_schmitt()
2211 switch (ctrl->type) { in rockchip_get_schmitt()
2213 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); in rockchip_get_schmitt()
2224 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_schmitt()
2225 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_schmitt()
2231 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n", in rockchip_set_schmitt()
2232 bank->bank_num, pin_num, enable); in rockchip_set_schmitt()
2234 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_schmitt()
2239 switch (ctrl->type) { in rockchip_set_schmitt()
2241 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); in rockchip_set_schmitt()
2262 return info->nfunctions; in rockchip_pmx_get_funcs_count()
2270 return info->functions[selector].name; in rockchip_pmx_get_func_name()
2279 *groups = info->functions[selector].groups; in rockchip_pmx_get_groups()
2280 *num_groups = info->functions[selector].ngroups; in rockchip_pmx_get_groups()
2289 const unsigned int *pins = info->groups[group].pins; in rockchip_pmx_set()
2290 const struct rockchip_pin_config *data = info->groups[group].data; in rockchip_pmx_set()
2294 dev_dbg(info->dev, "enable function %s group %s\n", in rockchip_pmx_set()
2295 info->functions[selector].name, info->groups[group].name); in rockchip_pmx_set()
2301 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { in rockchip_pmx_set()
2303 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, in rockchip_pmx_set()
2311 for (cnt--; cnt >= 0; cnt--) in rockchip_pmx_set()
2312 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); in rockchip_pmx_set()
2326 ret = clk_enable(bank->clk); in rockchip_gpio_get_direction()
2328 dev_err(bank->drvdata->dev, in rockchip_gpio_get_direction()
2329 "failed to enable clock for bank %s\n", bank->name); in rockchip_gpio_get_direction()
2332 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in rockchip_gpio_get_direction()
2333 clk_disable(bank->clk); in rockchip_gpio_get_direction()
2360 clk_enable(bank->clk); in _rockchip_pmx_gpio_set_direction()
2361 raw_spin_lock_irqsave(&bank->slock, flags); in _rockchip_pmx_gpio_set_direction()
2363 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in _rockchip_pmx_gpio_set_direction()
2369 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); in _rockchip_pmx_gpio_set_direction()
2371 raw_spin_unlock_irqrestore(&bank->slock, flags); in _rockchip_pmx_gpio_set_direction()
2372 clk_disable(bank->clk); in _rockchip_pmx_gpio_set_direction()
2385 chip = range->gc; in rockchip_pmx_gpio_set_direction()
2386 pin = offset - chip->base; in rockchip_pmx_gpio_set_direction()
2387 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", in rockchip_pmx_gpio_set_direction()
2388 offset, range->name, pin, input ? "input" : "output"); in rockchip_pmx_gpio_set_direction()
2390 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, in rockchip_pmx_gpio_set_direction()
2409 switch (ctrl->type) { in rockchip_pinconf_pull_valid()
2450 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2459 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) in rockchip_pinconf_set()
2460 return -ENOTSUPP; in rockchip_pinconf_set()
2463 return -EINVAL; in rockchip_pinconf_set()
2465 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2471 rockchip_gpio_set(&bank->gpio_chip, in rockchip_pinconf_set()
2472 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2473 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, in rockchip_pinconf_set()
2474 pin - bank->pin_base, false); in rockchip_pinconf_set()
2479 /* rk3288 is the first with per-pin drive-strength */ in rockchip_pinconf_set()
2480 if (!info->ctrl->drv_calc_reg) in rockchip_pinconf_set()
2481 return -ENOTSUPP; in rockchip_pinconf_set()
2484 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2489 if (!info->ctrl->schmitt_calc_reg) in rockchip_pinconf_set()
2490 return -ENOTSUPP; in rockchip_pinconf_set()
2493 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2498 return -ENOTSUPP; in rockchip_pinconf_set()
2518 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
2519 return -EINVAL; in rockchip_pinconf_get()
2527 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) in rockchip_pinconf_get()
2528 return -ENOTSUPP; in rockchip_pinconf_get()
2530 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
2531 return -EINVAL; in rockchip_pinconf_get()
2536 rc = rockchip_get_mux(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2538 return -EINVAL; in rockchip_pinconf_get()
2540 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); in rockchip_pinconf_get()
2547 /* rk3288 is the first with per-pin drive-strength */ in rockchip_pinconf_get()
2548 if (!info->ctrl->drv_calc_reg) in rockchip_pinconf_get()
2549 return -ENOTSUPP; in rockchip_pinconf_get()
2551 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2558 if (!info->ctrl->schmitt_calc_reg) in rockchip_pinconf_get()
2559 return -ENOTSUPP; in rockchip_pinconf_get()
2561 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2568 return -ENOTSUPP; in rockchip_pinconf_get()
2584 { .compatible = "rockchip,gpio-bank" },
2585 { .compatible = "rockchip,rk3188-gpio-bank0" },
2598 info->nfunctions++; in rockchip_pinctrl_child_count()
2599 info->ngroups += of_get_child_count(child); in rockchip_pinctrl_child_count()
2615 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); in rockchip_pinctrl_parse_groups()
2618 grp->name = np->name; in rockchip_pinctrl_parse_groups()
2628 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); in rockchip_pinctrl_parse_groups()
2629 return -EINVAL; in rockchip_pinctrl_parse_groups()
2632 grp->npins = size / 4; in rockchip_pinctrl_parse_groups()
2634 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), in rockchip_pinctrl_parse_groups()
2636 grp->data = devm_kcalloc(info->dev, in rockchip_pinctrl_parse_groups()
2637 grp->npins, in rockchip_pinctrl_parse_groups()
2640 if (!grp->pins || !grp->data) in rockchip_pinctrl_parse_groups()
2641 return -ENOMEM; in rockchip_pinctrl_parse_groups()
2652 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
2653 grp->data[j].func = be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
2657 return -EINVAL; in rockchip_pinctrl_parse_groups()
2661 &grp->data[j].configs, &grp->data[j].nconfigs); in rockchip_pinctrl_parse_groups()
2681 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); in rockchip_pinctrl_parse_functions()
2683 func = &info->functions[index]; in rockchip_pinctrl_parse_functions()
2686 func->name = np->name; in rockchip_pinctrl_parse_functions()
2687 func->ngroups = of_get_child_count(np); in rockchip_pinctrl_parse_functions()
2688 if (func->ngroups <= 0) in rockchip_pinctrl_parse_functions()
2691 func->groups = devm_kcalloc(info->dev, in rockchip_pinctrl_parse_functions()
2692 func->ngroups, sizeof(char *), GFP_KERNEL); in rockchip_pinctrl_parse_functions()
2693 if (!func->groups) in rockchip_pinctrl_parse_functions()
2694 return -ENOMEM; in rockchip_pinctrl_parse_functions()
2697 func->groups[i] = child->name; in rockchip_pinctrl_parse_functions()
2698 grp = &info->groups[grp_index++]; in rockchip_pinctrl_parse_functions()
2712 struct device *dev = &pdev->dev; in rockchip_pinctrl_parse_dt()
2713 struct device_node *np = dev->of_node; in rockchip_pinctrl_parse_dt()
2720 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); in rockchip_pinctrl_parse_dt()
2721 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); in rockchip_pinctrl_parse_dt()
2723 info->functions = devm_kcalloc(dev, in rockchip_pinctrl_parse_dt()
2724 info->nfunctions, in rockchip_pinctrl_parse_dt()
2727 if (!info->functions) in rockchip_pinctrl_parse_dt()
2728 return -ENOMEM; in rockchip_pinctrl_parse_dt()
2730 info->groups = devm_kcalloc(dev, in rockchip_pinctrl_parse_dt()
2731 info->ngroups, in rockchip_pinctrl_parse_dt()
2734 if (!info->groups) in rockchip_pinctrl_parse_dt()
2735 return -ENOMEM; in rockchip_pinctrl_parse_dt()
2745 dev_err(&pdev->dev, "failed to parse function\n"); in rockchip_pinctrl_parse_dt()
2757 struct pinctrl_desc *ctrldesc = &info->pctl; in rockchip_pinctrl_register()
2763 ctrldesc->name = "rockchip-pinctrl"; in rockchip_pinctrl_register()
2764 ctrldesc->owner = THIS_MODULE; in rockchip_pinctrl_register()
2765 ctrldesc->pctlops = &rockchip_pctrl_ops; in rockchip_pinctrl_register()
2766 ctrldesc->pmxops = &rockchip_pmx_ops; in rockchip_pinctrl_register()
2767 ctrldesc->confops = &rockchip_pinconf_ops; in rockchip_pinctrl_register()
2769 pindesc = devm_kcalloc(&pdev->dev, in rockchip_pinctrl_register()
2770 info->ctrl->nr_pins, sizeof(*pindesc), in rockchip_pinctrl_register()
2773 return -ENOMEM; in rockchip_pinctrl_register()
2775 ctrldesc->pins = pindesc; in rockchip_pinctrl_register()
2776 ctrldesc->npins = info->ctrl->nr_pins; in rockchip_pinctrl_register()
2779 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { in rockchip_pinctrl_register()
2780 pin_bank = &info->ctrl->pin_banks[bank]; in rockchip_pinctrl_register()
2781 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { in rockchip_pinctrl_register()
2782 pdesc->number = k; in rockchip_pinctrl_register()
2783 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", in rockchip_pinctrl_register()
2784 pin_bank->name, pin); in rockchip_pinctrl_register()
2793 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); in rockchip_pinctrl_register()
2794 if (IS_ERR(info->pctl_dev)) { in rockchip_pinctrl_register()
2795 dev_err(&pdev->dev, "could not register pinctrl driver\n"); in rockchip_pinctrl_register()
2796 return PTR_ERR(info->pctl_dev); in rockchip_pinctrl_register()
2799 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { in rockchip_pinctrl_register()
2800 pin_bank = &info->ctrl->pin_banks[bank]; in rockchip_pinctrl_register()
2801 pin_bank->grange.name = pin_bank->name; in rockchip_pinctrl_register()
2802 pin_bank->grange.id = bank; in rockchip_pinctrl_register()
2803 pin_bank->grange.pin_base = pin_bank->pin_base; in rockchip_pinctrl_register()
2804 pin_bank->grange.base = pin_bank->gpio_chip.base; in rockchip_pinctrl_register()
2805 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; in rockchip_pinctrl_register()
2806 pin_bank->grange.gc = &pin_bank->gpio_chip; in rockchip_pinctrl_register()
2807 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); in rockchip_pinctrl_register()
2820 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; in rockchip_gpio_set()
2824 clk_enable(bank->clk); in rockchip_gpio_set()
2825 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_gpio_set()
2833 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_gpio_set()
2834 clk_disable(bank->clk); in rockchip_gpio_set()
2846 clk_enable(bank->clk); in rockchip_gpio_get()
2847 data = readl(bank->reg_base + GPIO_EXT_PORT); in rockchip_gpio_get()
2848 clk_disable(bank->clk); in rockchip_gpio_get()
2861 return pinctrl_gpio_direction_input(gc->base + offset); in rockchip_gpio_direction_input()
2873 return pinctrl_gpio_direction_output(gc->base + offset); in rockchip_gpio_direction_output()
2880 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; in rockchip_gpio_set_debounce()
2884 clk_enable(bank->clk); in rockchip_gpio_set_debounce()
2885 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_gpio_set_debounce()
2894 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_gpio_set_debounce()
2895 clk_disable(bank->clk); in rockchip_gpio_set_debounce()
2919 * still return -ENOTSUPP as before, to make sure the caller in rockchip_gpio_set_config()
2922 return -ENOTSUPP; in rockchip_gpio_set_config()
2924 return -ENOTSUPP; in rockchip_gpio_set_config()
2937 if (!bank->domain) in rockchip_gpio_to_irq()
2938 return -ENXIO; in rockchip_gpio_to_irq()
2940 clk_enable(bank->clk); in rockchip_gpio_to_irq()
2941 virq = irq_create_mapping(bank->domain, offset); in rockchip_gpio_to_irq()
2942 clk_disable(bank->clk); in rockchip_gpio_to_irq()
2944 return (virq) ? : -ENXIO; in rockchip_gpio_to_irq()
2970 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); in rockchip_irq_demux()
2974 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); in rockchip_irq_demux()
2981 virq = irq_find_mapping(bank->domain, irq); in rockchip_irq_demux()
2984 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); in rockchip_irq_demux()
2988 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); in rockchip_irq_demux()
2994 if (bank->toggle_edge_mode & BIT(irq)) { in rockchip_irq_demux()
2998 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); in rockchip_irq_demux()
3000 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_demux()
3002 polarity = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
3009 bank->reg_base + GPIO_INT_POLARITY); in rockchip_irq_demux()
3011 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_demux()
3014 data = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
3028 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_set_type()
3029 u32 mask = BIT(d->hwirq); in rockchip_irq_set_type()
3037 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); in rockchip_irq_set_type()
3041 clk_enable(bank->clk); in rockchip_irq_set_type()
3042 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_set_type()
3044 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in rockchip_irq_set_type()
3046 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); in rockchip_irq_set_type()
3048 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
3055 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_set_type()
3058 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); in rockchip_irq_set_type()
3059 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); in rockchip_irq_set_type()
3063 bank->toggle_edge_mode |= mask; in rockchip_irq_set_type()
3070 data = readl(bank->reg_base + GPIO_EXT_PORT); in rockchip_irq_set_type()
3077 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3082 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3087 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3092 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3098 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
3099 clk_disable(bank->clk); in rockchip_irq_set_type()
3100 return -EINVAL; in rockchip_irq_set_type()
3103 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); in rockchip_irq_set_type()
3104 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); in rockchip_irq_set_type()
3107 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
3108 clk_disable(bank->clk); in rockchip_irq_set_type()
3116 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_suspend()
3118 clk_enable(bank->clk); in rockchip_irq_suspend()
3119 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); in rockchip_irq_suspend()
3120 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); in rockchip_irq_suspend()
3121 clk_disable(bank->clk); in rockchip_irq_suspend()
3127 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_resume()
3129 clk_enable(bank->clk); in rockchip_irq_resume()
3130 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); in rockchip_irq_resume()
3131 clk_disable(bank->clk); in rockchip_irq_resume()
3137 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_enable()
3139 clk_enable(bank->clk); in rockchip_irq_enable()
3146 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_disable()
3149 clk_disable(bank->clk); in rockchip_irq_disable()
3155 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_interrupts_register()
3156 struct rockchip_pin_bank *bank = ctrl->pin_banks; in rockchip_interrupts_register()
3162 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_interrupts_register()
3163 if (!bank->valid) { in rockchip_interrupts_register()
3164 dev_warn(&pdev->dev, "bank %s is not valid\n", in rockchip_interrupts_register()
3165 bank->name); in rockchip_interrupts_register()
3169 ret = clk_enable(bank->clk); in rockchip_interrupts_register()
3171 dev_err(&pdev->dev, "failed to enable clock for bank %s\n", in rockchip_interrupts_register()
3172 bank->name); in rockchip_interrupts_register()
3176 bank->domain = irq_domain_add_linear(bank->of_node, 32, in rockchip_interrupts_register()
3178 if (!bank->domain) { in rockchip_interrupts_register()
3179 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", in rockchip_interrupts_register()
3180 bank->name); in rockchip_interrupts_register()
3181 clk_disable(bank->clk); in rockchip_interrupts_register()
3185 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, in rockchip_interrupts_register()
3189 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", in rockchip_interrupts_register()
3190 bank->name); in rockchip_interrupts_register()
3191 irq_domain_remove(bank->domain); in rockchip_interrupts_register()
3192 clk_disable(bank->clk); in rockchip_interrupts_register()
3196 gc = irq_get_domain_generic_chip(bank->domain, 0); in rockchip_interrupts_register()
3197 gc->reg_base = bank->reg_base; in rockchip_interrupts_register()
3198 gc->private = bank; in rockchip_interrupts_register()
3199 gc->chip_types[0].regs.mask = GPIO_INTMASK; in rockchip_interrupts_register()
3200 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; in rockchip_interrupts_register()
3201 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; in rockchip_interrupts_register()
3202 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; in rockchip_interrupts_register()
3203 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; in rockchip_interrupts_register()
3204 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; in rockchip_interrupts_register()
3205 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; in rockchip_interrupts_register()
3206 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; in rockchip_interrupts_register()
3207 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; in rockchip_interrupts_register()
3208 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; in rockchip_interrupts_register()
3209 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; in rockchip_interrupts_register()
3210 gc->wake_enabled = IRQ_MSK(bank->nr_pins); in rockchip_interrupts_register()
3217 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); in rockchip_interrupts_register()
3218 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); in rockchip_interrupts_register()
3219 gc->mask_cache = 0xffffffff; in rockchip_interrupts_register()
3221 irq_set_chained_handler_and_data(bank->irq, in rockchip_interrupts_register()
3223 clk_disable(bank->clk); in rockchip_interrupts_register()
3232 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_gpiolib_register()
3233 struct rockchip_pin_bank *bank = ctrl->pin_banks; in rockchip_gpiolib_register()
3238 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_gpiolib_register()
3239 if (!bank->valid) { in rockchip_gpiolib_register()
3240 dev_warn(&pdev->dev, "bank %s is not valid\n", in rockchip_gpiolib_register()
3241 bank->name); in rockchip_gpiolib_register()
3245 bank->gpio_chip = rockchip_gpiolib_chip; in rockchip_gpiolib_register()
3247 gc = &bank->gpio_chip; in rockchip_gpiolib_register()
3248 gc->base = bank->pin_base; in rockchip_gpiolib_register()
3249 gc->ngpio = bank->nr_pins; in rockchip_gpiolib_register()
3250 gc->parent = &pdev->dev; in rockchip_gpiolib_register()
3251 gc->of_node = bank->of_node; in rockchip_gpiolib_register()
3252 gc->label = bank->name; in rockchip_gpiolib_register()
3256 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", in rockchip_gpiolib_register()
3257 gc->label, ret); in rockchip_gpiolib_register()
3267 for (--i, --bank; i >= 0; --i, --bank) { in rockchip_gpiolib_register()
3268 if (!bank->valid) in rockchip_gpiolib_register()
3270 gpiochip_remove(&bank->gpio_chip); in rockchip_gpiolib_register()
3278 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_gpiolib_unregister()
3279 struct rockchip_pin_bank *bank = ctrl->pin_banks; in rockchip_gpiolib_unregister()
3282 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_gpiolib_unregister()
3283 if (!bank->valid) in rockchip_gpiolib_unregister()
3285 gpiochip_remove(&bank->gpio_chip); in rockchip_gpiolib_unregister()
3297 if (of_address_to_resource(bank->of_node, 0, &res)) { in rockchip_get_bank_data()
3298 dev_err(info->dev, "cannot find IO resource for bank\n"); in rockchip_get_bank_data()
3299 return -ENOENT; in rockchip_get_bank_data()
3302 bank->reg_base = devm_ioremap_resource(info->dev, &res); in rockchip_get_bank_data()
3303 if (IS_ERR(bank->reg_base)) in rockchip_get_bank_data()
3304 return PTR_ERR(bank->reg_base); in rockchip_get_bank_data()
3307 * special case, where parts of the pull setting-registers are in rockchip_get_bank_data()
3310 if (of_device_is_compatible(bank->of_node, in rockchip_get_bank_data()
3311 "rockchip,rk3188-gpio-bank0")) { in rockchip_get_bank_data()
3314 node = of_parse_phandle(bank->of_node->parent, in rockchip_get_bank_data()
3317 if (of_address_to_resource(bank->of_node, 1, &res)) { in rockchip_get_bank_data()
3318 dev_err(info->dev, "cannot find IO resource for bank\n"); in rockchip_get_bank_data()
3319 return -ENOENT; in rockchip_get_bank_data()
3322 base = devm_ioremap_resource(info->dev, &res); in rockchip_get_bank_data()
3326 resource_size(&res) - 4; in rockchip_get_bank_data()
3328 "rockchip,rk3188-gpio-bank0-pull"; in rockchip_get_bank_data()
3329 bank->regmap_pull = devm_regmap_init_mmio(info->dev, in rockchip_get_bank_data()
3336 bank->irq = irq_of_parse_and_map(bank->of_node, 0); in rockchip_get_bank_data()
3338 bank->clk = of_clk_get(bank->of_node, 0); in rockchip_get_bank_data()
3339 if (IS_ERR(bank->clk)) in rockchip_get_bank_data()
3340 return PTR_ERR(bank->clk); in rockchip_get_bank_data()
3342 return clk_prepare(bank->clk); in rockchip_get_bank_data()
3353 struct device_node *node = pdev->dev.of_node; in rockchip_pinctrl_get_soc_data()
3360 ctrl = (struct rockchip_pin_ctrl *)match->data; in rockchip_pinctrl_get_soc_data()
3363 if (!of_find_property(np, "gpio-controller", NULL)) in rockchip_pinctrl_get_soc_data()
3366 bank = ctrl->pin_banks; in rockchip_pinctrl_get_soc_data()
3367 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_pinctrl_get_soc_data()
3368 if (!strcmp(bank->name, np->name)) { in rockchip_pinctrl_get_soc_data()
3369 bank->of_node = np; in rockchip_pinctrl_get_soc_data()
3372 bank->valid = true; in rockchip_pinctrl_get_soc_data()
3379 grf_offs = ctrl->grf_mux_offset; in rockchip_pinctrl_get_soc_data()
3380 pmu_offs = ctrl->pmu_mux_offset; in rockchip_pinctrl_get_soc_data()
3381 drv_pmu_offs = ctrl->pmu_drv_offset; in rockchip_pinctrl_get_soc_data()
3382 drv_grf_offs = ctrl->grf_drv_offset; in rockchip_pinctrl_get_soc_data()
3383 bank = ctrl->pin_banks; in rockchip_pinctrl_get_soc_data()
3384 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_pinctrl_get_soc_data()
3387 raw_spin_lock_init(&bank->slock); in rockchip_pinctrl_get_soc_data()
3388 bank->drvdata = d; in rockchip_pinctrl_get_soc_data()
3389 bank->pin_base = ctrl->nr_pins; in rockchip_pinctrl_get_soc_data()
3390 ctrl->nr_pins += bank->nr_pins; in rockchip_pinctrl_get_soc_data()
3394 struct rockchip_iomux *iom = &bank->iomux[j]; in rockchip_pinctrl_get_soc_data()
3395 struct rockchip_drv *drv = &bank->drv[j]; in rockchip_pinctrl_get_soc_data()
3398 if (bank_pins >= bank->nr_pins) in rockchip_pinctrl_get_soc_data()
3402 if (iom->offset >= 0) { in rockchip_pinctrl_get_soc_data()
3403 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3404 pmu_offs = iom->offset; in rockchip_pinctrl_get_soc_data()
3406 grf_offs = iom->offset; in rockchip_pinctrl_get_soc_data()
3408 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? in rockchip_pinctrl_get_soc_data()
3413 if (drv->offset >= 0) { in rockchip_pinctrl_get_soc_data()
3414 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3415 drv_pmu_offs = drv->offset; in rockchip_pinctrl_get_soc_data()
3417 drv_grf_offs = drv->offset; in rockchip_pinctrl_get_soc_data()
3419 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? in rockchip_pinctrl_get_soc_data()
3423 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", in rockchip_pinctrl_get_soc_data()
3424 i, j, iom->offset, drv->offset); in rockchip_pinctrl_get_soc_data()
3430 inc = (iom->type & (IOMUX_WIDTH_4BIT | in rockchip_pinctrl_get_soc_data()
3433 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3440 * 3bit drive-strenth'es are spread over two registers. in rockchip_pinctrl_get_soc_data()
3442 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rockchip_pinctrl_get_soc_data()
3443 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) in rockchip_pinctrl_get_soc_data()
3448 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3456 /* calculate the per-bank recalced_mask */ in rockchip_pinctrl_get_soc_data()
3457 for (j = 0; j < ctrl->niomux_recalced; j++) { in rockchip_pinctrl_get_soc_data()
3460 if (ctrl->iomux_recalced[j].num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
3461 pin = ctrl->iomux_recalced[j].pin; in rockchip_pinctrl_get_soc_data()
3462 bank->recalced_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
3466 /* calculate the per-bank route_mask */ in rockchip_pinctrl_get_soc_data()
3467 for (j = 0; j < ctrl->niomux_routes; j++) { in rockchip_pinctrl_get_soc_data()
3470 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
3471 pin = ctrl->iomux_routes[j].pin; in rockchip_pinctrl_get_soc_data()
3472 bank->route_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
3488 int ret = pinctrl_force_sleep(info->pctl_dev); in rockchip_pinctrl_suspend()
3497 if (info->ctrl->type == RK3288) { in rockchip_pinctrl_suspend()
3498 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, in rockchip_pinctrl_suspend()
3501 pinctrl_force_default(info->pctl_dev); in rockchip_pinctrl_suspend()
3514 if (info->ctrl->type == RK3288) { in rockchip_pinctrl_resume()
3515 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, in rockchip_pinctrl_resume()
3522 return pinctrl_force_default(info->pctl_dev); in rockchip_pinctrl_resume()
3531 struct device *dev = &pdev->dev; in rockchip_pinctrl_probe()
3533 struct device_node *np = pdev->dev.of_node, *node; in rockchip_pinctrl_probe()
3538 if (!dev->of_node) { in rockchip_pinctrl_probe()
3540 return -ENODEV; in rockchip_pinctrl_probe()
3545 return -ENOMEM; in rockchip_pinctrl_probe()
3547 info->dev = dev; in rockchip_pinctrl_probe()
3552 return -EINVAL; in rockchip_pinctrl_probe()
3554 info->ctrl = ctrl; in rockchip_pinctrl_probe()
3558 info->regmap_base = syscon_node_to_regmap(node); in rockchip_pinctrl_probe()
3560 if (IS_ERR(info->regmap_base)) in rockchip_pinctrl_probe()
3561 return PTR_ERR(info->regmap_base); in rockchip_pinctrl_probe()
3564 base = devm_ioremap_resource(&pdev->dev, res); in rockchip_pinctrl_probe()
3568 rockchip_regmap_config.max_register = resource_size(res) - 4; in rockchip_pinctrl_probe()
3570 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, in rockchip_pinctrl_probe()
3573 /* to check for the old dt-bindings */ in rockchip_pinctrl_probe()
3574 info->reg_size = resource_size(res); in rockchip_pinctrl_probe()
3577 if (ctrl->type == RK3188 && info->reg_size < 0x200) { in rockchip_pinctrl_probe()
3579 base = devm_ioremap_resource(&pdev->dev, res); in rockchip_pinctrl_probe()
3584 resource_size(res) - 4; in rockchip_pinctrl_probe()
3585 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; in rockchip_pinctrl_probe()
3586 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, in rockchip_pinctrl_probe()
3595 info->regmap_pmu = syscon_node_to_regmap(node); in rockchip_pinctrl_probe()
3597 if (IS_ERR(info->regmap_pmu)) in rockchip_pinctrl_probe()
3598 return PTR_ERR(info->regmap_pmu); in rockchip_pinctrl_probe()
3642 .label = "PX30-GPIO",
3666 .label = "RV1108-GPIO",
3687 .label = "RK2928-GPIO",
3702 .label = "RK3036-GPIO",
3720 .label = "RK3066a-GPIO",
3736 .label = "RK3066b-GPIO",
3751 .label = "RK3128-GPIO",
3771 .label = "RK3188-GPIO",
3789 .label = "RK3228-GPIO",
3833 .label = "RK3288-GPIO",
3869 .label = "RK3308-GPIO",
3898 .label = "RK3328-GPIO",
3924 .label = "RK3368-GPIO",
3944 -1,
3945 -1,
3988 .label = "RK3399-GPIO",
4026 .label = "RK3568-GPIO",
4040 { .compatible = "rockchip,px30-pinctrl",
4042 { .compatible = "rockchip,rv1108-pinctrl",
4044 { .compatible = "rockchip,rk2928-pinctrl",
4046 { .compatible = "rockchip,rk3036-pinctrl",
4048 { .compatible = "rockchip,rk3066a-pinctrl",
4050 { .compatible = "rockchip,rk3066b-pinctrl",
4052 { .compatible = "rockchip,rk3128-pinctrl",
4054 { .compatible = "rockchip,rk3188-pinctrl",
4056 { .compatible = "rockchip,rk3228-pinctrl",
4058 { .compatible = "rockchip,rk3288-pinctrl",
4060 { .compatible = "rockchip,rk3308-pinctrl",
4062 { .compatible = "rockchip,rk3328-pinctrl",
4064 { .compatible = "rockchip,rk3368-pinctrl",
4066 { .compatible = "rockchip,rk3399-pinctrl",
4068 { .compatible = "rockchip,rk3568-pinctrl",
4076 .name = "rockchip-pinctrl",