Lines Matching +full:0 +full:x407
89 BT_NONE = 0,
133 135100, 135100, 85500, 85500, 0
138 .sr07 = 0xF0,
139 .sr07_1bpp = 0xF0,
140 .sr07_1bpp_mux = 0xF6,
141 .sr07_8bpp = 0xF1,
142 .sr07_8bpp_mux = 0xF7,
143 .sr1f = 0x1E
154 .sr07 = 0x80,
155 .sr07_1bpp = 0x80,
156 .sr07_8bpp = 0x81,
157 .sr1f = 0x22
168 .sr07 = 0x20,
169 .sr07_1bpp = 0x20,
170 .sr07_8bpp = 0x21,
171 .sr1f = 0x22
182 .sr07 = 0x80,
183 .sr07_1bpp = 0x80,
184 .sr07_8bpp = 0x81,
185 .sr1f = 0x22
190 135100, 135100, 85500, 85500, 0
195 .sr07 = 0xA0,
196 .sr07_1bpp = 0xA0,
197 .sr07_1bpp_mux = 0xA6,
198 .sr07_8bpp = 0xA1,
199 .sr07_8bpp_mux = 0xA7,
200 .sr1f = 0
206 85500, 85500, 50000, 28500, 0
211 .sr07 = 0xA0,
212 .sr07_1bpp = 0xA0,
213 .sr07_1bpp_mux = 0xA6,
214 .sr07_8bpp = 0xA1,
215 .sr07_8bpp_mux = 0xA7,
216 .sr1f = 0x1C
226 .sr07 = 0x10,
227 .sr07_1bpp = 0x11,
228 .sr07_8bpp = 0x11,
229 .sr1f = 0x1C
255 { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
269 { 0, }
308 .regoffset = 0x00600000,
310 .ramoffset = 0x01000000, /* 0x02000000 for 64 MiB boards */
315 .regoffset = 0x10000,
341 { 0 }
390 #if 0
430 if (opencount++ == 0) in cirrusfb_open()
432 return 0; in cirrusfb_open()
438 if (--opencount == 0) in cirrusfb_release()
439 switch_monitor(info->par, 0); in cirrusfb_release()
440 return 0; in cirrusfb_release()
451 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f; in cirrusfb_check_mclk()
469 return 0; in cirrusfb_check_mclk()
484 cinfo->multiplexing = 0; in cirrusfb_check_pixclock()
520 cinfo->doubleVCLK = 0; in cirrusfb_check_pixclock()
526 return 0; in cirrusfb_check_pixclock()
539 var->red.offset = 0; in cirrusfb_check_var()
546 var->red.offset = 0; in cirrusfb_check_var()
555 var->blue.offset = 0; in cirrusfb_check_var()
564 var->blue.offset = 0; in cirrusfb_check_var()
608 var->transp.msb_right = 0; in cirrusfb_check_var()
628 return 0; in cirrusfb_check_var()
637 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40; in cirrusfb_set_mclk_as_source()
642 old1f |= 0x40; in cirrusfb_set_mclk_as_source()
643 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1; in cirrusfb_set_mclk_as_source()
669 unsigned int control = 0, format = 0, threshold = 0; in cirrusfb_set_par_foo()
747 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */ in cirrusfb_set_par_foo()
773 dev_dbg(info->device, "CRT6: %d\n", vtotal & 0xff); in cirrusfb_set_par_foo()
774 vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff); in cirrusfb_set_par_foo()
794 tmp = 0x40; /* LineCompare bit #8 */ in cirrusfb_set_par_foo()
796 tmp |= 0x20; in cirrusfb_set_par_foo()
798 tmp |= 0x80; in cirrusfb_set_par_foo()
802 dev_dbg(info->device, "CRT10: %d\n", vsyncstart & 0xff); in cirrusfb_set_par_foo()
803 vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff); in cirrusfb_set_par_foo()
808 dev_dbg(info->device, "CRT12: %d\n", vdispend & 0xff); in cirrusfb_set_par_foo()
809 vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff); in cirrusfb_set_par_foo()
811 dev_dbg(info->device, "CRT15: %d\n", (vdispend + 1) & 0xff); in cirrusfb_set_par_foo()
812 vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff); in cirrusfb_set_par_foo()
814 dev_dbg(info->device, "CRT16: %d\n", vtotal & 0xff); in cirrusfb_set_par_foo()
815 vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff); in cirrusfb_set_par_foo()
817 dev_dbg(info->device, "CRT18: 0xff\n"); in cirrusfb_set_par_foo()
818 vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff); in cirrusfb_set_par_foo()
820 tmp = 0; in cirrusfb_set_par_foo()
861 nom = 0; in cirrusfb_set_par_foo()
865 long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc); in cirrusfb_set_par_foo()
866 unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407); in cirrusfb_set_par_foo()
870 tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4); in cirrusfb_set_par_foo()
871 tile_control &= ~0x80; in cirrusfb_set_par_foo()
872 fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4); in cirrusfb_set_par_foo()
875 fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc); in cirrusfb_set_par_foo()
876 fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407); in cirrusfb_set_par_foo()
877 control = fb_readw(cinfo->laguna_mmio + 0x402); in cirrusfb_set_par_foo()
878 threshold = fb_readw(cinfo->laguna_mmio + 0xea); in cirrusfb_set_par_foo()
879 control &= ~0x6800; in cirrusfb_set_par_foo()
880 format = 0; in cirrusfb_set_par_foo()
881 threshold &= 0xffc0 & 0x3fbf; in cirrusfb_set_par_foo()
885 if (div != 0) in cirrusfb_set_par_foo()
891 tmp |= 0x80; in cirrusfb_set_par_foo()
905 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7); in cirrusfb_set_par_foo()
909 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3); in cirrusfb_set_par_foo()
916 vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */ in cirrusfb_set_par_foo()
920 tmp = 0x03 | 0xc; in cirrusfb_set_par_foo()
922 tmp |= 0x40; in cirrusfb_set_par_foo()
924 tmp |= 0x80; in cirrusfb_set_par_foo()
928 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0); in cirrusfb_set_par_foo()
941 vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */ in cirrusfb_set_par_foo()
960 vga_rseq(regbase, CL_SEQR7) & ~0x01); in cirrusfb_set_par_foo()
974 vga_wseq(regbase, CL_SEQRF, 0xb0); in cirrusfb_set_par_foo()
979 vga_wseq(regbase, CL_SEQRF, 0xd0); in cirrusfb_set_par_foo()
997 WGen(cinfo, VGA_PEL_MSK, 0x01); in cirrusfb_set_par_foo()
1000 WHDR(cinfo, 0x4a); in cirrusfb_set_par_foo()
1003 WHDR(cinfo, 0); in cirrusfb_set_par_foo()
1005 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06); in cirrusfb_set_par_foo()
1007 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01); in cirrusfb_set_par_foo()
1034 vga_rseq(regbase, CL_SEQR7) | 0x01); in cirrusfb_set_par_foo()
1035 threshold |= 0x10; in cirrusfb_set_par_foo()
1048 vga_wseq(regbase, CL_SEQRF, 0xb0); in cirrusfb_set_par_foo()
1054 vga_wseq(regbase, CL_SEQRF, 0xb8); in cirrusfb_set_par_foo()
1073 WHDR(cinfo, 0x4a); in cirrusfb_set_par_foo()
1076 WHDR(cinfo, 0); in cirrusfb_set_par_foo()
1090 vga_wseq(regbase, CL_SEQR7, 0x87); in cirrusfb_set_par_foo()
1092 vga_wseq(regbase, CL_SEQRF, 0xb0); in cirrusfb_set_par_foo()
1096 vga_wseq(regbase, CL_SEQR7, 0x27); in cirrusfb_set_par_foo()
1098 vga_wseq(regbase, CL_SEQRF, 0xb0); in cirrusfb_set_par_foo()
1106 cinfo->doubleVCLK ? 0xa3 : 0xa7); in cirrusfb_set_par_foo()
1110 vga_wseq(regbase, CL_SEQR7, 0x17); in cirrusfb_set_par_foo()
1117 vga_rseq(regbase, CL_SEQR7) & ~0x01); in cirrusfb_set_par_foo()
1118 control |= 0x2000; in cirrusfb_set_par_foo()
1119 format |= 0x1400; in cirrusfb_set_par_foo()
1120 threshold |= 0x10; in cirrusfb_set_par_foo()
1131 WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1); in cirrusfb_set_par_foo()
1134 WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */ in cirrusfb_set_par_foo()
1149 vga_wseq(regbase, CL_SEQR7, 0x85); in cirrusfb_set_par_foo()
1151 vga_wseq(regbase, CL_SEQRF, 0xb0); in cirrusfb_set_par_foo()
1155 vga_wseq(regbase, CL_SEQR7, 0x25); in cirrusfb_set_par_foo()
1157 vga_wseq(regbase, CL_SEQRF, 0xb0); in cirrusfb_set_par_foo()
1164 vga_wseq(regbase, CL_SEQR7, 0xa5); in cirrusfb_set_par_foo()
1168 vga_wseq(regbase, CL_SEQR7, 0x15); in cirrusfb_set_par_foo()
1175 vga_rseq(regbase, CL_SEQR7) & ~0x01); in cirrusfb_set_par_foo()
1176 control |= 0x4000; in cirrusfb_set_par_foo()
1177 format |= 0x2400; in cirrusfb_set_par_foo()
1178 threshold |= 0x20; in cirrusfb_set_par_foo()
1189 WHDR(cinfo, 0xc5); in cirrusfb_set_par_foo()
1204 vga_wcrt(regbase, VGA_CRTC_OFFSET, pitch & 0xff); in cirrusfb_set_par_foo()
1205 tmp = 0x22; in cirrusfb_set_par_foo()
1206 if (pitch & 0x100) in cirrusfb_set_par_foo()
1207 tmp |= 0x10; /* offset overflow bit */ in cirrusfb_set_par_foo()
1217 tmp = 0; in cirrusfb_set_par_foo()
1236 vga_wattr(regbase, CL_AR33, 0); in cirrusfb_set_par_foo()
1244 fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402); in cirrusfb_set_par_foo()
1245 fb_writew(format, cinfo->laguna_mmio + 0xc0); in cirrusfb_set_par_foo()
1246 fb_writew(threshold, cinfo->laguna_mmio + 0xea); in cirrusfb_set_par_foo()
1250 tmp = 0x01; in cirrusfb_set_par_foo()
1254 tmp |= 0x08; in cirrusfb_set_par_foo()
1264 return 0; in cirrusfb_set_par_foo()
1297 return 0; in cirrusfb_setcolreg()
1303 return 0; in cirrusfb_setcolreg()
1341 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff); in cirrusfb_pan_display()
1342 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff); in cirrusfb_pan_display()
1344 /* 0xf2 is %11110010, exclude tmp bits */ in cirrusfb_pan_display()
1345 tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2; in cirrusfb_pan_display()
1347 if (base & 0x10000) in cirrusfb_pan_display()
1348 tmp |= 0x01; in cirrusfb_pan_display()
1349 if (base & 0x20000) in cirrusfb_pan_display()
1350 tmp |= 0x04; in cirrusfb_pan_display()
1351 if (base & 0x40000) in cirrusfb_pan_display()
1352 tmp |= 0x08; in cirrusfb_pan_display()
1360 tmp = (tmp & ~0x18) | ((base >> 16) & 0x18); in cirrusfb_pan_display()
1362 tmp = (tmp & ~0x80) | ((base >> 12) & 0x80); in cirrusfb_pan_display()
1373 return 0; in cirrusfb_pan_display()
1379 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL in cirrusfb_blank()
1381 * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking in cirrusfb_blank()
1397 dev_dbg(info->device, "EXIT, returning 0\n"); in cirrusfb_blank()
1398 return 0; in cirrusfb_blank()
1405 val = 0; in cirrusfb_blank()
1408 val = 0x20; in cirrusfb_blank()
1410 val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf; in cirrusfb_blank()
1416 val = 0x00; in cirrusfb_blank()
1419 val = 0x04; in cirrusfb_blank()
1422 val = 0x02; in cirrusfb_blank()
1425 val = 0x06; in cirrusfb_blank()
1435 dev_dbg(info->device, "EXIT, returning 0\n"); in cirrusfb_blank()
1438 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0; in cirrusfb_blank()
1457 WSFR(cinfo, 0x01); in init_vgachip()
1459 WSFR(cinfo, 0x51); in init_vgachip()
1463 WSFR2(cinfo, 0xff); in init_vgachip()
1468 WSFR(cinfo, 0x1f); in init_vgachip()
1470 WSFR(cinfo, 0x4f); in init_vgachip()
1475 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00); in init_vgachip()
1478 vga_wgfx(cinfo->regbase, CL_GR31, 0x00); in init_vgachip()
1482 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00); in init_vgachip()
1486 vga_wgfx(cinfo->regbase, CL_GR33, 0x00); in init_vgachip()
1500 assert(info->screen_size > 0); in init_vgachip()
1507 WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */ in init_vgachip()
1508 WGen(cinfo, CL_POS102, 0x01); in init_vgachip()
1509 WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */ in init_vgachip()
1512 WGen(cinfo, CL_VSSM2, 0x01); in init_vgachip()
1515 vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03); in init_vgachip()
1518 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21); in init_vgachip()
1521 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */ in init_vgachip()
1523 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12); in init_vgachip()
1527 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98); in init_vgachip()
1535 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8); in init_vgachip()
1539 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f); in init_vgachip()
1540 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0); in init_vgachip()
1545 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff); in init_vgachip()
1547 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00); in init_vgachip()
1549 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a); in init_vgachip()
1555 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */ in init_vgachip()
1559 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00); in init_vgachip()
1561 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00); in init_vgachip()
1563 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00); in init_vgachip()
1565 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00); in init_vgachip()
1570 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00); in init_vgachip()
1572 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02); in init_vgachip()
1576 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00); in init_vgachip()
1578 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20); in init_vgachip()
1580 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00); in init_vgachip()
1581 /* text cursor location high: 0 */ in init_vgachip()
1582 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00); in init_vgachip()
1583 /* text cursor location low: 0 */ in init_vgachip()
1584 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00); in init_vgachip()
1587 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00); in init_vgachip()
1588 /* ### add 0x40 for text modes with > 30 MHz pixclock */ in init_vgachip()
1590 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02); in init_vgachip()
1593 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00); in init_vgachip()
1595 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00); in init_vgachip()
1597 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00); in init_vgachip()
1599 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00); in init_vgachip()
1601 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00); in init_vgachip()
1602 /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */ in init_vgachip()
1603 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00); in init_vgachip()
1605 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01); in init_vgachip()
1607 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f); in init_vgachip()
1609 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff); in init_vgachip()
1614 vga_wgfx(cinfo->regbase, CL_GRB, 0x20); in init_vgachip()
1619 vga_wgfx(cinfo->regbase, CL_GRB, 0x28); in init_vgachip()
1621 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */ in init_vgachip()
1622 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */ in init_vgachip()
1623 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */ in init_vgachip()
1625 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */ in init_vgachip()
1626 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */ in init_vgachip()
1629 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00); in init_vgachip()
1630 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01); in init_vgachip()
1631 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02); in init_vgachip()
1632 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03); in init_vgachip()
1633 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04); in init_vgachip()
1634 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05); in init_vgachip()
1635 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06); in init_vgachip()
1636 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07); in init_vgachip()
1637 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08); in init_vgachip()
1638 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09); in init_vgachip()
1639 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a); in init_vgachip()
1640 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b); in init_vgachip()
1641 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c); in init_vgachip()
1642 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d); in init_vgachip()
1643 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e); in init_vgachip()
1644 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f); in init_vgachip()
1647 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01); in init_vgachip()
1648 /* Overscan color reg.: reg. 0 */ in init_vgachip()
1649 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00); in init_vgachip()
1651 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f); in init_vgachip()
1653 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00); in init_vgachip()
1655 WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */ in init_vgachip()
1658 vga_wgfx(cinfo->regbase, CL_GR31, 0x04); in init_vgachip()
1660 vga_wgfx(cinfo->regbase, CL_GR31, 0x00); in init_vgachip()
1663 WHDR(cinfo, 0); /* Hidden DAC register: - */ in init_vgachip()
1670 static int IsOn = 0; /* XXX not ok for multiple boards */ in switch_monitor()
1680 WSFR(cinfo, 0xff); in switch_monitor()
1686 WSFR(cinfo, cinfo->SFR | 0x21); in switch_monitor()
1689 WSFR(cinfo, cinfo->SFR | 0x28); in switch_monitor()
1692 WSFR(cinfo, 0x6f); in switch_monitor()
1699 WSFR(cinfo, cinfo->SFR & 0xde); in switch_monitor()
1702 WSFR(cinfo, cinfo->SFR & 0xd7); in switch_monitor()
1705 WSFR(cinfo, 0x4f); in switch_monitor()
1723 while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03) in cirrusfb_sync()
1726 return 0; in cirrusfb_sync()
1765 info->fix.line_length, 0x40); in cirrusfb_fillrect()
1813 unsigned char op = (info->var.bits_per_pixel == 24) ? 0xc : 0x4; in cirrusfb_imageblit()
1821 op == 0xc) in cirrusfb_imageblit()
1843 info->fix.line_length, 0x40); in cirrusfb_imageblit()
1874 switch ((SRF & 0x18)) { in cirrusfb_get_memsize()
1875 case 0x08: in cirrusfb_get_memsize()
1878 case 0x10: in cirrusfb_get_memsize()
1884 case 0x18: in cirrusfb_get_memsize()
1894 if (cinfo->btype != BT_ALPINE && (SRF & 0x80) != 0) in cirrusfb_get_memsize()
1909 *display = 0; in get_pci_addrs()
1910 *registers = 0; in get_pci_addrs()
1914 if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) { in get_pci_addrs()
1916 *registers = pci_resource_start(pdev, 0); in get_pci_addrs()
1918 *display = pci_resource_start(pdev, 0); in get_pci_addrs()
1922 assert(*display != 0); in get_pci_addrs()
1933 #if 0 /* if system didn't claim this region, we would... */ in cirrusfb_pci_unmap()
1934 release_mem_region(0xA0000, 65535); in cirrusfb_pci_unmap()
1937 release_region(0x3C0, 32); in cirrusfb_pci_unmap()
2009 info->fix.type_aux = 0; in cirrusfb_set_fbinfo()
2012 info->fix.ywrapstep = 0; in cirrusfb_set_fbinfo()
2014 /* FIXME: map region at 0xB8000 if available, fill in here */ in cirrusfb_set_fbinfo()
2015 info->fix.mmio_len = 0; in cirrusfb_set_fbinfo()
2017 fb_alloc_cmap(&info->cmap, 256, 0); in cirrusfb_set_fbinfo()
2019 return 0; in cirrusfb_set_fbinfo()
2033 dev_dbg(info->device, "(RAM start set to: 0x%p)\n", info->screen_base); in cirrusfb_register()
2035 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8); in cirrusfb_register()
2045 if (err < 0) { in cirrusfb_register()
2053 if (err < 0) { in cirrusfb_register()
2059 return 0; in cirrusfb_register()
2070 switch_monitor(cinfo, 0); in cirrusfb_cleanup()
2088 if (ret < 0) { in cirrusfb_pci_register()
2103 " Found PCI device, base address 0 is 0x%Lx, btype set to %d\n", in cirrusfb_pci_register()
2104 (unsigned long long)pdev->resource[0].start, cinfo->btype); in cirrusfb_pci_register()
2105 dev_dbg(info->device, " base address 1 is 0x%Lx\n", in cirrusfb_pci_register()
2113 cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000); in cirrusfb_pci_register()
2115 dev_dbg(info->device, "Board address: 0x%lx, register address: 0x%lx\n", in cirrusfb_pci_register()
2122 if (ret < 0) { in cirrusfb_pci_register()
2123 dev_err(info->device, "cannot reserve region 0x%lx, abort\n", in cirrusfb_pci_register()
2127 #if 0 /* if the system didn't claim this region, we would... */ in cirrusfb_pci_register()
2128 if (!request_mem_region(0xA0000, 65535, "cirrusfb")) { in cirrusfb_pci_register()
2129 dev_err(info->device, "cannot reserve region 0x%lx, abort\n", in cirrusfb_pci_register()
2130 0xA0000L); in cirrusfb_pci_register()
2135 if (request_region(0x3C0, 32, "cirrusfb")) in cirrusfb_pci_register()
2149 "Cirrus Logic chipset on PCI bus, RAM (%lu kB) at 0x%lx\n", in cirrusfb_pci_register()
2155 return 0; in cirrusfb_pci_register()
2160 release_region(0x3C0, 32); in cirrusfb_pci_register()
2161 #if 0 in cirrusfb_pci_register()
2162 release_mem_region(0xA0000, 65535); in cirrusfb_pci_register()
2187 #if 0
2242 "%s board detected, REG at 0x%lx, %lu MiB RAM at 0x%lx\n", in cirrusfb_zorro_register()
2277 "Cirrus Logic chipset on Zorro bus, RAM (%lu MiB) at 0x%lx\n", in cirrusfb_zorro_register()
2293 return 0; in cirrusfb_zorro_register()
2331 return 0; in cirrusfb_setup()
2344 return 0; in cirrusfb_setup()
2358 int error = 0; in cirrusfb_init()
2389 module_param(mode_option, charp, 0);
2391 module_param(noaccel, bool, 0);
2409 unsigned long regofs = 0; in WGen()
2416 regofs = 0xfff; in WGen()
2425 unsigned long regofs = 0; in RGen()
2432 regofs = 0xfff; in RGen()
2443 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) { in AttrOn()
2450 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */ in AttrOn()
2451 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33); in AttrOn()
2454 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00); in AttrOn()
2471 /* first write 0 to pixel mask (3c6) */ in WHDR()
2472 WGen(cinfo, VGA_PEL_MSK, 0x00); in WHDR()
2498 /* ## is this mask always 0xff? */ in WHDR()
2499 WGen(cinfo, VGA_PEL_MSK, 0xff); in WHDR()
2510 z_writeb(val, cinfo->regbase + 0x8000); in WSFR()
2522 z_writeb(val, cinfo->regbase + 0x9000); in WSFR2()
2526 /*** WClut - set CLUT entry (range: 0..63) ***/
2540 data += 0xfff; in WClut()
2551 #if 0
2552 /*** RClut - read CLUT entry (range 0..63) ***/
2563 data += 0xfff;
2584 while (vga_rgfx(regbase, CL_GR31) & 0x08) in cirrusfb_WaitBLT()
2602 vga_wgfx(regbase, CL_GR24, line_length & 0xff); in cirrusfb_set_blitter()
2606 vga_wgfx(regbase, CL_GR26, line_length & 0xff); in cirrusfb_set_blitter()
2612 vga_wgfx(regbase, CL_GR20, nwidth & 0xff); in cirrusfb_set_blitter()
2618 vga_wgfx(regbase, CL_GR22, nheight & 0xff); in cirrusfb_set_blitter()
2624 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff)); in cirrusfb_set_blitter()
2632 vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff)); in cirrusfb_set_blitter()
2642 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */ in cirrusfb_set_blitter()
2645 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */ in cirrusfb_set_blitter()
2665 bltmode = 0x00; in cirrusfb_BitBLT()
2671 bltmode |= 0x01; in cirrusfb_BitBLT()
2673 bltmode |= 0x01; in cirrusfb_BitBLT()
2713 op = 0x80; in cirrusfb_RectFill()
2717 op = 0x90; in cirrusfb_RectFill()
2722 op = 0xa0; in cirrusfb_RectFill()
2727 op = 0xb0; in cirrusfb_RectFill()
2730 0, ndest, op | blitmode, line_length); in cirrusfb_RectFill()
2746 *nom = 0; in bestclock()
2747 *den = 0; in bestclock()
2748 *div = 0; in bestclock()
2756 int s = 0; in bestclock()
2818 unsigned char val = 0; in cirrusfb_dbg_print_regs()
2841 dev_dbg(info->device, "%8s = 0x%02X\n", name, val); in cirrusfb_dbg_print_regs()
2864 "CR00", 0x00, in cirrusfb_dbg_reg_dump()
2865 "CR01", 0x01, in cirrusfb_dbg_reg_dump()
2866 "CR02", 0x02, in cirrusfb_dbg_reg_dump()
2867 "CR03", 0x03, in cirrusfb_dbg_reg_dump()
2868 "CR04", 0x04, in cirrusfb_dbg_reg_dump()
2869 "CR05", 0x05, in cirrusfb_dbg_reg_dump()
2870 "CR06", 0x06, in cirrusfb_dbg_reg_dump()
2871 "CR07", 0x07, in cirrusfb_dbg_reg_dump()
2872 "CR08", 0x08, in cirrusfb_dbg_reg_dump()
2873 "CR09", 0x09, in cirrusfb_dbg_reg_dump()
2874 "CR0A", 0x0A, in cirrusfb_dbg_reg_dump()
2875 "CR0B", 0x0B, in cirrusfb_dbg_reg_dump()
2876 "CR0C", 0x0C, in cirrusfb_dbg_reg_dump()
2877 "CR0D", 0x0D, in cirrusfb_dbg_reg_dump()
2878 "CR0E", 0x0E, in cirrusfb_dbg_reg_dump()
2879 "CR0F", 0x0F, in cirrusfb_dbg_reg_dump()
2880 "CR10", 0x10, in cirrusfb_dbg_reg_dump()
2881 "CR11", 0x11, in cirrusfb_dbg_reg_dump()
2882 "CR12", 0x12, in cirrusfb_dbg_reg_dump()
2883 "CR13", 0x13, in cirrusfb_dbg_reg_dump()
2884 "CR14", 0x14, in cirrusfb_dbg_reg_dump()
2885 "CR15", 0x15, in cirrusfb_dbg_reg_dump()
2886 "CR16", 0x16, in cirrusfb_dbg_reg_dump()
2887 "CR17", 0x17, in cirrusfb_dbg_reg_dump()
2888 "CR18", 0x18, in cirrusfb_dbg_reg_dump()
2889 "CR22", 0x22, in cirrusfb_dbg_reg_dump()
2890 "CR24", 0x24, in cirrusfb_dbg_reg_dump()
2891 "CR26", 0x26, in cirrusfb_dbg_reg_dump()
2892 "CR2D", 0x2D, in cirrusfb_dbg_reg_dump()
2893 "CR2E", 0x2E, in cirrusfb_dbg_reg_dump()
2894 "CR2F", 0x2F, in cirrusfb_dbg_reg_dump()
2895 "CR30", 0x30, in cirrusfb_dbg_reg_dump()
2896 "CR31", 0x31, in cirrusfb_dbg_reg_dump()
2897 "CR32", 0x32, in cirrusfb_dbg_reg_dump()
2898 "CR33", 0x33, in cirrusfb_dbg_reg_dump()
2899 "CR34", 0x34, in cirrusfb_dbg_reg_dump()
2900 "CR35", 0x35, in cirrusfb_dbg_reg_dump()
2901 "CR36", 0x36, in cirrusfb_dbg_reg_dump()
2902 "CR37", 0x37, in cirrusfb_dbg_reg_dump()
2903 "CR38", 0x38, in cirrusfb_dbg_reg_dump()
2904 "CR39", 0x39, in cirrusfb_dbg_reg_dump()
2905 "CR3A", 0x3A, in cirrusfb_dbg_reg_dump()
2906 "CR3B", 0x3B, in cirrusfb_dbg_reg_dump()
2907 "CR3C", 0x3C, in cirrusfb_dbg_reg_dump()
2908 "CR3D", 0x3D, in cirrusfb_dbg_reg_dump()
2909 "CR3E", 0x3E, in cirrusfb_dbg_reg_dump()
2910 "CR3F", 0x3F, in cirrusfb_dbg_reg_dump()
2918 "SR00", 0x00, in cirrusfb_dbg_reg_dump()
2919 "SR01", 0x01, in cirrusfb_dbg_reg_dump()
2920 "SR02", 0x02, in cirrusfb_dbg_reg_dump()
2921 "SR03", 0x03, in cirrusfb_dbg_reg_dump()
2922 "SR04", 0x04, in cirrusfb_dbg_reg_dump()
2923 "SR08", 0x08, in cirrusfb_dbg_reg_dump()
2924 "SR09", 0x09, in cirrusfb_dbg_reg_dump()
2925 "SR0A", 0x0A, in cirrusfb_dbg_reg_dump()
2926 "SR0B", 0x0B, in cirrusfb_dbg_reg_dump()
2927 "SR0D", 0x0D, in cirrusfb_dbg_reg_dump()
2928 "SR10", 0x10, in cirrusfb_dbg_reg_dump()
2929 "SR11", 0x11, in cirrusfb_dbg_reg_dump()
2930 "SR12", 0x12, in cirrusfb_dbg_reg_dump()
2931 "SR13", 0x13, in cirrusfb_dbg_reg_dump()
2932 "SR14", 0x14, in cirrusfb_dbg_reg_dump()
2933 "SR15", 0x15, in cirrusfb_dbg_reg_dump()
2934 "SR16", 0x16, in cirrusfb_dbg_reg_dump()
2935 "SR17", 0x17, in cirrusfb_dbg_reg_dump()
2936 "SR18", 0x18, in cirrusfb_dbg_reg_dump()
2937 "SR19", 0x19, in cirrusfb_dbg_reg_dump()
2938 "SR1A", 0x1A, in cirrusfb_dbg_reg_dump()
2939 "SR1B", 0x1B, in cirrusfb_dbg_reg_dump()
2940 "SR1C", 0x1C, in cirrusfb_dbg_reg_dump()
2941 "SR1D", 0x1D, in cirrusfb_dbg_reg_dump()
2942 "SR1E", 0x1E, in cirrusfb_dbg_reg_dump()
2943 "SR1F", 0x1F, in cirrusfb_dbg_reg_dump()