Lines Matching +full:0 +full:x0000003c
33 #define SSC_CR 0x00000000
37 #define SSC_CR_RXEN_OFFSET 0
46 #define SSC_CMR 0x00000004
48 #define SSC_CMR_DIV_OFFSET 0
51 #define SSC_RCMR 0x00000010
59 #define SSC_RCMR_CKS_OFFSET 0
70 #define SSC_RFMR 0x00000014
72 #define SSC_RFMR_DATLEN_OFFSET 0
93 #define SSC_TCMR 0x00000018
101 #define SSC_TCMR_CKS_OFFSET 0
110 #define SSC_TFMR 0x0000001c
114 #define SSC_TFMR_DATLEN_OFFSET 0
135 #define SSC_RHR 0x00000020
137 #define SSC_RHR_RDAT_OFFSET 0
140 #define SSC_THR 0x00000024
142 #define SSC_THR_TDAT_OFFSET 0
145 #define SSC_RSHR 0x00000030
147 #define SSC_RSHR_RSDAT_OFFSET 0
150 #define SSC_TSHR 0x00000034
152 #define SSC_TSHR_RSDAT_OFFSET 0
154 /* SSC Receive Compare 0 Register */
155 #define SSC_RC0R 0x00000038
157 #define SSC_RC0R_CP0_OFFSET 0
160 #define SSC_RC1R 0x0000003c
162 #define SSC_RC1R_CP1_OFFSET 0
165 #define SSC_SR 0x00000040
191 #define SSC_SR_TXRDY_OFFSET 0
196 #define SSC_IER 0x00000044
218 #define SSC_IER_TXRDY_OFFSET 0
223 #define SSC_IDR 0x00000048
245 #define SSC_IDR_TXRDY_OFFSET 0
250 #define SSC_IMR 0x0000004c
272 #define SSC_IMR_TXRDY_OFFSET 0
277 #define SSC_PDC_RPR 0x00000100
280 #define SSC_PDC_RCR 0x00000104
283 #define SSC_PDC_TPR 0x00000108
286 #define SSC_PDC_RNPR 0x00000110
289 #define SSC_PDC_RNCR 0x00000114
292 #define SSC_PDC_TCR 0x0000010c
295 #define SSC_PDC_TNPR 0x00000118
298 #define SSC_PDC_TNCR 0x0000011c
301 #define SSC_PDC_PTCR 0x00000120
305 #define SSC_PDC_PTCR_RXTEN_OFFSET 0
312 #define SSC_PDC_PTSR 0x00000124
314 #define SSC_PDC_PTSR_RXTEN_OFFSET 0