45 	{ .compatible = "rockchip,rk3066-spdif",
47 	{ .compatible = "rockchip,rk3188-spdif",
49 	{ .compatible = "rockchip,rk3228-spdif",
51 	{ .compatible = "rockchip,rk3288-spdif",
53 	{ .compatible = "rockchip,rk3328-spdif",
55 	{ .compatible = "rockchip,rk3366-spdif",
57 	{ .compatible = "rockchip,rk3368-spdif",
59 	{ .compatible = "rockchip,rk3399-spdif",
67 	struct rk_spdif_dev *spdif = dev_get_drvdata(dev);  in rk_spdif_runtime_suspend()  local
69 	regcache_cache_only(spdif->regmap, true);  in rk_spdif_runtime_suspend()
70 	clk_disable_unprepare(spdif->mclk);  in rk_spdif_runtime_suspend()
71 	clk_disable_unprepare(spdif->hclk);  in rk_spdif_runtime_suspend()
78 	struct rk_spdif_dev *spdif = dev_get_drvdata(dev);  in rk_spdif_runtime_resume()  local
81 	ret = clk_prepare_enable(spdif->mclk);  in rk_spdif_runtime_resume()
83 		dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);  in rk_spdif_runtime_resume()
87 	ret = clk_prepare_enable(spdif->hclk);  in rk_spdif_runtime_resume()
89 		clk_disable_unprepare(spdif->mclk);  in rk_spdif_runtime_resume()
90 		dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);  in rk_spdif_runtime_resume()
94 	regcache_cache_only(spdif->regmap, false);  in rk_spdif_runtime_resume()
95 	regcache_mark_dirty(spdif->regmap);  in rk_spdif_runtime_resume()
97 	ret = regcache_sync(spdif->regmap);  in rk_spdif_runtime_resume()
99 		clk_disable_unprepare(spdif->mclk);  in rk_spdif_runtime_resume()
100 		clk_disable_unprepare(spdif->hclk);  in rk_spdif_runtime_resume()
110 	struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);  in rk_spdif_hw_params()  local
133 	ret = clk_set_rate(spdif->mclk, mclk);  in rk_spdif_hw_params()
135 		dev_err(spdif->dev, "Failed to set module clock rate: %d\n",  in rk_spdif_hw_params()
140 	ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,  in rk_spdif_hw_params()
151 	struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);  in rk_spdif_trigger()  local
158 		ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,  in rk_spdif_trigger()
167 		ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,  in rk_spdif_trigger()
174 		ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,  in rk_spdif_trigger()
181 		ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,  in rk_spdif_trigger()
195 	struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);  in rk_spdif_dai_probe()  local
197 	dai->playback_dma_data = &spdif->playback_dma_data;  in rk_spdif_dai_probe()
226 	.name = "rockchip-spdif",
282 	struct rk_spdif_dev *spdif;  in rk_spdif_probe()  local
299 		/* Select the 8 channel SPDIF solution on RK3288 as  in rk_spdif_probe()
305 	spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);  in rk_spdif_probe()
306 	if (!spdif)  in rk_spdif_probe()
309 	spdif->hclk = devm_clk_get(&pdev->dev, "hclk");  in rk_spdif_probe()
310 	if (IS_ERR(spdif->hclk))  in rk_spdif_probe()
311 		return PTR_ERR(spdif->hclk);  in rk_spdif_probe()
313 	spdif->mclk = devm_clk_get(&pdev->dev, "mclk");  in rk_spdif_probe()
314 	if (IS_ERR(spdif->mclk))  in rk_spdif_probe()
315 		return PTR_ERR(spdif->mclk);  in rk_spdif_probe()
322 	spdif->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "hclk", regs,  in rk_spdif_probe()
324 	if (IS_ERR(spdif->regmap))  in rk_spdif_probe()
325 		return PTR_ERR(spdif->regmap);  in rk_spdif_probe()
327 	spdif->playback_dma_data.addr = res->start + SPDIF_SMPDR;  in rk_spdif_probe()
328 	spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;  in rk_spdif_probe()
329 	spdif->playback_dma_data.maxburst = 4;  in rk_spdif_probe()
331 	spdif->dev = &pdev->dev;  in rk_spdif_probe()
332 	dev_set_drvdata(&pdev->dev, spdif);  in rk_spdif_probe()
384 		.name = "rockchip-spdif",
391 MODULE_ALIAS("platform:rockchip-spdif");
392 MODULE_DESCRIPTION("ROCKCHIP SPDIF transceiver Interface");