56  * Configures GPIOs 126, 127 and 129 to 1.8V mode instead of 3.0V
146 	u32 v;  in am35xx_enable_emac_int()  local
148 	v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);  in am35xx_enable_emac_int()
149 	v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |  in am35xx_enable_emac_int()
151 	omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);  in am35xx_enable_emac_int()
157 	u32 v;  in am35xx_disable_emac_int()  local
159 	v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);  in am35xx_disable_emac_int()
160 	v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);  in am35xx_disable_emac_int()
161 	omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);  in am35xx_disable_emac_int()
172 	u32 v;  in am35xx_emac_reset()  local
174 	v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);  in am35xx_emac_reset()
175 	v &= ~AM35XX_CPGMACSS_SW_RST;  in am35xx_emac_reset()
176 	omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);  in am35xx_emac_reset()
447 	OF_DEV_AUXDATA("ti,omap2-iommu", 0x480bd400, "480bd400.mmu",
450 		       "480cb000.smartreflex", &omap_sr_pdata[OMAP_SR_CORE]),
452 		       "480c9000.smartreflex", &omap_sr_pdata[OMAP_SR_MPU]),
454 	OF_DEV_AUXDATA("ti,omap3-hsmmc", 0x480b4000, "480b4000.mmc", &mmc_pdata[1]),