Lines Matching +full:entry +full:- +full:address
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S
5 * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
7 * (Many of cache codes are from proc-arm926.S)
14 #include <asm/pgtable-hwdef.h>
16 #include "proc-macros.S"
19 * ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
35 ENTRY(cpu_arm946_proc_init)
36 ENTRY(cpu_arm946_switch_mm)
42 ENTRY(cpu_arm946_proc_fin)
44 bic r0, r0, #0x00001000 @ i-cache
45 bic r0, r0, #0x00000004 @ d-cache
51 * Params : r0 = address to jump to
55 ENTRY(cpu_arm946_reset)
62 bic ip, ip, #0x00001000 @ i-cache
72 ENTRY(cpu_arm946_do_idle)
81 ENTRY(arm946_flush_icache_all)
90 ENTRY(arm946_flush_user_cache_all)
98 ENTRY(arm946_flush_kern_cache_all)
105 mov r1, #(CACHE_DSEGMENTS - 1) << 29 @ 4 segments
106 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries
122 * specified address range.
124 * - start - start address (inclusive)
125 * - end - end address (exclusive)
126 * - flags - vm_flags describing address space
129 ENTRY(arm946_flush_user_cache_range)
137 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
140 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
141 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
144 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
147 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
161 * region described by start, end. If you have non-snooping
164 * - start - virtual start address
165 * - end - virtual end address
167 ENTRY(arm946_coherent_kern_range)
174 * region described by start, end. If you have non-snooping
177 * - start - virtual start address
178 * - end - virtual end address
181 ENTRY(arm946_coherent_user_range)
182 bic r0, r0, #CACHE_DLINESIZE - 1
183 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
184 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
198 * - addr - kernel address
199 * - size - region size
202 ENTRY(arm946_flush_kern_dcache_area)
204 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
216 * Invalidate (discard) the specified virtual address range.
221 * - start - virtual start address
222 * - end - virtual end address
227 tst r0, #CACHE_DLINESIZE - 1
228 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
229 tst r1, #CACHE_DLINESIZE - 1
230 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
232 bic r0, r0, #CACHE_DLINESIZE - 1
233 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
243 * Clean the specified virtual address range.
245 * - start - virtual start address
246 * - end - virtual end address
252 bic r0, r0, #CACHE_DLINESIZE - 1
253 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
264 * Clean and invalidate the specified virtual address range.
266 * - start - virtual start address
267 * - end - virtual end address
271 ENTRY(arm946_dma_flush_range)
272 bic r0, r0, #CACHE_DLINESIZE - 1
275 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
277 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
287 * - start - kernel virtual start address
288 * - size - size of region
289 * - dir - DMA direction
291 ENTRY(arm946_dma_map_area)
301 * - start - kernel virtual start address
302 * - size - size of region
303 * - dir - DMA direction
305 ENTRY(arm946_dma_unmap_area)
312 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
315 ENTRY(cpu_arm946_dcache_clean_area)
317 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
352 mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
353 mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
365 * region 0 (whole) rw -- : b0001
367 * region 2 (FLASH) rw r- : b0010
368 * region 3~7 (none) -- -- : b0000
376 orr r0, r0, #0x00001000 @ I-cache
377 orr r0, r0, #0x00000005 @ MPU/D-cache
383 .size __arm946_setup, . - __arm946_setup
387 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
394 string cpu_arm946_name, "ARM946E-S"
414 .size __arm946_proc_info, . - __arm946_proc_info