Lines Matching +full:trace +full:- +full:buffer +full:- +full:extension
1 # SPDX-License-Identifier: GPL-2.0-only
194 if $(cc-option,-fpatchable-function-entry=2)
259 ARM 64-bit (AArch64) Linux support.
269 depends on $(cc-option,-fpatchable-function-entry=2)
302 # VA_BITS - PAGE_SHIFT - 3
378 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
433 at stage-2.
441 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
446 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
449 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
455 data cache clean-and-invalidate.
463 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
468 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
477 data cache clean-and-invalidate.
485 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
490 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
493 If a Cortex-A53 processor is executing a store or prefetch for
500 data cache clean-and-invalidate.
508 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
513 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
522 data cache clean-and-invalidate.
530 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
534 erratum 832075 on Cortex-A57 parts up to r1p2.
536 Affected Cortex-A57 parts might deadlock when exclusive load/store
537 instructions to Write-Back memory are mixed with Device loads.
539 The workaround is to promote device loads to use Load-Acquire
548 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
553 erratum 834220 on Cortex-A57 parts up to r1p2.
555 Affected Cortex-A57 parts might report a Stage 2 translation
569 …bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic i…
573 This option removes the AES hwcap for aarch32 user-space to
574 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
585 bool "Cortex-A53: 845719: a load might read incorrect data"
590 erratum 845719 on Cortex-A53 parts up to r0p4.
592 When running a compat (AArch32) userspace on an affected Cortex-A53
598 return to a 32-bit task.
606 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
609 This option links the kernel with '--fix-cortex-a53-843419' and
612 Cortex-A53 parts up to r0p4.
617 def_bool $(ld-option,--fix-cortex-a53-843419)
620 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
623 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
625 Affected Cortex-A55 cores (all revisions) could cause incorrect
627 without a break-before-make. The workaround is to disable the usage
634 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
638 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
641 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
651 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
655 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
657 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
664 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
668 This option adds work arounds for ARM Cortex-A57 erratum 1319537
671 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
677 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
681 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
683 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
693 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
697 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
699 Under very rare circumstances, affected Cortex-A55 CPUs
700 may not handle a race between a break-before-make sequence on one
710 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
714 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
716 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
720 break-before-make sequence, then under very rare circumstances
726 bool "Cortex-A76: Software Step might prevent interrupt recognition"
729 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
731 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
744 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
747 This option adds a workaround for ARM Neoverse-N1 erratum
750 Affected Neoverse-N1 cores could execute a stale instruction when
755 forces user-space to perform cache maintenance.
760 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
763 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
765 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
766 of a store-exclusive or read of PAR_EL1 and a load with device or
767 non-cacheable memory attributes. The workaround depends on a firmware
783 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
786 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
787 Affected Cortex-A510 might not respect the ordering rules for
794 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
797 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
798 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
806 previous guest entry, and can be restored from the in-memory copy.
811 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
814 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
815 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
819 user-space should not be using these instructions.
824 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
829 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
831 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
832 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
836 256 bytes before enabling the buffer and filling the first 256 bytes of
837 the buffer with ETM ignore packets upon disabling.
842 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
847 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
849 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
850 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
854 256 bytes before enabling the buffer and filling the first 256 bytes of
855 the buffer with ETM ignore packets upon disabling.
863 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
867 Enable workaround for ARM Cortex-A710 erratum 2054223
869 Affected cores may fail to flush the trace data on a TSB instruction, when
870 the PE is in trace prohibited state. This will cause losing a few bytes
871 of the trace cached.
878 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
882 Enable workaround for ARM Neoverse-N2 erratum 2067961
884 Affected cores may fail to flush the trace data on a TSB instruction, when
885 the PE is in trace prohibited state. This will cause losing a few bytes
886 of the trace cached.
896 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
901 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
903 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
914 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
919 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
921 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
932 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
936 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
938 Under very rare circumstances, affected Cortex-A510 CPUs
939 may not handle a race between a break-before-make sequence on one
949 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
953 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
955 Affected Cortex-A510 core might fail to write into system registers after the
967 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
971 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
973 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
974 prohibited within the CPU. As a result, the trace buffer or trace buffer state
975 might be corrupted. This happens after TRBE buffer has been enabled by setting
977 execution changes from a context, in which trace is prohibited to one where it
978 isn't, or vice versa. In these mentioned conditions, the view of whether trace
979 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
980 the trace buffer state might be corrupted.
983 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
990 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
994 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
996 Affected Cortex-A510 core might cause trace data corruption, when being written
998 trace data.
1008 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1012 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1015 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1025 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1028 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1030 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1031 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1034 Only user-space does executable to non-executable permission transition via
1035 mprotect() system call. Workaround the problem by doing a break-before-make
1044 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1048 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1050 On an affected Cortex-A520 core, a speculatively executed unprivileged
1058 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1062 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1064 On an affected Cortex-A510 core, a speculatively executed unprivileged
1077 This implements two gicv3-its errata workarounds for ThunderX. Both
1117 contains data for a non-current ASID. The fix is to
1128 interrupts in host. Trapping both GICv3 group-0 and group-1
1151 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1154 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1155 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1159 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1160 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1161 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1162 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1165 The workaround only affects the Fujitsu-A64FX.
1225 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1235 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1242 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1246 MSI doorbell writes with non-zero values for the device ID.
1275 look-up. AArch32 emulation requires applications compiled
1291 bool "36-bit" if EXPERT
1295 bool "39-bit"
1299 bool "42-bit"
1303 bool "47-bit"
1307 bool "48-bit"
1310 bool "52-bit"
1313 Enable 52-bit virtual addressing for userspace when explicitly
1314 requested via a hint to mmap(). The kernel will also use 52-bit
1316 this feature is available, otherwise it reverts to 48-bit).
1318 NOTE: Enabling 52-bit virtual addressing in conjunction with
1321 impact on its susceptibility to brute-force attacks.
1323 If unsure, select 48-bit virtual addressing instead.
1328 bool "Force 52-bit virtual addresses for userspace"
1331 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1332 to maintain compatibility with older software by providing 48-bit VAs
1335 This configuration option disables the 48-bit compatibility logic, and
1336 forces all userspace addresses to be 52-bit on HW that supports it. One
1357 bool "48-bit"
1360 bool "52-bit (ARMv8.2)"
1364 Enable support for a 52-bit physical address space, introduced as
1365 part of the ARMv8.2-LPA extension.
1368 do not support ARMv8.2-LPA, but with some added memory overhead (and
1387 bool "Build big-endian kernel"
1389 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1392 Say Y if you plan on running a kernel with a big-endian userspace.
1395 bool "Build little-endian kernel"
1397 Say Y if you plan on running a kernel with a little-endian userspace.
1403 bool "Multi-core scheduler support"
1405 Multi-core scheduler support improves the CPU scheduler's decision
1406 making when dealing with multi-core CPU chips at a cost of slightly
1415 by sharing mid-level caches, last-level cache tags or internal
1426 int "Maximum number of CPUs (2-4096)"
1431 bool "Support for hot-pluggable CPUs"
1448 Enable NUMA (Non-Uniform Memory Access) support.
1476 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1539 # so the maximum value of MAX_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1542 # ----+-------------------+--------------+-----------------+--------------------+
1570 Speculation attacks against some high-performance processors can
1582 Speculation attacks against some high-performance processors can
1584 When taking an exception from user-space, a sequence of branches
1591 Apply read-only attributes of VM areas to the linear alias of
1592 the backing pages as well. This prevents code or read-only data
1605 user-space memory directly by pointing TTBR0_EL1 to a reserved
1616 Documentation/arch/arm64/tagged-address-abi.rst.
1619 bool "Kernel support for 32-bit EL0"
1625 This option enables support for a 32-bit EL0 running under a 64-bit
1626 kernel at EL1. AArch32-specific components such as system calls,
1634 If you want to execute 32-bit userspace applications, say Y.
1639 bool "Enable kuser helpers page for 32-bit applications"
1642 Warning: disabling this option may break 32-bit user programs.
1666 bool "Enable vDSO for 32-bit applications"
1672 Place in the process address space of 32-bit applications an
1676 You must have a 32-bit build of glibc 2.22 or later for programs
1680 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1684 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1685 otherwise with '-marm'.
1688 bool "Fix up misaligned multi-word loads and stores in user space"
1730 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1731 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1746 The SETEND instruction alters the data-endianness of the
1754 for this feature to be enabled. If a new CPU - which doesn't support mixed
1755 endian - is hotplugged in after this feature has been enabled, there could
1774 Similarly, writes to read-only pages with the DBM bit set will
1775 clear the read-only bit (AP[2]) instead of raising a
1779 to work on pre-ARMv8.1 hardware and the performance impact is
1787 prevents the kernel or hypervisor from accessing user-space (EL0)
1797 def_bool $(as-instr,.arch_extension lse)
1812 Say Y here to make use of these instructions for the in-kernel
1823 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1826 def_bool $(as-instr,.arch armv8.2-a+sha3)
1853 and access the new registers if the system supports the extension.
1886 context-switched along with the process.
1909 If the compiler supports the -mbranch-protection or
1910 -msign-return-address flag (e.g. GCC 7 or later), then this option
1921 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1925 def_bool $(cc-option,-msign-return-address=all)
1928 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1931 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1934 def_bool $(as-instr,.arch_extension rcpc)
1941 bool "Enable support for the Activity Monitors Unit CPU extension"
1944 The activity monitors extension is an optional extension introduced
1948 To enable the use of this extension on CPUs that implement it, say Y.
1952 extension. The required support is present in:
1964 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1971 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1982 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
2016 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
2027 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2043 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2047 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2050 bool "Memory Tagging Extension support"
2062 architectural support for run-time, always-on detection of
2064 to eliminate vulnerabilities arising from memory-unsafe
2068 Extension at EL0 (i.e. for userspace).
2072 not be allowed a late bring-up.
2078 Documentation/arch/arm64/memory-tagging-extension.rst.
2090 Access Never to be used with Execute-only mappings.
2097 bool "ARM Scalable Vector Extension support"
2100 The Scalable Vector Extension (SVE) is an extension to the AArch64
2105 To enable use of this extension on CPUs that implement it, say Y.
2121 If you need the kernel to boot on SVE-capable hardware with broken
2128 bool "ARM Scalable Matrix Extension support"
2132 The Scalable Matrix Extension (SME) is an extension to the AArch64
2139 bool "Support for NMI-like interrupts"
2142 Adds support for mimicking Non-Maskable Interrupts through the use of
2185 random u64 value in /chosen/kaslr-seed at kernel entry.
2212 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
2244 Provide a set of default command-line options at build time by
2258 Uses the command-line options passed by the boot loader. If
2268 command-line options your boot loader passes to the kernel.
2290 by UEFI firmware (such as non-volatile variables, realtime
2304 continue to boot on existing non-UEFI platforms.