Lines Matching +full:4 +full:kb +full:- +full:page

1 # SPDX-License-Identifier: GPL-2.0
9 	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12 	  On other systems (such as the SH-3 and 4) where an MMU exists,
28 	  The kernel page allocator limits the size of maximal physically
35 	  The page size is not necessarily 4KB. Keep this in mind when
77 	bool "Support 32-bit physical addressing through PMB"
83 	  32-bits through the SH-4A PMB. If this is not set, legacy
84 	  29-bit physical addressing will be used.
91 	bool "Support vsyscall page"
95 	  This will enable support for the kernel mapping a vDSO page
100 	  For systems with an MMU that can afford to give up a page,
104 	bool "Non-Uniform Memory Access (NUMA) Support"
151 	prompt "Kernel page size"
155 	bool "4kB"
157 	  This is the default page size used by all SuperH CPUs.
160 	bool "8kB"
163 	  This enables 8kB pages as supported by SH-X2 and later MMUs.
166 	bool "16kB"
169 	  This enables 16kB pages on MMU-less SH systems.
172 	bool "64kB"
175 	  This enables support for 64kB pages, possible on all SH-4
181 	prompt "HugeTLB page size"
187 	bool "64kB"
191 	bool "256kB"
198 	bool "4MB"
208 	bool "Multi-core scheduler support"
212 	  Multi-core scheduler support improves the CPU scheduler's decision
213 	  making when dealing with multi-core CPU chips at a cost of slightly
221 	bool "Enable 32KB cache size for SH7705"
231 	bool "Write-back"
234 	bool "Write-through"
236 	  Selecting this option will configure the caches in write-through
237 	  mode, as opposed to the default write-back configuration.
239 	  Since there's sill some aliasing issues on SH-4, this option will