Lines Matching +full:reserved +full:- +full:ipi +full:- +full:vectors
1 // SPDX-License-Identifier: GPL-2.0-only
49 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
66 /* step-by-step approximation to mitigate fluctuation */
78 __kvm_lapic_set_reg(apic->regs, reg_off, val); in kvm_lapic_set_reg()
89 return __kvm_lapic_get_reg64(apic->regs, reg); in kvm_lapic_get_reg64()
101 __kvm_lapic_set_reg64(apic->regs, reg, val); in kvm_lapic_set_reg64()
111 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_pending_eoi()
113 return apic_test_vector(vector, apic->regs + APIC_ISR) || in kvm_apic_pending_eoi()
114 apic_test_vector(vector, apic->regs + APIC_IRR); in kvm_apic_pending_eoi()
144 return apic->vcpu->vcpu_id; in kvm_x2apic_id()
150 (kvm_mwait_in_guest(vcpu->kvm) || kvm_hlt_in_guest(vcpu->kvm)); in kvm_can_post_timer_interrupt()
156 && !(kvm_mwait_in_guest(vcpu->kvm) || in kvm_can_use_hv_timer()
162 return kvm_can_post_timer_interrupt(vcpu) && vcpu->mode == IN_GUEST_MODE; in kvm_use_posted_timer_interrupt()
172 switch (map->logical_mode) { in kvm_apic_map_get_logical_dest()
175 *cluster = map->xapic_flat_map; in kvm_apic_map_get_logical_dest()
180 u32 max_apic_id = map->max_apic_id; in kvm_apic_map_get_logical_dest()
183 u8 cluster_size = min(max_apic_id - offset + 1, 16U); in kvm_apic_map_get_logical_dest()
185 offset = array_index_nospec(offset, map->max_apic_id + 1); in kvm_apic_map_get_logical_dest()
186 *cluster = &map->phys_map[offset]; in kvm_apic_map_get_logical_dest()
187 *mask = dest_id & (0xffff >> (16 - cluster_size)); in kvm_apic_map_get_logical_dest()
195 *cluster = map->xapic_flat_map; in kvm_apic_map_get_logical_dest()
199 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf]; in kvm_apic_map_get_logical_dest()
221 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_recalculate_phys_map()
231 if (WARN_ON_ONCE(xapic_id > new->max_apic_id)) in kvm_recalculate_phys_map()
232 return -EINVAL; in kvm_recalculate_phys_map()
240 if (x2apic_id > new->max_apic_id) in kvm_recalculate_phys_map()
241 return -E2BIG; in kvm_recalculate_phys_map()
246 * 32-bit value. Any unwanted aliasing due to truncation results will in kvm_recalculate_phys_map()
249 if (!apic_x2apic_mode(apic) && xapic_id != (u8)vcpu->vcpu_id) in kvm_recalculate_phys_map()
253 * Apply KVM's hotplug hack if userspace has enable 32-bit APIC IDs. in kvm_recalculate_phys_map()
259 * Honor the architectural (and KVM's non-optimized) behavior if in kvm_recalculate_phys_map()
260 * userspace has not enabled 32-bit x2APIC IDs. Each APIC is supposed in kvm_recalculate_phys_map()
266 if (vcpu->kvm->arch.x2apic_format) { in kvm_recalculate_phys_map()
269 new->phys_map[x2apic_id] = apic; in kvm_recalculate_phys_map()
271 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id]) in kvm_recalculate_phys_map()
272 new->phys_map[xapic_id] = apic; in kvm_recalculate_phys_map()
284 if (new->phys_map[physical_id]) in kvm_recalculate_phys_map()
285 return -EINVAL; in kvm_recalculate_phys_map()
287 new->phys_map[physical_id] = apic; in kvm_recalculate_phys_map()
296 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_recalculate_logical_map()
302 if (new->logical_mode == KVM_APIC_MODE_MAP_DISABLED) in kvm_recalculate_logical_map()
323 * To optimize logical mode delivery, all software-enabled APICs must in kvm_recalculate_logical_map()
326 if (new->logical_mode == KVM_APIC_MODE_SW_DISABLED) { in kvm_recalculate_logical_map()
327 new->logical_mode = logical_mode; in kvm_recalculate_logical_map()
328 } else if (new->logical_mode != logical_mode) { in kvm_recalculate_logical_map()
329 new->logical_mode = KVM_APIC_MODE_MAP_DISABLED; in kvm_recalculate_logical_map()
334 * In x2APIC mode, the LDR is read-only and derived directly from the in kvm_recalculate_logical_map()
347 new->logical_mode = KVM_APIC_MODE_MAP_DISABLED; in kvm_recalculate_logical_map()
354 ldr = ffs(mask) - 1; in kvm_recalculate_logical_map()
356 new->logical_mode = KVM_APIC_MODE_MAP_DISABLED; in kvm_recalculate_logical_map()
362 * CLEAN -> DIRTY and UPDATE_IN_PROGRESS -> DIRTY changes happen without a lock.
364 * DIRTY -> UPDATE_IN_PROGRESS and UPDATE_IN_PROGRESS -> CLEAN happen with
382 /* Read kvm->arch.apic_map_dirty before kvm->arch.apic_map. */ in kvm_recalculate_apic_map()
383 if (atomic_read_acquire(&kvm->arch.apic_map_dirty) == CLEAN) in kvm_recalculate_apic_map()
387 "Dirty APIC map without an in-kernel local APIC"); in kvm_recalculate_apic_map()
389 mutex_lock(&kvm->arch.apic_map_lock); in kvm_recalculate_apic_map()
393 * Read kvm->arch.apic_map_dirty before kvm->arch.apic_map (if clean) in kvm_recalculate_apic_map()
396 * ID, i.e. the map may still show up as in-progress. In that case in kvm_recalculate_apic_map()
399 if (atomic_cmpxchg_acquire(&kvm->arch.apic_map_dirty, in kvm_recalculate_apic_map()
402 mutex_unlock(&kvm->arch.apic_map_lock); in kvm_recalculate_apic_map()
417 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic)); in kvm_recalculate_apic_map()
426 new->max_apic_id = max_id; in kvm_recalculate_apic_map()
427 new->logical_mode = KVM_APIC_MODE_SW_DISABLED; in kvm_recalculate_apic_map()
437 if (r == -E2BIG) { in kvm_recalculate_apic_map()
458 if (!new || new->logical_mode == KVM_APIC_MODE_MAP_DISABLED) in kvm_recalculate_apic_map()
468 old = rcu_dereference_protected(kvm->arch.apic_map, in kvm_recalculate_apic_map()
469 lockdep_is_held(&kvm->arch.apic_map_lock)); in kvm_recalculate_apic_map()
470 rcu_assign_pointer(kvm->arch.apic_map, new); in kvm_recalculate_apic_map()
472 * Write kvm->arch.apic_map before clearing apic->apic_map_dirty. in kvm_recalculate_apic_map()
475 atomic_cmpxchg_release(&kvm->arch.apic_map_dirty, in kvm_recalculate_apic_map()
477 mutex_unlock(&kvm->arch.apic_map_lock); in kvm_recalculate_apic_map()
480 call_rcu(&old->rcu, kvm_apic_map_free); in kvm_recalculate_apic_map()
491 if (enabled != apic->sw_enabled) { in apic_set_spiv()
492 apic->sw_enabled = enabled; in apic_set_spiv()
498 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in apic_set_spiv()
503 kvm_make_request(KVM_REQ_APF_READY, apic->vcpu); in apic_set_spiv()
509 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_xapic_id()
515 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_ldr()
521 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_dfr()
528 WARN_ON_ONCE(id != apic->vcpu->vcpu_id); in kvm_apic_set_x2apic_id()
532 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_x2apic_id()
542 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; in apic_lvtt_oneshot()
547 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; in apic_lvtt_period()
552 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; in apic_lvtt_tscdeadline()
562 return apic->nr_lvt_entries > lvt_index; in kvm_lapic_lvt_supported()
567 return KVM_APIC_MAX_NR_LVT_ENTRIES - !(vcpu->arch.mcg_cap & MCG_CMCI_P); in kvm_apic_calc_nr_lvt_entries()
572 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_version()
578 v = APIC_VERSION | ((apic->nr_lvt_entries - 1) << 16); in kvm_apic_set_version()
581 * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation) in kvm_apic_set_version()
583 * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC in kvm_apic_set_version()
584 * version first and level-triggered interrupts never get EOIed in in kvm_apic_set_version()
588 !ioapic_in_kernel(vcpu->kvm)) in kvm_apic_set_version()
596 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_after_set_mcg_cap()
599 if (!lapic_in_kernel(vcpu) || nr_lvt_entries == apic->nr_lvt_entries) in kvm_apic_after_set_mcg_cap()
603 for (i = apic->nr_lvt_entries; i < nr_lvt_entries; i++) in kvm_apic_after_set_mcg_cap()
606 apic->nr_lvt_entries = nr_lvt_entries; in kvm_apic_after_set_mcg_cap()
627 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; in find_highest_vector()
628 vec >= 0; vec -= APIC_VECTORS_PER_REG) { in find_highest_vector()
634 return -1; in find_highest_vector()
657 max_updated_irr = -1; in __kvm_apic_update_irr()
658 *max_irr = -1; in __kvm_apic_update_irr()
682 return ((max_updated_irr != -1) && in __kvm_apic_update_irr()
689 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_update_irr()
690 bool irr_updated = __kvm_apic_update_irr(pir, apic->regs, max_irr); in kvm_apic_update_irr()
692 if (unlikely(!apic->apicv_active && irr_updated)) in kvm_apic_update_irr()
693 apic->irr_pending = true; in kvm_apic_update_irr()
700 return find_highest_vector(apic->regs + APIC_IRR); in apic_search_irr()
711 if (!apic->irr_pending) in apic_find_highest_irr()
712 return -1; in apic_find_highest_irr()
715 ASSERT(result == -1 || result >= 16); in apic_find_highest_irr()
722 if (unlikely(apic->apicv_active)) { in apic_clear_irr()
724 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); in apic_clear_irr()
725 static_call_cond(kvm_x86_hwapic_irr_update)(apic->vcpu, in apic_clear_irr()
728 apic->irr_pending = false; in apic_clear_irr()
729 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); in apic_clear_irr()
730 if (apic_search_irr(apic) != -1) in apic_clear_irr()
731 apic->irr_pending = true; in apic_clear_irr()
737 apic_clear_irr(vec, vcpu->arch.apic); in kvm_apic_clear_irr()
743 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) in apic_set_isr()
751 if (unlikely(apic->apicv_active)) in apic_set_isr()
754 ++apic->isr_count; in apic_set_isr()
755 BUG_ON(apic->isr_count > MAX_APIC_VECTOR); in apic_set_isr()
761 apic->highest_isr_cache = vec; in apic_set_isr()
771 * is always -1, with APIC virtualization enabled. in apic_find_highest_isr()
773 if (!apic->isr_count) in apic_find_highest_isr()
774 return -1; in apic_find_highest_isr()
775 if (likely(apic->highest_isr_cache != -1)) in apic_find_highest_isr()
776 return apic->highest_isr_cache; in apic_find_highest_isr()
778 result = find_highest_vector(apic->regs + APIC_ISR); in apic_find_highest_isr()
779 ASSERT(result == -1 || result >= 16); in apic_find_highest_isr()
786 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) in apic_clear_isr()
791 * uses the Hyper-V APIC enlightenment. In this case we may need in apic_clear_isr()
796 if (unlikely(apic->apicv_active)) in apic_clear_isr()
799 --apic->isr_count; in apic_clear_isr()
800 BUG_ON(apic->isr_count < 0); in apic_clear_isr()
801 apic->highest_isr_cache = -1; in apic_clear_isr()
812 return apic_find_highest_irr(vcpu->arch.apic); in kvm_lapic_find_highest_irr()
823 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_irq()
825 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, in kvm_apic_set_irq()
826 irq->level, irq->trig_mode, dest_map); in kvm_apic_set_irq()
835 if (min > map->max_apic_id) in __pv_send_ipi()
839 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) { in __pv_send_ipi()
840 if (map->phys_map[min + i]) { in __pv_send_ipi()
841 vcpu = map->phys_map[min + i]->vcpu; in __pv_send_ipi()
859 return -KVM_EINVAL; in kvm_pv_send_ipi()
867 map = rcu_dereference(kvm->arch.apic_map); in kvm_pv_send_ipi()
869 count = -EOPNOTSUPP; in kvm_pv_send_ipi()
883 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, in pv_eoi_put_user()
890 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, in pv_eoi_get_user()
896 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; in pv_eoi_enabled()
904 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); in pv_eoi_set_pending()
924 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); in pv_eoi_test_and_clr_pending()
933 highest_irr = static_call(kvm_x86_sync_pir_to_irr)(apic->vcpu); in apic_has_interrupt_for_ppr()
936 if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr) in apic_has_interrupt_for_ppr()
937 return -1; in apic_has_interrupt_for_ppr()
949 isrv = (isr != -1) ? isr : 0; in __apic_update_ppr()
968 apic_has_interrupt_for_ppr(apic, ppr) != -1) in apic_update_ppr()
969 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in apic_update_ppr()
974 apic_update_ppr(vcpu->arch.apic); in kvm_apic_update_ppr()
1038 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
1042 * - in-kernel IOAPIC messages have to be delivered directly to
1045 * rewrites the destination of non-IPI messages from APIC_BROADCAST
1049 * important when userspace wants to use x2APIC-format MSIs, because
1050 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
1055 bool ipi = source != NULL; in kvm_apic_mda() local
1057 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled && in kvm_apic_mda()
1058 !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target)) in kvm_apic_mda()
1067 struct kvm_lapic *target = vcpu->arch.apic; in kvm_apic_match_dest()
1093 int i, idx = -1; in kvm_vector_to_index()
1107 if (!kvm->arch.disabled_lapic_found) { in kvm_apic_disabled_lapic_found()
1108 kvm->arch.disabled_lapic_found = true; in kvm_apic_disabled_lapic_found()
1116 if (kvm->arch.x2apic_broadcast_quirk_disabled) { in kvm_apic_is_broadcast_dest()
1117 if ((irq->dest_id == APIC_BROADCAST && in kvm_apic_is_broadcast_dest()
1118 map->logical_mode != KVM_APIC_MODE_X2APIC)) in kvm_apic_is_broadcast_dest()
1120 if (irq->dest_id == X2APIC_BROADCAST) in kvm_apic_is_broadcast_dest()
1124 if (irq->dest_id == (x2apic_ipi ? in kvm_apic_is_broadcast_dest()
1146 if (irq->shorthand == APIC_DEST_SELF && src) { in kvm_apic_map_get_dest_lapic()
1150 } else if (irq->shorthand) in kvm_apic_map_get_dest_lapic()
1156 if (irq->dest_mode == APIC_DEST_PHYSICAL) { in kvm_apic_map_get_dest_lapic()
1157 if (irq->dest_id > map->max_apic_id) { in kvm_apic_map_get_dest_lapic()
1160 u32 dest_id = array_index_nospec(irq->dest_id, map->max_apic_id + 1); in kvm_apic_map_get_dest_lapic()
1161 *dst = &map->phys_map[dest_id]; in kvm_apic_map_get_dest_lapic()
1168 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst, in kvm_apic_map_get_dest_lapic()
1176 lowest = -1; in kvm_apic_map_get_dest_lapic()
1182 else if (kvm_apic_compare_prio((*dst)[i]->vcpu, in kvm_apic_map_get_dest_lapic()
1183 (*dst)[lowest]->vcpu) < 0) in kvm_apic_map_get_dest_lapic()
1190 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap), in kvm_apic_map_get_dest_lapic()
1214 *r = -1; in kvm_irq_delivery_to_apic_fast()
1216 if (irq->shorthand == APIC_DEST_SELF) { in kvm_irq_delivery_to_apic_fast()
1221 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map); in kvm_irq_delivery_to_apic_fast()
1226 map = rcu_dereference(kvm->arch.apic_map); in kvm_irq_delivery_to_apic_fast()
1234 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map); in kvm_irq_delivery_to_apic_fast()
1245 * - For single-destination interrupts, handle it in posted mode
1246 * - Else if vector hashing is enabled and it is a lowest-priority
1249 * 1. For lowest-priority interrupts, store all the possible
1252 * the right destination vCPU in the array for the lowest-priority
1254 * - Otherwise, use remapped mode to inject the interrupt.
1264 if (irq->shorthand) in kvm_intr_is_single_vcpu_fast()
1268 map = rcu_dereference(kvm->arch.apic_map); in kvm_intr_is_single_vcpu_fast()
1275 *dest_vcpu = dst[i]->vcpu; in kvm_intr_is_single_vcpu_fast()
1293 struct kvm_vcpu *vcpu = apic->vcpu; in __apic_accept_irq()
1295 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, in __apic_accept_irq()
1299 vcpu->arch.apic_arb_prio++; in __apic_accept_irq()
1312 __set_bit(vcpu->vcpu_id, dest_map->map); in __apic_accept_irq()
1313 dest_map->vectors[vcpu->vcpu_id] = vector; in __apic_accept_irq()
1316 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) { in __apic_accept_irq()
1319 apic->regs + APIC_TMR); in __apic_accept_irq()
1322 apic->regs + APIC_TMR); in __apic_accept_irq()
1331 vcpu->arch.pv.pv_unhalted = 1; in __apic_accept_irq()
1353 apic->pending_events = (1UL << KVM_APIC_INIT); in __apic_accept_irq()
1361 apic->sipi_vector = vector; in __apic_accept_irq()
1364 set_bit(KVM_APIC_SIPI, &apic->pending_events); in __apic_accept_irq()
1403 map = rcu_dereference(kvm->arch.apic_map); in kvm_bitmap_or_dest_vcpus()
1411 vcpu_idx = dest_vcpu[i]->vcpu->vcpu_idx; in kvm_bitmap_or_dest_vcpus()
1419 irq->shorthand, in kvm_bitmap_or_dest_vcpus()
1420 irq->dest_id, in kvm_bitmap_or_dest_vcpus()
1421 irq->dest_mode)) in kvm_bitmap_or_dest_vcpus()
1431 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; in kvm_apic_compare_prio()
1436 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors); in kvm_ioapic_handles_vector()
1448 if (irqchip_split(apic->vcpu->kvm)) { in kvm_ioapic_send_eoi()
1449 apic->vcpu->arch.pending_ioapic_eoi = vector; in kvm_ioapic_send_eoi()
1450 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu); in kvm_ioapic_send_eoi()
1454 if (apic_test_vector(vector, apic->regs + APIC_TMR)) in kvm_ioapic_send_eoi()
1459 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); in kvm_ioapic_send_eoi()
1472 if (vector == -1) in apic_set_eoi()
1478 if (to_hv_vcpu(apic->vcpu) && in apic_set_eoi()
1479 test_bit(vector, to_hv_synic(apic->vcpu)->vec_bitmap)) in apic_set_eoi()
1480 kvm_hv_synic_send_eoi(apic->vcpu, vector); in apic_set_eoi()
1483 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in apic_set_eoi()
1488 * this interface assumes a trap-like exit, which has already finished
1493 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_eoi_accelerated()
1498 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in kvm_apic_set_eoi_accelerated()
1523 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); in kvm_apic_send_ipi()
1536 apic->lapic_timer.period == 0) in apic_get_tmcct()
1540 remaining = ktime_sub(apic->lapic_timer.target_expiration, now); in apic_get_tmcct()
1544 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); in apic_get_tmcct()
1545 return div64_u64(ns, (APIC_BUS_CYCLE_NS * apic->divide_count)); in apic_get_tmcct()
1550 struct kvm_vcpu *vcpu = apic->vcpu; in __report_tpr_access()
1551 struct kvm_run *run = vcpu->run; in __report_tpr_access()
1554 run->tpr_access.rip = kvm_rip_read(vcpu); in __report_tpr_access()
1555 run->tpr_access.is_write = write; in __report_tpr_access()
1560 if (apic->vcpu->arch.tpr_access_reporting) in report_tpr_access()
1603 (APIC_REG_MASK(first) * ((1ull << (count)) - 1))
1607 /* Leave bits '0' for reserved and write-only registers. */ in kvm_lapic_readable_reg_mask()
1650 * WARN if KVM reads ICR in x2APIC mode, as it's an 8-byte register in in kvm_lapic_reg_read()
1682 return addr >= apic->base_address && in apic_mmio_in_range()
1683 addr < apic->base_address + LAPIC_MMIO_LENGTH; in apic_mmio_in_range()
1690 u32 offset = address - apic->base_address; in apic_mmio_read()
1693 return -EOPNOTSUPP; in apic_mmio_read()
1696 if (!kvm_check_has_quirk(vcpu->kvm, in apic_mmio_read()
1698 return -EOPNOTSUPP; in apic_mmio_read()
1716 apic->divide_count = 0x1 << (tmp2 & 0x7); in update_divide_count()
1726 if (apic_lvtt_period(apic) && apic->lapic_timer.period) { in limit_periodic_timer_frequency()
1729 if (apic->lapic_timer.period < min_period) { in limit_periodic_timer_frequency()
1733 apic->vcpu->vcpu_id, in limit_periodic_timer_frequency()
1734 apic->lapic_timer.period, min_period); in limit_periodic_timer_frequency()
1735 apic->lapic_timer.period = min_period; in limit_periodic_timer_frequency()
1744 hrtimer_cancel(&apic->lapic_timer.timer); in cancel_apic_timer()
1746 if (apic->lapic_timer.hv_timer_in_use) in cancel_apic_timer()
1749 atomic_set(&apic->lapic_timer.pending, 0); in cancel_apic_timer()
1755 apic->lapic_timer.timer_mode_mask; in apic_update_lvtt()
1757 if (apic->lapic_timer.timer_mode != timer_mode) { in apic_update_lvtt()
1762 apic->lapic_timer.period = 0; in apic_update_lvtt()
1763 apic->lapic_timer.tscdeadline = 0; in apic_update_lvtt()
1765 apic->lapic_timer.timer_mode = timer_mode; in apic_update_lvtt()
1772 * during a higher-priority task.
1777 struct kvm_lapic *apic = vcpu->arch.apic; in lapic_timer_int_injected()
1782 void *bitmap = apic->regs + APIC_ISR; in lapic_timer_int_injected()
1784 if (apic->apicv_active) in lapic_timer_int_injected()
1785 bitmap = apic->regs + APIC_IRR; in lapic_timer_int_injected()
1795 u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns; in __wait_lapic_expire()
1803 if (vcpu->arch.tsc_scaling_ratio == kvm_caps.default_tsc_scaling_ratio) { in __wait_lapic_expire()
1808 do_div(delay_ns, vcpu->arch.virtual_tsc_khz); in __wait_lapic_expire()
1816 struct kvm_lapic *apic = vcpu->arch.apic; in adjust_lapic_timer_advance()
1817 u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns; in adjust_lapic_timer_advance()
1827 ns = -advance_expire_delta * 1000000ULL; in adjust_lapic_timer_advance()
1828 do_div(ns, vcpu->arch.virtual_tsc_khz); in adjust_lapic_timer_advance()
1829 timer_advance_ns -= ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP; in adjust_lapic_timer_advance()
1833 do_div(ns, vcpu->arch.virtual_tsc_khz); in adjust_lapic_timer_advance()
1839 apic->lapic_timer.timer_advance_ns = timer_advance_ns; in adjust_lapic_timer_advance()
1844 struct kvm_lapic *apic = vcpu->arch.apic; in __kvm_wait_lapic_expire()
1847 tsc_deadline = apic->lapic_timer.expired_tscdeadline; in __kvm_wait_lapic_expire()
1848 apic->lapic_timer.expired_tscdeadline = 0; in __kvm_wait_lapic_expire()
1850 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline); in __kvm_wait_lapic_expire()
1853 adjust_lapic_timer_advance(vcpu, guest_tsc - tsc_deadline); in __kvm_wait_lapic_expire()
1864 __wait_lapic_expire(vcpu, tsc_deadline - guest_tsc); in __kvm_wait_lapic_expire()
1870 vcpu->arch.apic->lapic_timer.expired_tscdeadline && in kvm_wait_lapic_expire()
1871 vcpu->arch.apic->lapic_timer.timer_advance_ns && in kvm_wait_lapic_expire()
1879 struct kvm_timer *ktimer = &apic->lapic_timer; in kvm_apic_inject_pending_timer_irqs()
1883 ktimer->tscdeadline = 0; in kvm_apic_inject_pending_timer_irqs()
1885 ktimer->tscdeadline = 0; in kvm_apic_inject_pending_timer_irqs()
1886 ktimer->target_expiration = 0; in kvm_apic_inject_pending_timer_irqs()
1892 struct kvm_vcpu *vcpu = apic->vcpu; in apic_timer_expired()
1893 struct kvm_timer *ktimer = &apic->lapic_timer; in apic_timer_expired()
1895 if (atomic_read(&apic->lapic_timer.pending)) in apic_timer_expired()
1898 if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use) in apic_timer_expired()
1899 ktimer->expired_tscdeadline = ktimer->tscdeadline; in apic_timer_expired()
1901 if (!from_timer_fn && apic->apicv_active) { in apic_timer_expired()
1907 if (kvm_use_posted_timer_interrupt(apic->vcpu)) { in apic_timer_expired()
1915 if (vcpu->arch.apic->lapic_timer.expired_tscdeadline && in apic_timer_expired()
1916 vcpu->arch.apic->lapic_timer.timer_advance_ns) in apic_timer_expired()
1922 atomic_inc(&apic->lapic_timer.pending); in apic_timer_expired()
1930 struct kvm_timer *ktimer = &apic->lapic_timer; in start_sw_tscdeadline()
1931 u64 guest_tsc, tscdeadline = ktimer->tscdeadline; in start_sw_tscdeadline()
1934 struct kvm_vcpu *vcpu = apic->vcpu; in start_sw_tscdeadline()
1935 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; in start_sw_tscdeadline()
1947 ns = (tscdeadline - guest_tsc) * 1000000ULL; in start_sw_tscdeadline()
1951 likely(ns > apic->lapic_timer.timer_advance_ns)) { in start_sw_tscdeadline()
1953 expire = ktime_sub_ns(expire, ktimer->timer_advance_ns); in start_sw_tscdeadline()
1954 hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS_HARD); in start_sw_tscdeadline()
1963 return (u64)tmict * APIC_BUS_CYCLE_NS * (u64)apic->divide_count; in tmict_to_ns()
1971 apic->lapic_timer.period = in update_target_expiration()
1976 remaining = ktime_sub(apic->lapic_timer.target_expiration, now); in update_target_expiration()
1982 apic->divide_count, old_divisor); in update_target_expiration()
1984 apic->lapic_timer.tscdeadline += in update_target_expiration()
1985 nsec_to_cycles(apic->vcpu, ns_remaining_new) - in update_target_expiration()
1986 nsec_to_cycles(apic->vcpu, ns_remaining_old); in update_target_expiration()
1987 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new); in update_target_expiration()
1997 apic->lapic_timer.period = in set_target_expiration()
2000 if (!apic->lapic_timer.period) { in set_target_expiration()
2001 apic->lapic_timer.tscdeadline = 0; in set_target_expiration()
2006 deadline = apic->lapic_timer.period; in set_target_expiration()
2014 deadline = apic->lapic_timer.period; in set_target_expiration()
2018 else if (unlikely(deadline > apic->lapic_timer.period)) { in set_target_expiration()
2023 apic->vcpu->vcpu_id, in set_target_expiration()
2026 deadline, apic->lapic_timer.period); in set_target_expiration()
2028 deadline = apic->lapic_timer.period; in set_target_expiration()
2033 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + in set_target_expiration()
2034 nsec_to_cycles(apic->vcpu, deadline); in set_target_expiration()
2035 apic->lapic_timer.target_expiration = ktime_add_ns(now, deadline); in set_target_expiration()
2053 apic->lapic_timer.target_expiration = in advance_periodic_target_expiration()
2054 ktime_add_ns(apic->lapic_timer.target_expiration, in advance_periodic_target_expiration()
2055 apic->lapic_timer.period); in advance_periodic_target_expiration()
2056 delta = ktime_sub(apic->lapic_timer.target_expiration, now); in advance_periodic_target_expiration()
2057 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + in advance_periodic_target_expiration()
2058 nsec_to_cycles(apic->vcpu, delta); in advance_periodic_target_expiration()
2063 if (!apic->lapic_timer.period) in start_sw_period()
2067 apic->lapic_timer.target_expiration)) { in start_sw_period()
2076 hrtimer_start(&apic->lapic_timer.timer, in start_sw_period()
2077 apic->lapic_timer.target_expiration, in start_sw_period()
2086 return vcpu->arch.apic->lapic_timer.hv_timer_in_use; in kvm_lapic_hv_timer_in_use()
2092 WARN_ON(!apic->lapic_timer.hv_timer_in_use); in cancel_hv_timer()
2093 static_call(kvm_x86_cancel_hv_timer)(apic->vcpu); in cancel_hv_timer()
2094 apic->lapic_timer.hv_timer_in_use = false; in cancel_hv_timer()
2099 struct kvm_timer *ktimer = &apic->lapic_timer; in start_hv_timer()
2100 struct kvm_vcpu *vcpu = apic->vcpu; in start_hv_timer()
2107 if (!ktimer->tscdeadline) in start_hv_timer()
2110 if (static_call(kvm_x86_set_hv_timer)(vcpu, ktimer->tscdeadline, &expired)) in start_hv_timer()
2113 ktimer->hv_timer_in_use = true; in start_hv_timer()
2114 hrtimer_cancel(&ktimer->timer); in start_hv_timer()
2119 * VM-Exit to recompute the periodic timer's target expiration. in start_hv_timer()
2126 if (atomic_read(&ktimer->pending)) { in start_hv_timer()
2134 trace_kvm_hv_timer_state(vcpu->vcpu_id, ktimer->hv_timer_in_use); in start_hv_timer()
2141 struct kvm_timer *ktimer = &apic->lapic_timer; in start_sw_timer()
2144 if (apic->lapic_timer.hv_timer_in_use) in start_sw_timer()
2146 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending)) in start_sw_timer()
2153 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false); in start_sw_timer()
2160 if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending)) in restart_apic_timer()
2171 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_expired_hv_timer()
2175 if (!apic->lapic_timer.hv_timer_in_use) in kvm_lapic_expired_hv_timer()
2181 if (apic_lvtt_period(apic) && apic->lapic_timer.period) { in kvm_lapic_expired_hv_timer()
2192 restart_apic_timer(vcpu->arch.apic); in kvm_lapic_switch_to_hv_timer()
2197 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_switch_to_sw_timer()
2201 if (apic->lapic_timer.hv_timer_in_use) in kvm_lapic_switch_to_sw_timer()
2208 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_restart_hv_timer()
2210 WARN_ON(!apic->lapic_timer.hv_timer_in_use); in kvm_lapic_restart_hv_timer()
2216 atomic_set(&apic->lapic_timer.pending, 0); in __start_apic_timer()
2234 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { in apic_manage_nmi_watchdog()
2235 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; in apic_manage_nmi_watchdog()
2237 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); in apic_manage_nmi_watchdog()
2239 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); in apic_manage_nmi_watchdog()
2248 return -1; in get_lvt_index()
2250 (reg - APIC_LVTT) >> 4, KVM_APIC_MAX_NR_LVT_ENTRIES); in get_lvt_index()
2299 for (i = 0; i < apic->nr_lvt_entries; i++) { in kvm_lapic_reg_write()
2304 atomic_set(&apic->lapic_timer.pending, 0); in kvm_lapic_reg_write()
2347 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); in kvm_lapic_reg_write()
2362 uint32_t old_divisor = apic->divide_count; in kvm_lapic_reg_write()
2366 if (apic->divide_count != old_divisor && in kvm_lapic_reg_write()
2367 apic->lapic_timer.period) { in kvm_lapic_reg_write()
2368 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_lapic_reg_write()
2381 * Self-IPI exists only when x2APIC is enabled. Bits 7:0 hold in kvm_lapic_reg_write()
2382 * the vector, everything else is reserved. in kvm_lapic_reg_write()
2399 kvm_recalculate_apic_map(apic->vcpu->kvm); in kvm_lapic_reg_write()
2408 unsigned int offset = address - apic->base_address; in apic_mmio_write()
2412 return -EOPNOTSUPP; in apic_mmio_write()
2415 if (!kvm_check_has_quirk(vcpu->kvm, in apic_mmio_write()
2417 return -EOPNOTSUPP; in apic_mmio_write()
2423 * APIC register must be aligned on 128-bits boundary. in apic_mmio_write()
2439 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0); in kvm_lapic_set_eoi()
2446 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_write_nodecode()
2449 * ICR is a single 64-bit register when x2APIC is enabled, all others in kvm_apic_write_nodecode()
2450 * registers hold 32-bit values. For legacy xAPIC, ICR writes need to in kvm_apic_write_nodecode()
2457 * maybe-unecessary write, and both are in the noise anyways. in kvm_apic_write_nodecode()
2468 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_free_lapic()
2470 if (!vcpu->arch.apic) in kvm_free_lapic()
2473 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_free_lapic()
2475 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) in kvm_free_lapic()
2478 if (!apic->sw_enabled) in kvm_free_lapic()
2481 if (apic->regs) in kvm_free_lapic()
2482 free_page((unsigned long)apic->regs); in kvm_free_lapic()
2488 *----------------------------------------------------------------------
2490 *----------------------------------------------------------------------
2494 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_get_lapic_tscdeadline_msr()
2499 return apic->lapic_timer.tscdeadline; in kvm_get_lapic_tscdeadline_msr()
2504 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_set_lapic_tscdeadline_msr()
2509 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_set_lapic_tscdeadline_msr()
2510 apic->lapic_timer.tscdeadline = data; in kvm_set_lapic_tscdeadline_msr()
2516 apic_set_tpr(vcpu->arch.apic, (cr8 & 0x0f) << 4); in kvm_lapic_set_tpr()
2523 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI); in kvm_lapic_get_cr8()
2530 u64 old_value = vcpu->arch.apic_base; in kvm_lapic_set_base()
2531 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_set_base()
2533 vcpu->arch.apic_base = value; in kvm_lapic_set_base()
2544 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); in kvm_lapic_set_base()
2550 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_lapic_set_base()
2556 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); in kvm_lapic_set_base()
2558 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); in kvm_lapic_set_base()
2566 apic->base_address = apic->vcpu->arch.apic_base & in kvm_lapic_set_base()
2570 apic->base_address != APIC_DEFAULT_PHYS_BASE) { in kvm_lapic_set_base()
2571 kvm_set_apicv_inhibit(apic->vcpu->kvm, in kvm_lapic_set_base()
2578 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_update_apicv()
2580 if (apic->apicv_active) { in kvm_apic_update_apicv()
2582 apic->irr_pending = true; in kvm_apic_update_apicv()
2583 apic->isr_count = 1; in kvm_apic_update_apicv()
2591 apic->isr_count = count_vectors(apic->regs + APIC_ISR); in kvm_apic_update_apicv()
2593 apic->highest_isr_cache = -1; in kvm_apic_update_apicv()
2602 mutex_lock(&kvm->slots_lock); in kvm_alloc_apic_access_page()
2603 if (kvm->arch.apic_access_memslot_enabled || in kvm_alloc_apic_access_page()
2604 kvm->arch.apic_access_memslot_inhibited) in kvm_alloc_apic_access_page()
2616 ret = -EFAULT; in kvm_alloc_apic_access_page()
2621 * Do not pin the page in memory, so that memory hot-unplug in kvm_alloc_apic_access_page()
2625 kvm->arch.apic_access_memslot_enabled = true; in kvm_alloc_apic_access_page()
2627 mutex_unlock(&kvm->slots_lock); in kvm_alloc_apic_access_page()
2634 struct kvm *kvm = vcpu->kvm; in kvm_inhibit_apic_access_page()
2636 if (!kvm->arch.apic_access_memslot_enabled) in kvm_inhibit_apic_access_page()
2641 mutex_lock(&kvm->slots_lock); in kvm_inhibit_apic_access_page()
2643 if (kvm->arch.apic_access_memslot_enabled) { in kvm_inhibit_apic_access_page()
2653 kvm->arch.apic_access_memslot_enabled = false; in kvm_inhibit_apic_access_page()
2659 kvm->arch.apic_access_memslot_inhibited = true; in kvm_inhibit_apic_access_page()
2662 mutex_unlock(&kvm->slots_lock); in kvm_inhibit_apic_access_page()
2669 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_reset()
2686 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_lapic_reset()
2690 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); in kvm_lapic_reset()
2691 kvm_apic_set_version(apic->vcpu); in kvm_lapic_reset()
2693 for (i = 0; i < apic->nr_lvt_entries; i++) in kvm_lapic_reset()
2697 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED)) in kvm_lapic_reset()
2723 atomic_set(&apic->lapic_timer.pending, 0); in kvm_lapic_reset()
2725 vcpu->arch.pv_eoi.msr_val = 0; in kvm_lapic_reset()
2727 if (apic->apicv_active) { in kvm_lapic_reset()
2729 static_call_cond(kvm_x86_hwapic_irr_update)(vcpu, -1); in kvm_lapic_reset()
2730 static_call_cond(kvm_x86_hwapic_isr_update)(-1); in kvm_lapic_reset()
2733 vcpu->arch.apic_arb_prio = 0; in kvm_lapic_reset()
2734 vcpu->arch.apic_attention = 0; in kvm_lapic_reset()
2736 kvm_recalculate_apic_map(vcpu->kvm); in kvm_lapic_reset()
2740 *----------------------------------------------------------------------
2742 *----------------------------------------------------------------------
2752 struct kvm_lapic *apic = vcpu->arch.apic; in apic_has_pending_timer()
2755 return atomic_read(&apic->lapic_timer.pending); in apic_has_pending_timer()
2781 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_nmi_wd_deliver()
2801 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); in apic_timer_fn()
2817 vcpu->arch.apic = apic; in kvm_create_lapic()
2819 apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); in kvm_create_lapic()
2820 if (!apic->regs) { in kvm_create_lapic()
2822 vcpu->vcpu_id); in kvm_create_lapic()
2825 apic->vcpu = vcpu; in kvm_create_lapic()
2827 apic->nr_lvt_entries = kvm_apic_calc_nr_lvt_entries(vcpu); in kvm_create_lapic()
2829 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, in kvm_create_lapic()
2831 apic->lapic_timer.timer.function = apic_timer_fn; in kvm_create_lapic()
2832 if (timer_advance_ns == -1) { in kvm_create_lapic()
2833 apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT; in kvm_create_lapic()
2836 apic->lapic_timer.timer_advance_ns = timer_advance_ns; in kvm_create_lapic()
2844 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; in kvm_create_lapic()
2846 kvm_iodevice_init(&apic->dev, &apic_mmio_ops); in kvm_create_lapic()
2851 vcpu->arch.apic = NULL; in kvm_create_lapic()
2853 return -ENOMEM; in kvm_create_lapic()
2858 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_has_interrupt()
2862 return -1; in kvm_apic_has_interrupt()
2871 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0); in kvm_apic_accept_pic_intr()
2873 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) in kvm_apic_accept_pic_intr()
2883 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_inject_apic_timer_irqs()
2885 if (atomic_read(&apic->lapic_timer.pending) > 0) { in kvm_inject_apic_timer_irqs()
2887 atomic_set(&apic->lapic_timer.pending, 0); in kvm_inject_apic_timer_irqs()
2894 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_get_apic_interrupt()
2897 if (vector == -1) in kvm_get_apic_interrupt()
2898 return -1; in kvm_get_apic_interrupt()
2908 if (to_hv_vcpu(vcpu) && test_bit(vector, to_hv_synic(vcpu)->auto_eoi_bitmap)) { in kvm_get_apic_interrupt()
2910 * For auto-EOI interrupts, there might be another pending in kvm_get_apic_interrupt()
2918 * be a higher-priority pending interrupt---except if there was in kvm_get_apic_interrupt()
2932 if (apic_x2apic_mode(vcpu->arch.apic)) { in kvm_apic_state_fixup()
2933 u32 *id = (u32 *)(s->regs + APIC_ID); in kvm_apic_state_fixup()
2934 u32 *ldr = (u32 *)(s->regs + APIC_LDR); in kvm_apic_state_fixup()
2937 if (vcpu->kvm->arch.x2apic_format) { in kvm_apic_state_fixup()
2938 if (*id != vcpu->vcpu_id) in kvm_apic_state_fixup()
2939 return -EINVAL; in kvm_apic_state_fixup()
2949 * ICR is internally a single 64-bit register, but needs to be in kvm_apic_state_fixup()
2955 icr = __kvm_lapic_get_reg(s->regs, APIC_ICR) | in kvm_apic_state_fixup()
2956 (u64)__kvm_lapic_get_reg(s->regs, APIC_ICR2) << 32; in kvm_apic_state_fixup()
2957 __kvm_lapic_set_reg64(s->regs, APIC_ICR, icr); in kvm_apic_state_fixup()
2959 icr = __kvm_lapic_get_reg64(s->regs, APIC_ICR); in kvm_apic_state_fixup()
2960 __kvm_lapic_set_reg(s->regs, APIC_ICR2, icr >> 32); in kvm_apic_state_fixup()
2969 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s)); in kvm_apic_get_state()
2975 __kvm_lapic_set_reg(s->regs, APIC_TMCCT, in kvm_apic_get_state()
2976 __apic_read(vcpu->arch.apic, APIC_TMCCT)); in kvm_apic_get_state()
2983 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_state()
2988 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); in kvm_apic_set_state()
2990 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); in kvm_apic_set_state()
2994 kvm_recalculate_apic_map(vcpu->kvm); in kvm_apic_set_state()
2997 memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s)); in kvm_apic_set_state()
2999 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_state()
3000 kvm_recalculate_apic_map(vcpu->kvm); in kvm_apic_set_state()
3005 apic->lapic_timer.expired_tscdeadline = 0; in kvm_apic_set_state()
3012 if (apic->apicv_active) { in kvm_apic_set_state()
3018 if (ioapic_in_kernel(vcpu->kvm)) in kvm_apic_set_state()
3021 vcpu->arch.apic_arb_prio = 0; in kvm_apic_set_state()
3034 timer = &vcpu->arch.apic->lapic_timer.timer; in __kvm_migrate_apic_timer()
3040 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
3055 * -> host disabled PV EOI. in apic_sync_pv_eoi_from_guest()
3057 * -> host enabled PV EOI, guest did not execute EOI yet. in apic_sync_pv_eoi_from_guest()
3059 * -> host enabled PV EOI, guest executed EOI. in apic_sync_pv_eoi_from_guest()
3073 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) in kvm_lapic_sync_from_vapic()
3074 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); in kvm_lapic_sync_from_vapic()
3076 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) in kvm_lapic_sync_from_vapic()
3079 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, in kvm_lapic_sync_from_vapic()
3083 apic_set_tpr(vcpu->arch.apic, data & 0xff); in kvm_lapic_sync_from_vapic()
3087 * apic_sync_pv_eoi_to_guest - called before vmentry
3097 apic->irr_pending || in apic_sync_pv_eoi_to_guest()
3099 apic->highest_isr_cache == -1 || in apic_sync_pv_eoi_to_guest()
3101 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) { in apic_sync_pv_eoi_to_guest()
3109 pv_eoi_set_pending(apic->vcpu); in apic_sync_pv_eoi_to_guest()
3116 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_sync_to_vapic()
3120 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) in kvm_lapic_sync_to_vapic()
3132 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, in kvm_lapic_sync_to_vapic()
3139 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, in kvm_lapic_set_vapic_addr()
3140 &vcpu->arch.apic->vapic_cache, in kvm_lapic_set_vapic_addr()
3142 return -EINVAL; in kvm_lapic_set_vapic_addr()
3143 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); in kvm_lapic_set_vapic_addr()
3145 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); in kvm_lapic_set_vapic_addr()
3148 vcpu->arch.apic->vapic_addr = vapic_addr; in kvm_lapic_set_vapic_addr()
3182 * ICR is a 64-bit register in x2APIC mode (and Hyper-V PV vAPIC) and in kvm_lapic_msr_write()
3184 * through 32-bit reads/writes. in kvm_lapic_msr_write()
3189 /* Bits 63:32 are reserved in all other registers. */ in kvm_lapic_msr_write()
3198 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_x2apic_msr_write()
3199 u32 reg = (msr - APIC_BASE_MSR) << 4; in kvm_x2apic_msr_write()
3209 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_x2apic_msr_read()
3210 u32 reg = (msr - APIC_BASE_MSR) << 4; in kvm_x2apic_msr_read()
3223 return kvm_lapic_msr_write(vcpu->arch.apic, reg, data); in kvm_hv_vapic_msr_write()
3231 return kvm_lapic_msr_read(vcpu->arch.apic, reg, data); in kvm_hv_vapic_msr_read()
3237 struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data; in kvm_lapic_set_pv_eoi()
3245 if (addr == ghc->gpa && len <= ghc->len) in kvm_lapic_set_pv_eoi()
3246 new_len = ghc->len; in kvm_lapic_set_pv_eoi()
3250 ret = kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len); in kvm_lapic_set_pv_eoi()
3255 vcpu->arch.pv_eoi.msr_val = data; in kvm_lapic_set_pv_eoi()
3262 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_accept_events()
3272 return r == -EBUSY ? 0 : r; in kvm_apic_accept_events()
3274 * Continue processing INIT/SIPI even if a nested VM-Exit in kvm_apic_accept_events()
3283 * wait-for-SIPI (WFS). in kvm_apic_accept_events()
3286 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED); in kvm_apic_accept_events()
3287 clear_bit(KVM_APIC_SIPI, &apic->pending_events); in kvm_apic_accept_events()
3291 if (test_and_clear_bit(KVM_APIC_INIT, &apic->pending_events)) { in kvm_apic_accept_events()
3293 if (kvm_vcpu_is_bsp(apic->vcpu)) in kvm_apic_accept_events()
3294 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; in kvm_apic_accept_events()
3296 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; in kvm_apic_accept_events()
3298 if (test_and_clear_bit(KVM_APIC_SIPI, &apic->pending_events)) { in kvm_apic_accept_events()
3299 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { in kvm_apic_accept_events()
3302 sipi_vector = apic->sipi_vector; in kvm_apic_accept_events()
3304 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; in kvm_apic_accept_events()