Lines Matching +full:chip +full:- +full:enable +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2006-2007 David Brownell
22 #include <linux/platform_data/gpio-davinci.h>
45 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
52 struct davinci_gpio_controller *chip; member
57 struct gpio_chip chip; member
84 /*--------------------------------------------------------------------------*/
86 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
87 static inline int __davinci_direction(struct gpio_chip *chip, in __davinci_direction() argument
90 struct davinci_gpio_controller *d = gpiochip_get_data(chip); in __davinci_direction()
97 g = d->regs[bank]; in __davinci_direction()
98 spin_lock_irqsave(&d->lock, flags); in __davinci_direction()
99 temp = readl_relaxed(&g->dir); in __davinci_direction()
102 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction()
106 writel_relaxed(temp, &g->dir); in __davinci_direction()
107 spin_unlock_irqrestore(&d->lock, flags); in __davinci_direction()
112 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) in davinci_direction_in() argument
114 return __davinci_direction(chip, offset, false, 0); in davinci_direction_in()
118 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) in davinci_direction_out() argument
120 return __davinci_direction(chip, offset, true, value); in davinci_direction_out()
130 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) in davinci_gpio_get() argument
132 struct davinci_gpio_controller *d = gpiochip_get_data(chip); in davinci_gpio_get()
136 g = d->regs[bank]; in davinci_gpio_get()
138 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); in davinci_gpio_get()
145 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) in davinci_gpio_set() argument
147 struct davinci_gpio_controller *d = gpiochip_get_data(chip); in davinci_gpio_set()
151 g = d->regs[bank]; in davinci_gpio_set()
154 value ? &g->set_data : &g->clr_data); in davinci_gpio_set()
160 struct device_node *dn = pdev->dev.of_node; in davinci_gpio_get_pdata()
165 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) in davinci_gpio_get_pdata()
166 return dev_get_platdata(&pdev->dev); in davinci_gpio_get_pdata()
168 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); in davinci_gpio_get_pdata()
176 pdata->ngpio = val; in davinci_gpio_get_pdata()
178 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); in davinci_gpio_get_pdata()
182 pdata->gpio_unbanked = val; in davinci_gpio_get_pdata()
187 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret); in davinci_gpio_get_pdata()
197 struct device *dev = &pdev->dev; in davinci_gpio_probe()
202 return -EINVAL; in davinci_gpio_probe()
205 dev->platform_data = pdata; in davinci_gpio_probe()
209 * and "ngpio" is one more than the largest zero-based in davinci_gpio_probe()
212 ngpio = pdata->ngpio; in davinci_gpio_probe()
214 dev_err(dev, "How many GPIOs?\n"); in davinci_gpio_probe()
215 return -EINVAL; in davinci_gpio_probe()
220 * interrupts is equal to number of gpios else all are banked so in davinci_gpio_probe()
221 * number of interrupts is equal to number of banks(each with 16 gpios) in davinci_gpio_probe()
223 if (pdata->gpio_unbanked) in davinci_gpio_probe()
224 nirq = pdata->gpio_unbanked; in davinci_gpio_probe()
230 return -ENOMEM; in davinci_gpio_probe()
237 chips->irqs[i] = platform_get_irq(pdev, i); in davinci_gpio_probe()
238 if (chips->irqs[i] < 0) in davinci_gpio_probe()
239 return chips->irqs[i]; in davinci_gpio_probe()
242 chips->chip.label = dev_name(dev); in davinci_gpio_probe()
244 chips->chip.direction_input = davinci_direction_in; in davinci_gpio_probe()
245 chips->chip.get = davinci_gpio_get; in davinci_gpio_probe()
246 chips->chip.direction_output = davinci_direction_out; in davinci_gpio_probe()
247 chips->chip.set = davinci_gpio_set; in davinci_gpio_probe()
249 chips->chip.ngpio = ngpio; in davinci_gpio_probe()
250 chips->chip.base = pdata->no_auto_base ? pdata->base : -1; in davinci_gpio_probe()
253 chips->chip.parent = dev; in davinci_gpio_probe()
254 chips->chip.request = gpiochip_generic_request; in davinci_gpio_probe()
255 chips->chip.free = gpiochip_generic_free; in davinci_gpio_probe()
257 spin_lock_init(&chips->lock); in davinci_gpio_probe()
261 chips->regs[bank] = gpio_base + offset_array[bank]; in davinci_gpio_probe()
263 ret = devm_gpiochip_add_data(dev, &chips->chip, chips); in davinci_gpio_probe()
275 /*--------------------------------------------------------------------------*/
280 * NOTE: The first few GPIOs also have direct INTC hookups in addition
292 writel_relaxed(mask, &g->clr_falling); in gpio_irq_disable()
293 writel_relaxed(mask, &g->clr_rising); in gpio_irq_disable()
307 writel_relaxed(mask, &g->set_falling); in gpio_irq_enable()
309 writel_relaxed(mask, &g->set_rising); in gpio_irq_enable()
315 return -EINVAL; in gpio_irq_type()
337 bank_num = irqdata->bank_num; in gpio_irq_handler()
338 g = irqdata->regs; in gpio_irq_handler()
339 d = irqdata->chip; in gpio_irq_handler()
353 status = readl_relaxed(&g->intstat) & mask; in gpio_irq_handler()
356 writel_relaxed(status, &g->intstat); in gpio_irq_handler()
363 /* Max number of gpios per controller is 144 so in gpio_irq_handler()
368 generic_handle_domain_irq(d->irq_domain, hw_irq); in gpio_irq_handler()
372 /* now it may re-trigger */ in gpio_irq_handler()
375 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) in gpio_to_irq_banked() argument
377 struct davinci_gpio_controller *d = gpiochip_get_data(chip); in gpio_to_irq_banked()
379 if (d->irq_domain) in gpio_to_irq_banked()
380 return irq_create_mapping(d->irq_domain, offset); in gpio_to_irq_banked()
382 return -ENXIO; in gpio_to_irq_banked()
385 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) in gpio_to_irq_unbanked() argument
387 struct davinci_gpio_controller *d = gpiochip_get_data(chip); in gpio_to_irq_unbanked()
391 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). in gpio_to_irq_unbanked()
393 if (offset < d->gpio_unbanked) in gpio_to_irq_unbanked()
394 return d->irqs[offset]; in gpio_to_irq_unbanked()
396 return -ENODEV; in gpio_to_irq_unbanked()
406 g = (struct davinci_gpio_regs __iomem *)d->regs[0]; in gpio_irq_type_unbanked()
408 if (data->irq == d->irqs[i]) in gpio_irq_type_unbanked()
412 return -EINVAL; in gpio_irq_type_unbanked()
417 return -EINVAL; in gpio_irq_type_unbanked()
420 ? &g->set_falling : &g->clr_falling); in gpio_irq_type_unbanked()
422 ? &g->set_rising : &g->clr_rising); in gpio_irq_type_unbanked()
432 (struct davinci_gpio_controller *)d->host_data; in davinci_gpio_irq_map()
433 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32]; in davinci_gpio_irq_map()
455 return &gpio_unbanked.chip; in davinci_gpio_get_irq_chip()
471 * calls ... so if no gpios are wakeup events the clock can be disabled,
484 struct device *dev = &pdev->dev; in davinci_gpio_irq_setup()
486 struct davinci_gpio_platform_data *pdata = dev->platform_data; in davinci_gpio_irq_setup()
501 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data; in davinci_gpio_irq_setup()
503 ngpio = pdata->ngpio; in davinci_gpio_irq_setup()
515 if (!pdata->gpio_unbanked) { in davinci_gpio_irq_setup()
516 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0); in davinci_gpio_irq_setup()
523 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0, in davinci_gpio_irq_setup()
529 return -ENODEV; in davinci_gpio_irq_setup()
535 * banked IRQs. Having GPIOs in the first GPIO bank use direct in davinci_gpio_irq_setup()
539 chips->chip.to_irq = gpio_to_irq_banked; in davinci_gpio_irq_setup()
540 chips->irq_domain = irq_domain; in davinci_gpio_irq_setup()
543 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO in davinci_gpio_irq_setup()
545 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. in davinci_gpio_irq_setup()
547 if (pdata->gpio_unbanked) { in davinci_gpio_irq_setup()
549 chips->chip.to_irq = gpio_to_irq_unbanked; in davinci_gpio_irq_setup()
550 chips->gpio_unbanked = pdata->gpio_unbanked; in davinci_gpio_irq_setup()
551 binten = GENMASK(pdata->gpio_unbanked / 16, 0); in davinci_gpio_irq_setup()
554 irq = chips->irqs[0]; in davinci_gpio_irq_setup()
556 irq_chip->name = "GPIO-AINTC"; in davinci_gpio_irq_setup()
557 irq_chip->irq_set_type = gpio_irq_type_unbanked; in davinci_gpio_irq_setup()
560 g = chips->regs[0]; in davinci_gpio_irq_setup()
561 writel_relaxed(~0, &g->set_falling); in davinci_gpio_irq_setup()
562 writel_relaxed(~0, &g->set_rising); in davinci_gpio_irq_setup()
565 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) { in davinci_gpio_irq_setup()
566 irq_set_chip(chips->irqs[gpio], irq_chip); in davinci_gpio_irq_setup()
567 irq_set_handler_data(chips->irqs[gpio], chips); in davinci_gpio_irq_setup()
568 irq_set_status_flags(chips->irqs[gpio], in davinci_gpio_irq_setup()
581 * There are register sets for 32 GPIOs. 2 banks of 16 in davinci_gpio_irq_setup()
582 * GPIOs are covered by each set of registers hence divide by 2 in davinci_gpio_irq_setup()
584 g = chips->regs[bank / 2]; in davinci_gpio_irq_setup()
585 writel_relaxed(~0, &g->clr_falling); in davinci_gpio_irq_setup()
586 writel_relaxed(~0, &g->clr_rising); in davinci_gpio_irq_setup()
589 * Each chip handles 32 gpios, and each irq bank consists of 16 in davinci_gpio_irq_setup()
593 irqdata = devm_kzalloc(&pdev->dev, in davinci_gpio_irq_setup()
599 return -ENOMEM; in davinci_gpio_irq_setup()
602 irqdata->regs = g; in davinci_gpio_irq_setup()
603 irqdata->bank_num = bank; in davinci_gpio_irq_setup()
604 irqdata->chip = chips; in davinci_gpio_irq_setup()
606 irq_set_chained_handler_and_data(chips->irqs[bank], in davinci_gpio_irq_setup()
614 * BINTEN -- per-bank interrupt enable. genirq would also let these in davinci_gpio_irq_setup()
630 base = chips->regs[0] - offset_array[0]; in davinci_gpio_save_context()
631 chips->binten_context = readl_relaxed(base + BINTEN); in davinci_gpio_save_context()
634 g = chips->regs[bank]; in davinci_gpio_save_context()
635 context = &chips->context[bank]; in davinci_gpio_save_context()
636 context->dir = readl_relaxed(&g->dir); in davinci_gpio_save_context()
637 context->set_data = readl_relaxed(&g->set_data); in davinci_gpio_save_context()
638 context->set_rising = readl_relaxed(&g->set_rising); in davinci_gpio_save_context()
639 context->set_falling = readl_relaxed(&g->set_falling); in davinci_gpio_save_context()
643 writel_relaxed(GENMASK(31, 0), &g->intstat); in davinci_gpio_save_context()
654 base = chips->regs[0] - offset_array[0]; in davinci_gpio_restore_context()
656 if (readl_relaxed(base + BINTEN) != chips->binten_context) in davinci_gpio_restore_context()
657 writel_relaxed(chips->binten_context, base + BINTEN); in davinci_gpio_restore_context()
660 g = chips->regs[bank]; in davinci_gpio_restore_context()
661 context = &chips->context[bank]; in davinci_gpio_restore_context()
662 if (readl_relaxed(&g->dir) != context->dir) in davinci_gpio_restore_context()
663 writel_relaxed(context->dir, &g->dir); in davinci_gpio_restore_context()
664 if (readl_relaxed(&g->set_data) != context->set_data) in davinci_gpio_restore_context()
665 writel_relaxed(context->set_data, &g->set_data); in davinci_gpio_restore_context()
666 if (readl_relaxed(&g->set_rising) != context->set_rising) in davinci_gpio_restore_context()
667 writel_relaxed(context->set_rising, &g->set_rising); in davinci_gpio_restore_context()
668 if (readl_relaxed(&g->set_falling) != context->set_falling) in davinci_gpio_restore_context()
669 writel_relaxed(context->set_falling, &g->set_falling); in davinci_gpio_restore_context()
677 u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32); in davinci_gpio_suspend()
688 u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32); in davinci_gpio_resume()
699 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
700 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
701 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
734 MODULE_ALIAS("platform:gpio-davinci");