Lines Matching +full:0 +full:x0020000
39 ATOM_MAJOR_VERSION =0x0003,
40 ATOM_MINOR_VERSION =0x0003,
58 ATOM_CRTC1 =0,
64 ATOM_CRTC_INVALID =0xff,
78 ATOM_PPLL_INVALID =0xff,
83 ASIC_INT_DIG1_ENCODER_ID =0x03,
84 ASIC_INT_DIG2_ENCODER_ID =0x09,
85 ASIC_INT_DIG3_ENCODER_ID =0x0a,
86 ASIC_INT_DIG4_ENCODER_ID =0x0b,
87 ASIC_INT_DIG5_ENCODER_ID =0x0c,
88 ASIC_INT_DIG6_ENCODER_ID =0x0d,
89 ASIC_INT_DIG7_ENCODER_ID =0x0e,
95 ATOM_ENCODER_MODE_DP =0,
96 ATOM_ENCODER_MODE_DP_SST =0,
107 ENCODER_REFCLK_SRC_P1PLL =0,
111 ENCODER_REFCLK_SRC_INVALID =0xff,
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
121 ATOM_DISABLE = 0,
136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01,
137 ATOM_SS_DOWN_SPREAD_MODE = 0x00,
138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01,
139 ATOM_INT_OR_EXT_SS_MASK = 0x02,
140 ATOM_INTERNAL_SS_MASK = 0x00,
141 ATOM_EXTERNAL_SS_MASK = 0x02,
146 PANEL_BPC_UNDEFINE =0x00,
147 PANEL_6BIT_PER_COLOR =0x01,
148 PANEL_8BIT_PER_COLOR =0x02,
149 PANEL_10BIT_PER_COLOR =0x03,
150 PANEL_12BIT_PER_COLOR =0x04,
151 PANEL_16BIT_PER_COLOR =0x05,
168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11,
169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12,
170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13,
171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14,
172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15,
173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16,
174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17,
175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18,
176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19,
177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A,
181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60,
183 ATOM_DGPU_VRAM_TYPE_HBM2E = 0x61,
184 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70,
185 ATOM_DGPU_VRAM_TYPE_HBM3 = 0x80,
189 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00,
190 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01,
191 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02,
192 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03,
193 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08,
194 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09,
195 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a,
196 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10,
197 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11,
198 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
216 OFFSET_TO_ATOM_ROM_HEADER_POINTER = 0x00000048,
217 OFFSET_TO_ATOM_ROM_IMAGE_SIZE = 0x00000002,
218 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE = 0x94,
219 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE = 20, /*including the terminator 0x0!*/
220 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS = 0x2f,
221 OFFSET_TO_GET_ATOMBIOS_STRING_START = 0x6e,
222 OFFSET_TO_VBIOS_PART_NUMBER = 0x80,
223 OFFSET_TO_VBIOS_DATE = 0x50,
366 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
457 ATOM_HSYNC_POLARITY = 0x0002,
458 ATOM_VSYNC_POLARITY = 0x0004,
459 ATOM_H_REPLICATIONBY2 = 0x0010,
460 ATOM_V_REPLICATIONBY2 = 0x0020,
461 ATOM_INTERLACE = 0x0080,
462 ATOM_COMPOSITESYNC = 0x0040,
492 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
502 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
503 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002,
504 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040,
505 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080,
506 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100,
507 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200,
508 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400,
509 ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000,
510 ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE = 0x0020000,
514 AIR_COOLING = 0x00,
515 LIQUID_COOLING = 0x01
531 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
559 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
570 …uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table ins…
587 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
598 …uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table ins…
650 ATOM_PANEL_MISC_FPDI =0x0002,
656 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip
657 …eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without A…
658 …eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init
679 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */
680 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */
681 …I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C …
694 …/* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; …
725 * set SRIOV_MSG_SHARE_RESERVATION mask start_address_in_kb = 0
788 ATOM_RECORD_END_TYPE = 0xFF,
801 …uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached …
814 …uint16_t connector_caps; //01b if internal display is checked; 10b if internal BL is checked; 0 of…
827 …ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW enco…
828 …ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is …
829 …ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified an…
830 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not.
831 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board.
832 ATOM_ENCODER_CAP_RECORD_DP2 =0x10, // DP2 is supported by ASIC/board.
833 …ATOM_ENCODER_CAP_RECORD_UHBR10_EN =0x20, // DP2.0 UHBR10 settings is supported…
834 …ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN =0x40, // DP2.0 UHBR13.5 settings is support…
835 …ATOM_ENCODER_CAP_RECORD_UHBR20_EN =0x80, // DP2.0 UHBR20 settings is supported…
836 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type.
847 …ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-e…
848 …ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this inter…
875 GPIO_PIN_TYPE_INPUT = 0x00,
876 GPIO_PIN_TYPE_OUTPUT = 0x10,
877 GPIO_PIN_TYPE_HW_CONTROL = 0x20,
880 GPIO_PIN_OUTPUT_STATE_MASK = 0x01,
881 GPIO_PIN_OUTPUT_STATE_SHIFT = 0,
882 GPIO_PIN_STATE_ACTIVE_LOW = 0x0,
883 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1,
890 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0,
955 uint8_t mini_type; //Mini Type (0 = Normal; 1 = Mini)
961 MINI_TYPE_NORMAL = 0,
966 …ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP sign…
967 …ATOM_DISPLAY_LCD2_SUPPORT = 0x0020, //second edp device tag 0x0020 for backward compabili…
968 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008,
969 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080,
970 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200,
971 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400,
972 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800,
973 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040,
974 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8,
994 uint16_t reserved1; //only on USBC case, otherwise always = 0
995 uint16_t reserved2; //reserved and always = 0
996 uint16_t reserved3; //reserved and always = 0
1000 uint16_t reserved4; //reserved and always = 0
1183 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED = 0x02,
1185 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 = 0x04,
1187 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING = 0x08,
1189 DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE = 0x20,
1190 DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40,
1263 …uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapp…
1264 …uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not inv…
1271 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE = 0x0001,
1272 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = 0x0002,
1273 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007C,
1274 EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x01 << 2), //PI redriver chip
1275 EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), //TI retimer chip
1276 EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x03 << 2) //Parade DP->HDMI recoverter chip
1284 … // a simple Checksum of the sum of whole structure equal to 0x0.
1311 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
1318 uint8_t flashlight_id; // 0: Rear, 1: Front
1337 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1346 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1383 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1393 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1630 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
1636 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10,
1641 ATOM_ENABLE_DVI_TUNINGSET = 0x01,
1642 ATOM_ENABLE_HDMI_TUNINGSET = 0x02,
1643 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04,
1644 ATOM_ENABLE_DP_TUNINGSET = 0x08,
1645 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10,
1651 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01,
1652 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04,
1653 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08,
1659 OtherMemType = 0x01, ///< Assign 01 to Other
1679 Ddr3MemType = 0x18, ///< Assign 24 to DDR3
1880 …t; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1882 …_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1884 …_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1886 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1901 …t; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1903 …_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1905 …_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1907 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1909 …uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff mea…
1934 …t; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1936 …_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1938 …_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1940 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1942 …uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff mea…
1977 …uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff mea…
2407 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0,
2419 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
2501 uint8_t LedPin0; // GPIO number for LedPin[0]
2672 uint8_t LedPin0; // GPIO number for LedPin[0]
2794 uint8_t LedPin0; // GPIO number for LedPin[0]
3060 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001,
3061 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002,
3062 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004,
3063 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008,
3064 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010,
3065 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020,
3112 UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN = 0x00000001,
3113 UMC_CONFIG1__ENABLE_AUTO_FRAMING = 0x00000002,
3114 UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA = 0x00000004,
3115 UMC_CONFIG1__DISABLE_STROBE_MODE = 0x00000008,
3116 UMC_CONFIG1__DEBUG_DATA_PARITY_EN = 0x00000010,
3117 UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000,
3147 …uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 m…
3157 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3158 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3161 char dram_pnstring[20]; // part number end with '0'.
3183 Data Table vram_info v3.0 structure
3234 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01,
3270 …uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 m…
3280 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3281 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3288 char dram_pnstring[20]; // part number end with '0'
3321 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3322 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3332 char dram_pnstring[40]; // part number end with '0'.
3468 …VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage…
3483 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
3484 …uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in un…
3486 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff
3492 VOLTAGE_DATA_ONE_BYTE = 0,
3506 …uint8_t gpio_control_id; // default is 0 which indicate control through CG VI…
3517 …dline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset tri…
3586 b3NORMAL_ENGINE_INIT = 0,
3587 b3SRIOV_SKIP_ASIC_INIT = 0x02,
3588 b3SRIOV_LOAD_UCODE = 0x40,
3593 b3NORMAL_MEM_INIT = 0,
3594 b3DRAM_SELF_REFRESH_EXIT =0x20,
3619 b3NORMAL_CHANGE_CLOCK = 0,
3620 b3FIRST_TIME_CHANGE_CLOCK = 0x08,
3621 …b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store speci…
3677 …uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2…
3682 ATOM_SET_VOLTAGE = 0,
3704 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00,
3705 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01,
3706 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02,
3721 …uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, …
3722 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac
3759 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
3762 …uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid wh…
3767 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0,
3774 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK
3788 SMU11_SYSPLL0_ID = 0,
3798 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK
3807 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
3811 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
3815 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
3819 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
3823 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
3829 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
3835 SMU12_SYSPLL0_ID = 0,
3843 SMU12_SYSPLL0_SMNCLK_ID = 0, // SOCCLK
3857 SMU12_SYSPLL1_DISPCLK_ID = 0, // DISPCLK
3864 SMU12_SYSPLL2_Pre_GFXCLK_ID = 0, // Pre_GFXCLK
3868 SMU12_SYSPLL3_0_FCLK_ID = 0, // FCLK
3872 SMU12_SYSPLL3_1_UMCCLK_ID = 0, // UMCCLK
3932 UMC60_UCODE_FUNC_ID_REINIT = 0,
3970 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01,
3971 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02,
3972 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04,
3973 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08,
3974 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30,
3975 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00,
3976 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10,
3977 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20,
3978 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30,
3979 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40,
3980 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80,
3986 …PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disab…
3987 …PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set…
3988 …PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set…
3989 …PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set…
4002 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
4004 …uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when u…
4011 DCE_CLOCK_TYPE_DISPCLK = 0,
4019 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03,
4020 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00,
4021 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01,
4022 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02,
4023 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03,
4029 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03,
4030 …DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disab…
4031 …DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set…
4032 …DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set…
4033 …DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set…
4034 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04,
4058 ATOM_BLANKING_OFF = 0,
4131 HW_I2C_READ = 0,
4132 I2C_2BYTE_ADDR = 0x02,
4133 HW_I2C_SMBUS_BYTE_WR = 0x04,
4158 …uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, …
4182 ATOM_ENCODER_CMD_DISABLE_DIG = 0,
4184 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08,
4185 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09,
4186 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a,
4187 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13,
4188 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b,
4189 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c,
4190 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d,
4191 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10,
4192 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14,
4193 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F,
4194 ATOM_ENCODER_CMD_LINK_SETUP = 0x11,
4195 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12,
4201 DP_PANEL_MODE_DISABLE = 0x00,
4202 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01,
4203 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11,
4209 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00,
4210 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01,
4211 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02,
4212 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03,
4213 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04,
4214 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05,
4215 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06,
4216 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07,
4221 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4233 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4245 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4254 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4275 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
4283 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
4299 ATOM_TRANSMITTER_ACTION_DISABLE = 0,
4318 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01,
4319 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02,
4320 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04,
4321 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08,
4322 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10,
4323 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20,
4324 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40,
4331 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00,
4332 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01,
4333 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02,
4334 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03,
4335 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04,
4336 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05,
4337 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06,
4343 DP_LANE_SET__0DB_0_4V = 0x00,
4344 DP_LANE_SET__0DB_0_6V = 0x01,
4345 DP_LANE_SET__0DB_0_8V = 0x02,
4346 DP_LANE_SET__0DB_1_2V = 0x03,
4347 DP_LANE_SET__3_5DB_0_4V = 0x08,
4348 DP_LANE_SET__3_5DB_0_6V = 0x09,
4349 DP_LANE_SET__3_5DB_0_8V = 0x0a,
4350 DP_LANE_SET__6DB_0_4V = 0x10,
4351 DP_LANE_SET__6DB_0_6V = 0x11,
4352 DP_LANE_SET__9_5DB_0_4V = 0x18,
4376 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00,
4377 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01,
4378 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07,
4379 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f,
4380 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10,
4381 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11,
4382 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12,
4383 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14,
4389 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03,
4390 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00,
4391 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01,
4392 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02,
4393 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03,
4394 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70,
4395 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00,
4396 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10,
4397 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20,
4428 uint8_t tableUUID[16]; //0x24
4429 …uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning …
4430 …uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning o…
4431 uint32_t reserved[4]; //0x3C
4435 uint32_t pcibus; //0x4C
4436 uint32_t pcidevice; //0x50
4437 uint32_t pcifunction; //0x54
4438 uint16_t vendorid; //0x58
4439 uint16_t deviceid; //0x5A
4440 uint16_t ssvid; //0x5C
4441 uint16_t ssid; //0x5E
4442 uint32_t revision; //0x60
4443 uint32_t imagelength; //0x64
4468 ATOM_DEVICE_CONNECT_INFO_DEF = 0,
4480 ATOM_DISPLAY_LCD1_CONNECT =0x0002,
4481 ATOM_DISPLAY_DFP1_CONNECT =0x0008,
4482 ATOM_DISPLAY_DFP2_CONNECT =0x0080,
4483 ATOM_DISPLAY_DFP3_CONNECT =0x0200,
4484 ATOM_DISPLAY_DFP4_CONNECT =0x0400,
4485 ATOM_DISPLAY_DFP5_CONNECT =0x0800,
4486 ATOM_DISPLAY_DFP6_CONNECT =0x0040,
4487 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8,
4488 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff,
4492 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8,
4494 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00,
4495 ATOM_DEVICE_DPMS_STATE =0x00010000,
4500 ATOM_DISPLAY_LCD1_ACTIVE =0x0002,
4501 ATOM_DISPLAY_DFP1_ACTIVE =0x0008,
4502 ATOM_DISPLAY_DFP2_ACTIVE =0x0080,
4503 ATOM_DISPLAY_DFP3_ACTIVE =0x0200,
4504 ATOM_DISPLAY_DFP4_ACTIVE =0x0400,
4505 ATOM_DISPLAY_DFP5_ACTIVE =0x0800,
4506 ATOM_DISPLAY_DFP6_ACTIVE =0x0040,
4507 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff,
4511 ATOM_DISPLAY_LCD1_REQ =0x0002,
4512 ATOM_DISPLAY_DFP1_REQ =0x0008,
4513 ATOM_DISPLAY_DFP2_REQ =0x0080,
4514 ATOM_DISPLAY_DFP3_REQ =0x0200,
4515 ATOM_DISPLAY_DFP4_REQ =0x0400,
4516 ATOM_DISPLAY_DFP5_REQ =0x0800,
4517 ATOM_DISPLAY_DFP6_REQ =0x0040,
4518 ATOM_REQ_INFO_DEVICE_MASK =0x0fff,
4527 ATOM_ACC_CHANGE_ACC_MODE =0x00000010,
4528 ATOM_ACC_CHANGE_LID_STATUS =0x00000040,
4532 ATOM_PRE_OS_MODE_MASK =0x00000003,
4533 ATOM_PRE_OS_MODE_VGA =0x00000000,
4534 ATOM_PRE_OS_MODE_VESA =0x00000001,
4535 ATOM_PRE_OS_MODE_GOP =0x00000002,
4536 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C,
4537 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0,
4538 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100,
4539 ATOM_ASIC_INIT_COMPLETE =0x00000200,
4541 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000,