Lines Matching +full:0 +full:x0c08
11 #define KS_PRIO_M 0x7
14 /* 0 - Operation */
15 #define REG_CHIP_ID0__1 0x0000
17 #define REG_CHIP_ID1__1 0x0001
19 #define FAMILY_ID 0x95
20 #define FAMILY_ID_94 0x94
21 #define FAMILY_ID_95 0x95
22 #define FAMILY_ID_85 0x85
23 #define FAMILY_ID_98 0x98
24 #define FAMILY_ID_88 0x88
26 #define REG_CHIP_ID2__1 0x0002
28 #define CHIP_ID_66 0x66
29 #define CHIP_ID_67 0x67
30 #define CHIP_ID_77 0x77
31 #define CHIP_ID_93 0x93
32 #define CHIP_ID_96 0x96
33 #define CHIP_ID_97 0x97
35 #define REG_CHIP_ID3__1 0x0003
37 #define SWITCH_REVISION_M 0x0F
39 #define SWITCH_RESET 0x01
41 #define REG_SW_PME_CTRL 0x0006
44 #define PME_POLARITY BIT(0)
46 #define REG_GLOBAL_OPTIONS 0x000F
51 #define SW_9567_RL_5_2 0xC
52 #define SW_9477_SL_5_2 0xD
54 #define SW_9896_GL_5_1 0xB
55 #define SW_9896_RL_5_1 0x8
56 #define SW_9896_SL_5_1 0x9
58 #define SW_9895_GL_4_1 0x7
59 #define SW_9895_RL_4_1 0x4
60 #define SW_9895_SL_4_1 0x5
62 #define SW_9896_RL_4_2 0x6
64 #define SW_9893_RL_2_1 0x0
65 #define SW_9893_SL_2_1 0x1
66 #define SW_9893_GL_2_1 0x3
69 #define SW_9893_RN_2_1 0xC
71 #define REG_SW_INT_STATUS__4 0x0010
72 #define REG_SW_INT_MASK__4 0x0014
80 #define REG_SW_PORT_INT_STATUS__4 0x0018
81 #define REG_SW_PORT_INT_MASK__4 0x001C
82 #define REG_SW_PHY_INT_STATUS 0x0020
83 #define REG_SW_PHY_INT_ENABLE 0x0024
86 #define REG_SW_GLOBAL_SERIAL_CTRL_0 0x0100
92 #define SPI_CLOCK_OUT_RISING_EDGE BIT(0)
94 #define REG_SW_GLOBAL_OUTPUT_CTRL__1 0x0103
96 #define SW_REFCLKO_IS_125MHZ BIT(0)
98 #define REG_SW_IBA__4 0x0104
103 #define SW_IBA_QID_M 0xF
105 #define SW_IBA_PORT_M 0x2F
107 #define SW_IBA_FRAME_TPID_M 0xFFFF
109 #define REG_SW_APB_TIMEOUT_ADDR__4 0x0108
113 #define REG_SW_IBA_SYNC__1 0x010C
115 #define REG_SW_IO_STRENGTH__1 0x010D
116 #define SW_DRIVE_STRENGTH_M 0x7
117 #define SW_DRIVE_STRENGTH_2MA 0
126 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0
128 #define REG_SW_IBA_STATUS__4 0x0110
138 #define REG_SW_IBA_STATES__4 0x0114
143 #define SW_IBA_STATE_M 0x3
144 #define SW_IBA_PACKET_SIZE_M 0x7F
146 #define SW_IBA_FMT_ID_M 0xFFFF
148 #define REG_SW_IBA_RESULT__4 0x0118
155 #define REG_SW_POWER_MANAGEMENT_CTRL 0x0201
158 #define SW_POWER_DOWN_MODE 0x3
164 #define REG_SW_OPERATION 0x0300
169 #define REG_SW_MAC_ADDR_0 0x0302
170 #define REG_SW_MAC_ADDR_1 0x0303
171 #define REG_SW_MAC_ADDR_2 0x0304
172 #define REG_SW_MAC_ADDR_3 0x0305
173 #define REG_SW_MAC_ADDR_4 0x0306
174 #define REG_SW_MAC_ADDR_5 0x0307
176 #define REG_SW_MTU__2 0x0308
177 #define REG_SW_MTU_MASK GENMASK(13, 0)
179 #define REG_SW_ISP_TPID__2 0x030A
181 #define REG_SW_HSR_TPID__2 0x030C
183 #define REG_AVB_STRATEGY__2 0x030E
186 #define SW_POLICING_CREDIT_ACCT BIT(0)
188 #define REG_SW_LUE_CTRL_0 0x0310
196 #define SW_HASH_OPTION_M 0x03
201 #define REG_SW_LUE_CTRL_1 0x0311
210 #define SW_LINK_AUTO_AGING BIT(0)
212 #define REG_SW_LUE_CTRL_2 0x0312
217 #define SW_FLUSH_OPTION_M 0x3
222 #define SW_PRIO_M 0x3
223 #define SW_PRIO_DA 0
228 #define REG_SW_LUE_CTRL_3 0x0313
229 #define SW_AGE_PERIOD_7_0_M GENMASK(7, 0)
231 #define REG_SW_LUE_INT_STATUS 0x0314
232 #define REG_SW_LUE_INT_ENABLE 0x0315
236 #define WRITE_FAIL_INT BIT(0)
238 #define REG_SW_LUE_INDEX_0__2 0x0316
240 #define ENTRY_INDEX_M 0x0FFF
242 #define REG_SW_LUE_INDEX_1__2 0x0318
244 #define FAIL_INDEX_M 0x03FF
246 #define REG_SW_LUE_INDEX_2__2 0x031A
248 #define REG_SW_LUE_UNK_UCAST_CTRL__4 0x0320
252 #define REG_SW_LUE_UNK_MCAST_CTRL__4 0x0324
256 #define REG_SW_LUE_UNK_VID_CTRL__4 0x0328
260 #define REG_SW_MAC_CTRL_0 0x0330
265 #define SW_AGGR_BACKOFF BIT(0)
267 #define REG_SW_MAC_CTRL_1 0x0331
274 #define SW_PASS_SHORT_FRAME BIT(0)
276 #define REG_SW_MAC_CTRL_2 0x0332
280 #define REG_SW_MAC_CTRL_3 0x0333
282 #define REG_SW_MAC_CTRL_4 0x0334
286 #define REG_SW_MAC_CTRL_5 0x0335
290 #define REG_SW_MAC_CTRL_6 0x0336
295 #define REG_SW_MAC_802_1P_MAP_0 0x0338
296 #define REG_SW_MAC_802_1P_MAP_1 0x0339
297 #define REG_SW_MAC_802_1P_MAP_2 0x033A
298 #define REG_SW_MAC_802_1P_MAP_3 0x033B
303 #define REG_SW_MAC_ISP_CTRL 0x033C
305 #define REG_SW_MAC_TOS_CTRL 0x033E
308 #define SW_TOS_DSCP_REMAP BIT(0)
310 #define REG_SW_MAC_TOS_PRIO_0 0x0340
311 #define REG_SW_MAC_TOS_PRIO_1 0x0341
312 #define REG_SW_MAC_TOS_PRIO_2 0x0342
313 #define REG_SW_MAC_TOS_PRIO_3 0x0343
314 #define REG_SW_MAC_TOS_PRIO_4 0x0344
315 #define REG_SW_MAC_TOS_PRIO_5 0x0345
316 #define REG_SW_MAC_TOS_PRIO_6 0x0346
317 #define REG_SW_MAC_TOS_PRIO_7 0x0347
318 #define REG_SW_MAC_TOS_PRIO_8 0x0348
319 #define REG_SW_MAC_TOS_PRIO_9 0x0349
320 #define REG_SW_MAC_TOS_PRIO_10 0x034A
321 #define REG_SW_MAC_TOS_PRIO_11 0x034B
322 #define REG_SW_MAC_TOS_PRIO_12 0x034C
323 #define REG_SW_MAC_TOS_PRIO_13 0x034D
324 #define REG_SW_MAC_TOS_PRIO_14 0x034E
325 #define REG_SW_MAC_TOS_PRIO_15 0x034F
326 #define REG_SW_MAC_TOS_PRIO_16 0x0350
327 #define REG_SW_MAC_TOS_PRIO_17 0x0351
328 #define REG_SW_MAC_TOS_PRIO_18 0x0352
329 #define REG_SW_MAC_TOS_PRIO_19 0x0353
330 #define REG_SW_MAC_TOS_PRIO_20 0x0354
331 #define REG_SW_MAC_TOS_PRIO_21 0x0355
332 #define REG_SW_MAC_TOS_PRIO_22 0x0356
333 #define REG_SW_MAC_TOS_PRIO_23 0x0357
334 #define REG_SW_MAC_TOS_PRIO_24 0x0358
335 #define REG_SW_MAC_TOS_PRIO_25 0x0359
336 #define REG_SW_MAC_TOS_PRIO_26 0x035A
337 #define REG_SW_MAC_TOS_PRIO_27 0x035B
338 #define REG_SW_MAC_TOS_PRIO_28 0x035C
339 #define REG_SW_MAC_TOS_PRIO_29 0x035D
340 #define REG_SW_MAC_TOS_PRIO_30 0x035E
341 #define REG_SW_MAC_TOS_PRIO_31 0x035F
343 #define REG_SW_MRI_CTRL_0 0x0370
348 #define SW_MIRROR_RX_TX BIT(0)
350 #define REG_SW_CLASS_D_IP_CTRL__4 0x0374
354 #define REG_SW_MRI_CTRL_8 0x0378
359 #define SW_GREEN_COLOR_S 0
360 #define SW_COLOR_M 0x3
362 #define REG_SW_QM_CTRL__4 0x0390
366 #define PRIO_MAP_3_HI 0
371 #define REG_SW_EEE_QM_CTRL__2 0x03C0
373 #define REG_SW_EEE_TXQ_WAIT_TIME__2 0x03C2
376 #define REG_SW_VLAN_ENTRY__4 0x0400
382 #define VLAN_MSTP_M 0x7
384 #define VLAN_FID_M 0x7F
386 #define REG_SW_VLAN_ENTRY_UNTAG__4 0x0404
387 #define REG_SW_VLAN_ENTRY_PORTS__4 0x0408
389 #define REG_SW_VLAN_ENTRY_INDEX__2 0x040C
391 #define VLAN_INDEX_M 0x0FFF
393 #define REG_SW_VLAN_CTRL 0x040E
396 #define VLAN_ACTION 0x3
401 #define REG_SW_ALU_INDEX_0 0x0410
404 #define ALU_MAC_ADDR_HI 0xFFFF
406 #define REG_SW_ALU_INDEX_1 0x0414
410 #define REG_SW_ALU_CTRL__4 0x0418
417 #define ALU_ACTION 0x3
422 #define REG_SW_ALU_STAT_CTRL__4 0x041C
428 #define REG_SW_ALU_VAL_A 0x0420
435 #define ALU_V_MSTP_M 0x7
437 #define REG_SW_ALU_VAL_B 0x0424
443 #define REG_SW_ALU_VAL_C 0x0428
447 #define ALU_V_MAC_ADDR_HI 0xFFFF
449 #define REG_SW_ALU_VAL_D 0x042C
451 #define REG_HSR_ALU_INDEX_0 0x0440
453 #define REG_HSR_ALU_INDEX_1 0x0444
456 #define HSR_SRC_MAC_INDEX_HI 0xFFFF
458 #define REG_HSR_ALU_INDEX_2 0x0448
463 #define REG_HSR_ALU_INDEX_3 0x044C
467 #define REG_HSR_ALU_CTRL__4 0x0450
475 #define HSR_ACTION 0x3
480 #define REG_HSR_ALU_VAL_A 0x0454
487 #define REG_HSR_ALU_VAL_B 0x0458
489 #define REG_HSR_ALU_VAL_C 0x045C
492 #define HSR_V_SRC_MAC_ADDR_HI 0xFFFF
494 #define REG_HSR_ALU_VAL_D 0x0460
496 #define REG_HSR_ALU_VAL_E 0x0464
499 #define HSR_V_START_SEQ_2_S 0
501 #define REG_HSR_ALU_VAL_F 0x0468
504 #define HSR_V_EXP_SEQ_2_S 0
506 #define REG_HSR_ALU_VAL_G 0x046C
509 #define HSR_V_SEQ_CNT_2_S 0
514 #define REG_PTP_CLK_CTRL 0x0500
522 #define PTP_CLK_RESET BIT(0)
524 #define REG_PTP_RTC_SUB_NANOSEC__2 0x0502
526 #define PTP_RTC_SUB_NANOSEC_M 0x0007
528 #define REG_PTP_RTC_NANOSEC 0x0504
529 #define REG_PTP_RTC_NANOSEC_H 0x0504
530 #define REG_PTP_RTC_NANOSEC_L 0x0506
532 #define REG_PTP_RTC_SEC 0x0508
533 #define REG_PTP_RTC_SEC_H 0x0508
534 #define REG_PTP_RTC_SEC_L 0x050A
536 #define REG_PTP_SUBNANOSEC_RATE 0x050C
537 #define REG_PTP_SUBNANOSEC_RATE_H 0x050C
542 #define REG_PTP_SUBNANOSEC_RATE_L 0x050E
544 #define REG_PTP_RATE_DURATION 0x0510
545 #define REG_PTP_RATE_DURATION_H 0x0510
546 #define REG_PTP_RATE_DURATION_L 0x0512
548 #define REG_PTP_MSG_CONF1 0x0514
557 #define PTP_1STEP BIT(0)
559 #define REG_PTP_MSG_CONF2 0x0516
571 #define REG_PTP_DOMAIN_VERSION 0x0518
572 #define PTP_VERSION_M 0xFF00
573 #define PTP_DOMAIN_M 0x00FF
575 #define REG_PTP_UNIT_INDEX__4 0x0520
577 #define PTP_UNIT_M 0xF
581 #define PTP_TOU_INDEX_S 0
583 #define REG_PTP_TRIG_STATUS__4 0x0524
586 #define TRIG_DONE_S 0
588 #define REG_PTP_INT_STATUS__4 0x0528
591 #define TS_INT_S 0
593 #define TRIG_UNIT_M 0x7
594 #define TS_UNIT_M 0x3
596 #define REG_PTP_CTRL_STAT__4 0x052C
605 #define TS_RESET BIT(0)
615 #define REG_TRIG_TARGET_NANOSEC 0x0530
616 #define REG_TRIG_TARGET_SEC 0x0534
618 #define REG_TRIG_CTRL__4 0x0538
622 #define TRIG_CASCADE_UPS_M 0xF
628 #define TRIG_PATTERN_M 0x7
629 #define TRIG_NEG_EDGE 0
637 #define TRIG_GPO_M 0xF
638 #define TRIG_CASCADE_ITERATE_CNT_M 0xFFFF
640 #define REG_TRIG_CYCLE_WIDTH 0x053C
642 #define REG_TRIG_CYCLE_CNT 0x0540
644 #define TRIG_CYCLE_CNT_M 0xFFFF
646 #define TRIG_BIT_PATTERN_M 0xFFFF
648 #define REG_TRIG_ITERATE_TIME 0x0544
650 #define REG_TRIG_PULSE_WIDTH__4 0x0548
652 #define TRIG_PULSE_WIDTH_M 0x00FFFFFF
654 #define REG_TS_CTRL_STAT__4 0x0550
656 #define TS_EVENT_DETECT_M 0xF
659 #define TS_GPI_M 0xF
665 #define TS_CASCADE_UPS_M 0xF
667 #define TS_CASCADE_ENABLE BIT(0)
672 #define REG_TS_EVENT_0_NANOSEC 0x0554
673 #define REG_TS_EVENT_0_SEC 0x0558
674 #define REG_TS_EVENT_0_SUB_NANOSEC 0x055C
676 #define REG_TS_EVENT_1_NANOSEC 0x0560
677 #define REG_TS_EVENT_1_SEC 0x0564
678 #define REG_TS_EVENT_1_SUB_NANOSEC 0x0568
680 #define REG_TS_EVENT_2_NANOSEC 0x056C
681 #define REG_TS_EVENT_2_SEC 0x0570
682 #define REG_TS_EVENT_2_SUB_NANOSEC 0x0574
684 #define REG_TS_EVENT_3_NANOSEC 0x0578
685 #define REG_TS_EVENT_3_SEC 0x057C
686 #define REG_TS_EVENT_3_SUB_NANOSEC 0x0580
688 #define REG_TS_EVENT_4_NANOSEC 0x0584
689 #define REG_TS_EVENT_4_SEC 0x0588
690 #define REG_TS_EVENT_4_SUB_NANOSEC 0x058C
692 #define REG_TS_EVENT_5_NANOSEC 0x0590
693 #define REG_TS_EVENT_5_SEC 0x0594
694 #define REG_TS_EVENT_5_SUB_NANOSEC 0x0598
696 #define REG_TS_EVENT_6_NANOSEC 0x059C
697 #define REG_TS_EVENT_6_SEC 0x05A0
698 #define REG_TS_EVENT_6_SUB_NANOSEC 0x05A4
700 #define REG_TS_EVENT_7_NANOSEC 0x05A8
701 #define REG_TS_EVENT_7_SEC 0x05AC
702 #define REG_TS_EVENT_7_SUB_NANOSEC 0x05B0
704 #define TS_EVENT_EDGE_M 0x1
708 #define TS_EVENT_SUB_NANOSEC_M 0x7
715 #define REG_GLOBAL_RR_INDEX__1 0x0600
718 #define REG_DLR_SRC_PORT__4 0x0604
721 #define DLR_SRC_PORT_M 0x3
722 #define DLR_SRC_PORT_BOTH 0
725 #define REG_DLR_IP_ADDR__4 0x0608
727 #define REG_DLR_CTRL__1 0x0610
732 #define DLR_ASSIST_ENABLE BIT(0)
734 #define REG_DLR_STATE__1 0x0611
736 #define DLR_NODE_STATE_M 0x3
738 #define DLR_NODE_STATE_IDLE 0
741 #define DLR_RING_STATE_FAULT 0
744 #define REG_DLR_PRECEDENCE__1 0x0612
746 #define REG_DLR_BEACON_INTERVAL__4 0x0614
748 #define REG_DLR_BEACON_TIMEOUT__4 0x0618
750 #define REG_DLR_TIMEOUT_WINDOW__4 0x061C
754 #define REG_DLR_VLAN_ID__2 0x0620
758 #define REG_DLR_DEST_ADDR_0 0x0622
759 #define REG_DLR_DEST_ADDR_1 0x0623
760 #define REG_DLR_DEST_ADDR_2 0x0624
761 #define REG_DLR_DEST_ADDR_3 0x0625
762 #define REG_DLR_DEST_ADDR_4 0x0626
763 #define REG_DLR_DEST_ADDR_5 0x0627
765 #define REG_DLR_PORT_MAP__4 0x0628
767 #define REG_DLR_CLASS__1 0x062C
769 #define DLR_FRAME_QID_M 0x3
772 #define REG_HSR_PORT_MAP__4 0x0640
774 #define REG_HSR_ALU_CTRL_0__1 0x0644
778 #define HSR_AGE_CNT_DEFAULT_M 0x7
781 #define HSR_HASH_OPTION_M 0x3
782 #define HSR_HASH_DISABLE 0
787 #define REG_HSR_ALU_CTRL_1__1 0x0645
794 #define REG_HSR_ALU_CTRL_2__2 0x0646
796 #define REG_HSR_ALU_AGE_PERIOD__4 0x0648
798 #define REG_HSR_ALU_INT_STATUS__1 0x064C
799 #define REG_HSR_ALU_INT_MASK__1 0x064D
804 #define HSR_WRITE_FAIL_INT BIT(0)
806 #define REG_HSR_ALU_ENTRY_0__2 0x0650
811 #define REG_HSR_ALU_ENTRY_1__2 0x0652
815 #define REG_HSR_ALU_ENTRY_3__2 0x0654
819 /* 0 - Operation */
820 #define REG_PORT_DEFAULT_VID 0x0000
822 #define REG_PORT_CUSTOM_VID 0x0002
823 #define REG_PORT_AVB_SR_1_VID 0x0004
824 #define REG_PORT_AVB_SR_2_VID 0x0006
826 #define REG_PORT_AVB_SR_1_TYPE 0x0008
827 #define REG_PORT_AVB_SR_2_TYPE 0x000A
829 #define REG_PORT_PME_STATUS 0x0013
830 #define REG_PORT_PME_CTRL 0x0017
834 #define PME_WOL_ENERGY BIT(0)
836 #define REG_PORT_INT_STATUS 0x001B
837 #define REG_PORT_INT_MASK 0x001F
842 #define PORT_ACL_INT BIT(0)
847 #define REG_PORT_CTRL_0 0x0020
853 #define PORT_QUEUE_SPLIT_MASK GENMASK(1, 0)
854 #define PORT_EIGHT_QUEUE 0x3
855 #define PORT_FOUR_QUEUE 0x2
856 #define PORT_TWO_QUEUE 0x1
857 #define PORT_SINGLE_QUEUE 0x0
859 #define REG_PORT_CTRL_1 0x0021
861 #define PORT_SRP_ENABLE 0x3
863 #define REG_PORT_STATUS_0 0x0030
865 #define PORT_INTF_SPEED_M 0x3
869 #define PORT_RX_FLOW_CTRL BIT(0)
871 #define REG_PORT_STATUS_1 0x0034
874 #define REG_PORT_PHY_CTRL 0x0100
887 #define REG_PORT_PHY_STATUS 0x0102
901 #define PORT_EXTENDED_CAPABILITY BIT(0)
903 #define REG_PORT_PHY_ID_HI 0x0104
904 #define REG_PORT_PHY_ID_LO 0x0106
906 #define KSZ9477_ID_HI 0x0022
907 #define KSZ9477_ID_LO 0x1622
909 #define REG_PORT_PHY_AUTO_NEGOTIATION 0x0108
920 #define PORT_AUTO_NEG_SELECTOR 0x001F
921 #define PORT_AUTO_NEG_802_3 0x0001
926 #define REG_PORT_PHY_REMOTE_CAPABILITY 0x010A
938 #define REG_PORT_PHY_1000_CTRL 0x0112
946 #define REG_PORT_PHY_1000_STATUS 0x0114
954 #define PORT_REMOTE_IDLE_CNT_M 0x0F
962 #define REG_PORT_PHY_MMD_SETUP 0x011A
964 #define PORT_MMD_OP_MODE_M 0x3
966 #define PORT_MMD_OP_INDEX 0
970 #define PORT_MMD_DEVICE_ID_M 0x1F
975 #define REG_PORT_PHY_MMD_INDEX_DATA 0x011C
979 #define MMD_DSP_SQI_CHAN_A 0xAC
980 #define MMD_DSP_SQI_CHAN_B 0xAD
981 #define MMD_DSP_SQI_CHAN_C 0xAE
982 #define MMD_DSP_SQI_CHAN_D 0xAF
985 #define DSP_SQI_AVG_ERR 0x7FFF
991 #define MMD_EEE_ADV 0x3C
995 #define MMD_EEE_LP_ADV 0x3D
996 #define MMD_EEE_MSG_CODE 0x3F
998 #define MMD_DEVICE_ID_AFED 0x1C
1000 #define REG_PORT_PHY_EXTENDED_STATUS 0x011E
1007 #define REG_PORT_SGMII_ADDR__4 0x0200
1009 #define PORT_SGMII_DEVICE_ID_M 0x1F
1013 #define REG_PORT_SGMII_DATA__4 0x0204
1016 #define MMD_DEVICE_ID_PMA 0x01
1017 #define MMD_DEVICE_ID_PCS 0x03
1018 #define MMD_DEVICE_ID_PHY_XS 0x04
1019 #define MMD_DEVICE_ID_DTE_XS 0x05
1020 #define MMD_DEVICE_ID_AN 0x07
1021 #define MMD_DEVICE_ID_VENDOR_CTRL 0x1E
1022 #define MMD_DEVICE_ID_VENDOR_MII 0x1F
1026 #define MMD_SR_MII_CTRL 0x0000
1037 #define MMD_SR_MII_STATUS 0x0001
1038 #define MMD_SR_MII_ID_1 0x0002
1039 #define MMD_SR_MII_ID_2 0x0003
1040 #define MMD_SR_MII_AUTO_NEGOTIATION 0x0004
1043 #define SR_MII_AUTO_NEG_REMOTE_FAULT_M 0x3
1045 #define SR_MII_AUTO_NEG_NO_ERROR 0
1049 #define SR_MII_AUTO_NEG_PAUSE_M 0x3
1051 #define SR_MII_AUTO_NEG_NO_PAUSE 0
1058 #define MMD_SR_MII_REMOTE_CAPABILITY 0x0005
1059 #define MMD_SR_MII_AUTO_NEG_EXP 0x0006
1060 #define MMD_SR_MII_AUTO_NEG_EXT 0x000F
1062 #define MMD_SR_MII_DIGITAL_CTRL_1 0x8000
1064 #define MMD_SR_MII_AUTO_NEG_CTRL 0x8001
1069 #define SR_MII_PCS_MODE_M 0x3
1072 #define SR_MII_AUTO_NEG_COMPLETE_INTR BIT(0)
1074 #define MMD_SR_MII_AUTO_NEG_STATUS 0x8002
1077 #define SR_MII_STAT_M 0x3
1079 #define SR_MII_STAT_10_MBPS 0
1084 #define MMD_SR_MII_PHY_CTRL 0x80A0
1086 #define SR_MII_PHY_LANE_SEL_M 0xF
1089 #define SR_MII_PHY_START_BUSY BIT(0)
1091 #define MMD_SR_MII_PHY_ADDR 0x80A1
1095 #define MMD_SR_MII_PHY_DATA 0x80A2
1099 #define SR_MII_PHY_JTAG_CHIP_ID_HI 0x000C
1100 #define SR_MII_PHY_JTAG_CHIP_ID_LO 0x000D
1102 #define REG_PORT_PHY_REMOTE_LB_LED 0x0122
1110 #define PORT_LINK_MD_PASS BIT(0)
1112 #define REG_PORT_PHY_LINK_MD 0x0124
1116 #define PORT_CABLE_DIAG_PAIR_M 0x3
1118 #define PORT_CABLE_DIAG_SELECT_M 0x3
1120 #define PORT_CABLE_DIAG_RESULT_M 0x3
1122 #define PORT_CABLE_STAT_NORMAL 0
1126 #define PORT_CABLE_FAULT_COUNTER 0x00FF
1128 #define REG_PORT_PHY_PMA_STATUS 0x0126
1131 #define PORT_100_LINK_GOOD BIT(0)
1133 #define REG_PORT_PHY_DIGITAL_STATUS 0x0128
1140 #define REG_PORT_PHY_RXER_COUNTER 0x012A
1142 #define REG_PORT_PHY_INT_ENABLE 0x0136
1143 #define REG_PORT_PHY_INT_STATUS 0x0137
1152 #define LINK_UP_INT BIT(0)
1154 #define REG_PORT_PHY_DIGITAL_DEBUG_1 0x0138
1161 #define PORT_PHY_PCS_LOOPBACK BIT(0)
1163 #define REG_PORT_PHY_DIGITAL_DEBUG_2 0x013A
1165 #define REG_PORT_PHY_DIGITAL_DEBUG_3 0x013C
1169 #define REG_PORT_PHY_PHY_CTRL 0x013E
1181 #define PORT_LINK_STATUS_FAIL BIT(0)
1185 #define PORT_GRXC_ENABLE BIT(0)
1191 #define REG_PORT_MAC_CTRL_0 0x0400
1194 #define PORT_JUMBO_FRAME BIT(0)
1196 #define REG_PORT_MAC_CTRL_1 0x0401
1199 #define PORT_PASS_ALL BIT(0)
1201 #define REG_PORT_MAC_CTRL_2 0x0402
1206 #define REG_PORT_MAC_IN_RATE_LIMIT 0x0403
1212 #define PORT_COUNT_PREAMBLE_S 0
1216 #define PORT_IN_LIMIT_MODE_M 0x3
1218 #define PORT_IN_ALL 0
1223 #define PORT_COUNT_PREAMBLE BIT(0)
1225 #define REG_PORT_IN_RATE_0 0x0410
1226 #define REG_PORT_IN_RATE_1 0x0411
1227 #define REG_PORT_IN_RATE_2 0x0412
1228 #define REG_PORT_IN_RATE_3 0x0413
1229 #define REG_PORT_IN_RATE_4 0x0414
1230 #define REG_PORT_IN_RATE_5 0x0415
1231 #define REG_PORT_IN_RATE_6 0x0416
1232 #define REG_PORT_IN_RATE_7 0x0417
1234 #define REG_PORT_OUT_RATE_0 0x0420
1235 #define REG_PORT_OUT_RATE_1 0x0421
1236 #define REG_PORT_OUT_RATE_2 0x0422
1237 #define REG_PORT_OUT_RATE_3 0x0423
1242 #define REG_PORT_MIB_CTRL_STAT__4 0x0500
1248 #define MIB_COUNTER_DATA_HI_M 0xF
1250 #define REG_PORT_MIB_DATA 0x0504
1253 #define REG_PORT_ACL_0 0x0600
1255 #define ACL_FIRST_RULE_M 0xF
1257 #define REG_PORT_ACL_1 0x0601
1259 #define ACL_MODE_M 0x3
1261 #define ACL_MODE_DISABLE 0
1265 #define ACL_ENABLE_M 0x3
1267 #define ACL_ENABLE_2_COUNT 0
1273 #define ACL_ENABLE_4_PROTOCOL 0
1278 #define ACL_EQUAL BIT(0)
1280 #define REG_PORT_ACL_2 0x0602
1281 #define REG_PORT_ACL_3 0x0603
1283 #define ACL_MAX_PORT 0xFFFF
1285 #define REG_PORT_ACL_4 0x0604
1286 #define REG_PORT_ACL_5 0x0605
1288 #define ACL_MIN_PORT 0xFFFF
1289 #define ACL_IP_ADDR 0xFFFFFFFF
1290 #define ACL_TCP_SEQNUM 0xFFFFFFFF
1292 #define REG_PORT_ACL_6 0x0606
1294 #define ACL_RESERVED 0xF8
1295 #define ACL_PORT_MODE_M 0x3
1297 #define ACL_PORT_MODE_DISABLE 0
1302 #define REG_PORT_ACL_7 0x0607
1304 #define ACL_TCP_FLAG_ENABLE BIT(0)
1306 #define REG_PORT_ACL_8 0x0608
1308 #define ACL_TCP_FLAG_M 0xFF
1310 #define REG_PORT_ACL_9 0x0609
1312 #define ACL_TCP_FLAG 0xFF
1313 #define ACL_ETH_TYPE 0xFFFF
1314 #define ACL_IP_M 0xFFFFFFFF
1316 #define REG_PORT_ACL_A 0x060A
1318 #define ACL_PRIO_MODE_M 0x3
1320 #define ACL_PRIO_MODE_DISABLE 0
1328 #define ACL_VLAN_PRIO_HI_M 0x3
1330 #define REG_PORT_ACL_B 0x060B
1332 #define ACL_VLAN_PRIO_LO_M 0x8
1334 #define ACL_MAP_MODE_M 0x3
1336 #define ACL_MAP_MODE_DISABLE 0
1344 #define REG_PORT_ACL_C 0x060C
1346 #define REG_PORT_ACL_D 0x060D
1349 #define ACL_PORT_MAP 0x7F
1351 #define REG_PORT_ACL_E 0x060E
1352 #define REG_PORT_ACL_F 0x060F
1354 #define REG_PORT_ACL_BYTE_EN_MSB 0x0610
1355 #define REG_PORT_ACL_BYTE_EN_LSB 0x0611
1357 #define ACL_ACTION_START 0xA
1359 #define ACL_INTR_CNT_START 0xD
1360 #define ACL_RULESET_START 0xE
1364 #define ACL_ACTION_ENABLE 0x003C
1365 #define ACL_MATCH_ENABLE 0x7FC3
1366 #define ACL_RULESET_ENABLE 0x8003
1367 #define ACL_BYTE_ENABLE 0xFFFF
1369 #define REG_PORT_ACL_CTRL_0 0x0612
1374 #define PORT_ACL_INDEX_M 0xF
1376 #define REG_PORT_ACL_CTRL_1 0x0613
1379 #define REG_PORT_MRI_MIRROR_CTRL 0x0800
1385 #define REG_PORT_MRI_PRIO_CTRL 0x0801
1393 #define PORT_ACL_PRIO_ENABLE BIT(0)
1395 #define REG_PORT_MRI_MAC_CTRL 0x0802
1401 #define PORT_BASED_PRIO_S 0
1403 #define REG_PORT_MRI_AUTHEN_CTRL 0x0803
1406 #define PORT_AUTHEN_MODE 0x3
1407 #define PORT_AUTHEN_PASS 0
1411 #define REG_PORT_MRI_INDEX__4 0x0804
1413 #define MRI_INDEX_P_M 0x7
1415 #define MRI_INDEX_Q_M 0x3
1416 #define MRI_INDEX_Q_S 0
1418 #define REG_PORT_MRI_TC_MAP__4 0x0808
1420 #define PORT_TC_MAP_M 0xf
1423 #define REG_PORT_MRI_POLICE_CTRL__4 0x080C
1426 #define POLICE_PACKET_TYPE_M 0x3
1428 #define POLICE_PACKET_DROPPED 0
1433 #define NON_DSCP_COLOR_M 0x3
1439 #define POLICE_ENABLE BIT(0)
1441 #define REG_PORT_POLICE_COLOR_0__4 0x0810
1442 #define REG_PORT_POLICE_COLOR_1__4 0x0814
1443 #define REG_PORT_POLICE_COLOR_2__4 0x0818
1444 #define REG_PORT_POLICE_COLOR_3__4 0x081C
1449 #define REG_PORT_POLICE_RATE__4 0x0820
1452 #define POLICE_PIR_S 0
1454 #define REG_PORT_POLICE_BURST_SIZE__4 0x0824
1456 #define POLICE_BURST_SIZE_M 0x3FFF
1458 #define POLICE_PBS_S 0
1460 #define REG_PORT_WRED_PM_CTRL_0__4 0x0830
1465 #define WRED_PM_MIN_THRESHOLD_S 0
1467 #define REG_PORT_WRED_PM_CTRL_1__4 0x0834
1470 #define WRED_PM_AVG_QUEUE_SIZE_S 0
1472 #define REG_PORT_WRED_QUEUE_CTRL_0__4 0x0840
1473 #define REG_PORT_WRED_QUEUE_CTRL_1__4 0x0844
1475 #define REG_PORT_WRED_QUEUE_PMON__4 0x0848
1487 #define REG_PORT_MTI_QUEUE_CTRL_0__4 0x0904
1489 #define MTI_PVID_REPLACE BIT(0)
1491 #define REG_PORT_MTI_CREDIT_INCREMENT 0x091A
1495 #define REG_PORT_QM_CTRL__4 0x0A00
1497 #define PORT_QM_DROP_PRIO_M 0x3
1499 #define REG_PORT_VLAN_MEMBERSHIP__4 0x0A04
1501 #define REG_PORT_QM_QUEUE_INDEX__4 0x0A08
1507 #define REG_PORT_QM_WATER_MARK__4 0x0A0C
1510 #define PORT_QM_LO_WATER_MARK_S 0
1513 #define REG_PORT_QM_TX_CNT_0__4 0x0A10
1515 #define PORT_QM_TX_CNT_USED_S 0
1518 #define REG_PORT_QM_TX_CNT_1__4 0x0A14
1521 #define PORT_QM_TX_CNT_AVAIL_S 0
1524 #define REG_PORT_LUE_CTRL 0x0B00
1532 #define REG_PORT_LUE_MSTP_INDEX 0x0B01
1534 #define REG_PORT_LUE_MSTP_STATE 0x0B04
1538 #define REG_PTP_PORT_RX_DELAY__2 0x0C00
1539 #define REG_PTP_PORT_TX_DELAY__2 0x0C02
1540 #define REG_PTP_PORT_ASYM_DELAY__2 0x0C04
1542 #define REG_PTP_PORT_XDELAY_TS 0x0C08
1543 #define REG_PTP_PORT_XDELAY_TS_H 0x0C08
1544 #define REG_PTP_PORT_XDELAY_TS_L 0x0C0A
1546 #define REG_PTP_PORT_SYNC_TS 0x0C0C
1547 #define REG_PTP_PORT_SYNC_TS_H 0x0C0C
1548 #define REG_PTP_PORT_SYNC_TS_L 0x0C0E
1550 #define REG_PTP_PORT_PDRESP_TS 0x0C10
1551 #define REG_PTP_PORT_PDRESP_TS_H 0x0C10
1552 #define REG_PTP_PORT_PDRESP_TS_L 0x0C12
1554 #define REG_PTP_PORT_TX_INT_STATUS__2 0x0C14
1555 #define REG_PTP_PORT_TX_INT_ENABLE__2 0x0C16
1561 #define REG_PTP_PORT_LINK_DELAY__4 0x0C18
1570 #define KSZ9477_COUNTER_NUM 0x20