Lines Matching +full:0 +full:x1821
82 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ in pcie_failed_link_retrain()
252 u8 cls = 0; in pci_apply_final_quirks()
286 return 0; in pci_apply_final_quirks()
324 pci_read_config_byte(d, 0x82, &dlc); in quirk_passive_release()
328 pci_write_config_byte(d, 0x82, dlc); in quirk_passive_release()
374 pci_read_config_dword(dev, 0x40, &pmbase); in quirk_tigerpoint_bm_sts()
375 pmbase = pmbase & 0xff80; in quirk_tigerpoint_bm_sts()
378 if (pm1a & 0x10) { in quirk_tigerpoint_bm_sts()
380 outw(0x10, pmbase); in quirk_tigerpoint_bm_sts()
389 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { in quirk_nopcipci()
400 pci_read_config_byte(dev, 0x08, &rev); in quirk_nopciamd()
401 if (rev == 0x13) { in quirk_nopciamd()
412 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { in quirk_triton()
445 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; in quirk_vialatency()
449 if (p->revision < 0x40 || p->revision > 0x42) in quirk_vialatency()
457 if (p->revision < 0x10 || p->revision > 0x12) in quirk_vialatency()
473 pci_read_config_byte(dev, 0x76, &busarb); in quirk_vialatency()
476 * Set bit 4 and bit 5 of byte 76 to 0x01 in quirk_vialatency()
481 pci_write_config_byte(dev, 0x76, busarb); in quirk_vialatency()
497 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { in quirk_viaetbf()
506 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { in quirk_vsfx()
515 * space. Latency must be set to 0xA and Triton workaround applied too.
520 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { in quirk_alimagik()
531 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { in quirk_natoma()
544 * This chip can cause PCI parity errors if config register 0xA0 is read
549 dev->cfg_size = 0xA0; in quirk_citrine()
554 * This chip can cause bus lockups if config addresses above 0x600
559 dev->cfg_size = 0x600; in quirk_nfp6000()
571 for (i = 0; i < PCI_STD_NUM_BARS; i++) { in quirk_extend_bar_to_page()
576 r->start = 0; in quirk_extend_bar_to_page()
583 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
591 struct resource *r = &dev->resource[0]; in quirk_s3_64M()
593 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { in quirk_s3_64M()
595 r->start = 0; in quirk_s3_64M()
596 r->end = 0x3ffffff; in quirk_s3_64M()
625 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", in quirk_io()
642 if (pci_resource_len(dev, 0) != 8) { in quirk_cs5536_vsa()
643 quirk_io(dev, 0, 8, name); /* SMB */ in quirk_cs5536_vsa()
679 * between 0x3b0->0x3bb or read 0x3d3
683 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); in quirk_ati_exploding_mce()
685 request_region(0x3b0, 0x0C, "RadeonIGP"); in quirk_ati_exploding_mce()
686 request_region(0x3d3, 0x01, "RadeonIGP"); in quirk_ati_exploding_mce()
692 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
697 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
740 PCI_CLASS_SERIAL_USB_XHCI, 0,
750 * 0xE0 (64 bytes of ACPI registers)
751 * 0xE2 (32 bytes of SMB registers)
755 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); in quirk_ali7101_acpi()
756 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); in quirk_ali7101_acpi()
769 base = devres & 0xffff; in piix4_io_quirk()
779 * reserve it (at least if it's in the 0x1000+ range), but in piix4_io_quirk()
794 base = devres & 0xffff0000; in piix4_mem_quirk()
795 mask = (devres & 0x3f) << 16; in piix4_mem_quirk()
814 * 0x40 (64 bytes of ACPI registers)
815 * 0x90 (16 bytes of SMB registers)
822 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); in quirk_piix4_acpi()
823 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); in quirk_piix4_acpi()
826 pci_read_config_dword(dev, 0x5c, &res_a); in quirk_piix4_acpi()
828 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); in quirk_piix4_acpi()
829 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); in quirk_piix4_acpi()
835 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); in quirk_piix4_acpi()
836 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); in quirk_piix4_acpi()
840 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); in quirk_piix4_acpi()
841 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); in quirk_piix4_acpi()
843 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); in quirk_piix4_acpi()
844 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); in quirk_piix4_acpi()
849 #define ICH_PMBASE 0x40
850 #define ICH_ACPI_CNTL 0x44
851 #define ICH4_ACPI_EN 0x10
852 #define ICH6_ACPI_EN 0x80
853 #define ICH4_GPIOBASE 0x58
854 #define ICH4_GPIO_CNTL 0x5c
855 #define ICH4_GPIO_EN 0x10
856 #define ICH6_GPIOBASE 0x48
857 #define ICH6_GPIO_CNTL 0x4c
858 #define ICH6_GPIO_EN 0x10
862 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
863 * 0x58 (64 bytes of GPIO I/O space)
923 base = val & 0xfffc; in ich6_lpc_generic_decode()
950 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); in quirk_ich6_lpc()
951 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); in quirk_ich6_lpc()
969 base = val & 0xfffc; in ich7_lpc_generic_decode()
970 mask = (val >> 16) & 0xfc; in ich7_lpc_generic_decode()
987 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); in quirk_ich7_lpc()
988 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); in quirk_ich7_lpc()
989 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); in quirk_ich7_lpc()
990 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); in quirk_ich7_lpc()
1008 * 0x48 or 0x20 (256 bytes of ACPI registers)
1012 if (dev->revision & 0x10) in quirk_vt82c586_acpi()
1013 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, in quirk_vt82c586_acpi()
1020 * 0x48 (256 bytes of ACPI registers)
1021 * 0x70 (128 bytes of hardware monitoring register)
1022 * 0x90 (16 bytes of SMB registers)
1028 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, in quirk_vt82c686_acpi()
1031 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); in quirk_vt82c686_acpi()
1037 * 0x88 (128 bytes of power management registers)
1038 * 0xd0 (16 bytes of SMB registers)
1042 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); in quirk_vt8235_acpi()
1043 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); in quirk_vt8235_acpi()
1082 tmp = 0; /* nothing routed to external APIC */ in quirk_via_ioapic()
1084 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ in quirk_via_ioapic()
1089 /* Offset 0x58: External APIC IRQ output control */ in quirk_via_ioapic()
1090 pci_write_config_byte(dev, 0x58, tmp); in quirk_via_ioapic()
1106 pci_read_config_byte(dev, 0x5B, &misc_control2); in quirk_via_vt8237_bypass_apic_deassert()
1109 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); in quirk_via_vt8237_bypass_apic_deassert()
1126 if (dev->revision >= 0x02) { in quirk_amd_ioapic()
1139 if (dev->subsystem_device == 0xa118) in quirk_cavium_sriov_rnm_link()
1142 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1151 if (dev->subordinate && dev->revision <= 0x12) { in quirk_amd_8131_mmrbc()
1170 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ in quirk_via_acpi()
1171 pci_read_config_byte(d, 0x42, &irq); in quirk_via_acpi()
1172 irq &= 0xf; in quirk_via_acpi()
1245 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || in quirk_via_vlink()
1270 pci_write_config_byte(dev, 0xfc, 0); in quirk_vt82c598_id()
1283 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); in quirk_cardbus_legacy()
1300 pci_read_config_dword(dev, 0x4C, &pcic); in quirk_amd_ordering()
1304 pci_write_config_dword(dev, 0x4C, pcic); in quirk_amd_ordering()
1305 pci_read_config_dword(dev, 0x84, &pcic); in quirk_amd_ordering()
1307 pci_write_config_dword(dev, 0x84, pcic); in quirk_amd_ordering()
1325 r->start = 0; in quirk_dunord()
1326 r->end = 0xffffff; in quirk_dunord()
1333 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1352 pci_read_config_byte(dev, 0x41, ®); in quirk_mediagx_master()
1355 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", in quirk_mediagx_master()
1357 pci_write_config_byte(dev, 0x41, reg); in quirk_mediagx_master()
1372 if (pdev->revision != 0x04) /* Only C0 requires this */ in quirk_disable_pxb()
1374 pci_read_config_word(pdev, 0x40, &config); in quirk_disable_pxb()
1377 pci_write_config_word(pdev, 0x40, config); in quirk_disable_pxb()
1390 if (tmp == 0x01) { in quirk_amd_ide_mode()
1391 pci_read_config_byte(pdev, 0x40, &tmp); in quirk_amd_ide_mode()
1392 pci_write_config_byte(pdev, 0x40, tmp|1); in quirk_amd_ide_mode()
1393 pci_write_config_byte(pdev, 0x9, 1); in quirk_amd_ide_mode()
1394 pci_write_config_byte(pdev, 0xa, 6); in quirk_amd_ide_mode()
1395 pci_write_config_byte(pdev, 0x40, tmp); in quirk_amd_ide_mode()
1407 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1408 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1473 * package 2.7.0 for details)
1500 case 0x8025: /* P4B-LX */ in asus_hides_smbus_hostbridge()
1501 case 0x8070: /* P4B */ in asus_hides_smbus_hostbridge()
1502 case 0x8088: /* P4B533 */ in asus_hides_smbus_hostbridge()
1503 case 0x1626: /* L3C notebook */ in asus_hides_smbus_hostbridge()
1508 case 0x80b1: /* P4GE-V */ in asus_hides_smbus_hostbridge()
1509 case 0x80b2: /* P4PE */ in asus_hides_smbus_hostbridge()
1510 case 0x8093: /* P4B533-V */ in asus_hides_smbus_hostbridge()
1515 case 0x8030: /* P4T533 */ in asus_hides_smbus_hostbridge()
1520 case 0x8070: /* P4G8X Deluxe */ in asus_hides_smbus_hostbridge()
1525 case 0x80c9: /* PU-DLS */ in asus_hides_smbus_hostbridge()
1530 case 0x1751: /* M2N notebook */ in asus_hides_smbus_hostbridge()
1531 case 0x1821: /* M5N notebook */ in asus_hides_smbus_hostbridge()
1532 case 0x1897: /* A6L notebook */ in asus_hides_smbus_hostbridge()
1537 case 0x184b: /* W1N notebook */ in asus_hides_smbus_hostbridge()
1538 case 0x186a: /* M6Ne notebook */ in asus_hides_smbus_hostbridge()
1543 case 0x80f2: /* P4P800-X */ in asus_hides_smbus_hostbridge()
1548 case 0x1882: /* M6V notebook */ in asus_hides_smbus_hostbridge()
1549 case 0x1977: /* A6VA notebook */ in asus_hides_smbus_hostbridge()
1555 case 0x088C: /* HP Compaq nc8000 */ in asus_hides_smbus_hostbridge()
1556 case 0x0890: /* HP Compaq nc6000 */ in asus_hides_smbus_hostbridge()
1561 case 0x12bc: /* HP D330L */ in asus_hides_smbus_hostbridge()
1562 case 0x12bd: /* HP D530 */ in asus_hides_smbus_hostbridge()
1563 case 0x006a: /* HP Compaq nx9500 */ in asus_hides_smbus_hostbridge()
1568 case 0x12bf: /* HP xw4100 */ in asus_hides_smbus_hostbridge()
1574 case 0xC00C: /* Samsung P35 notebook */ in asus_hides_smbus_hostbridge()
1580 case 0x0058: /* Compaq Evo N620c */ in asus_hides_smbus_hostbridge()
1585 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ in asus_hides_smbus_hostbridge()
1593 case 0x00b8: /* Compaq Evo D510 CMT */ in asus_hides_smbus_hostbridge()
1594 case 0x00b9: /* Compaq Evo D510 SFF */ in asus_hides_smbus_hostbridge()
1595 case 0x00ba: /* Compaq Evo D510 USDT */ in asus_hides_smbus_hostbridge()
1605 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ in asus_hides_smbus_hostbridge()
1635 pci_read_config_word(dev, 0xF2, &val); in asus_hides_smbus_lpc()
1636 if (val & 0x8) { in asus_hides_smbus_lpc()
1637 pci_write_config_word(dev, 0xF2, val & (~0x8)); in asus_hides_smbus_lpc()
1638 pci_read_config_word(dev, 0xF2, &val); in asus_hides_smbus_lpc()
1639 if (val & 0x8) in asus_hides_smbus_lpc()
1640 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", in asus_hides_smbus_lpc()
1671 pci_read_config_dword(dev, 0xF0, &rcba); in asus_hides_smbus_lpc_ich6_suspend()
1673 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); in asus_hides_smbus_lpc_ich6_suspend()
1686 val = readl(asus_rcba_base + 0x3418); in asus_hides_smbus_lpc_ich6_resume_early()
1689 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); in asus_hides_smbus_lpc_ich6_resume_early()
1716 u8 val = 0; in quirk_sis_96x_smbus()
1717 pci_read_config_byte(dev, 0x77, &val); in quirk_sis_96x_smbus()
1718 if (val & 0x10) { in quirk_sis_96x_smbus()
1720 pci_write_config_byte(dev, 0x77, val & ~0x10); in quirk_sis_96x_smbus()
1740 #define SIS_DETECT_REGISTER 0x40
1750 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { in quirk_sis_503()
1775 int asus_hides_ac97 = 0; in asus_hides_ac97_lpc()
1785 pci_read_config_byte(dev, 0x50, &val); in asus_hides_ac97_lpc()
1786 if (val & 0xc0) { in asus_hides_ac97_lpc()
1787 pci_write_config_byte(dev, 0x50, val & (~0xc0)); in asus_hides_ac97_lpc()
1788 pci_read_config_byte(dev, 0x50, &val); in asus_hides_ac97_lpc()
1789 if (val & 0xc0) in asus_hides_ac97_lpc()
1790 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", in asus_hides_ac97_lpc()
1810 /* Only poke fn 0 */ in quirk_jmicron_ata()
1814 pci_read_config_dword(pdev, 0x40, &conf1); in quirk_jmicron_ata()
1815 pci_read_config_dword(pdev, 0x80, &conf5); in quirk_jmicron_ata()
1817 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ in quirk_jmicron_ata()
1825 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ in quirk_jmicron_ata()
1836 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ in quirk_jmicron_ata()
1837 /* Set the class codes correctly and then direct IDE 0 */ in quirk_jmicron_ata()
1838 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ in quirk_jmicron_ata()
1843 conf1 |= 0x00C00000; /* Set 22, 23 */ in quirk_jmicron_ata()
1847 pci_write_config_dword(pdev, 0x40, conf1); in quirk_jmicron_ata()
1848 pci_write_config_dword(pdev, 0x80, conf5); in quirk_jmicron_ata()
1852 pdev->hdr_type = hdr & 0x7f; in quirk_jmicron_ata()
1853 pdev->multifunction = !!(hdr & 0x80); in quirk_jmicron_ata()
1887 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, qu…
1888 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1889 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1896 if ((pdev->class >> 8) != 0xff00) in quirk_alder_ioapic()
1904 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) in quirk_alder_ioapic()
1905 insert_resource(&iomem_resource, &pdev->resource[0]); in quirk_alder_ioapic()
1912 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); in quirk_alder_ioapic()
1922 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi);
1923 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi);
1924 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi);
1925 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi);
1926 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi);
1927 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi);
1937 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch…
1958 if (pdev->revision != 0x21 && pdev->revision != 0x30) in quirk_huawei_pcie_sva()
1971 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva);
1972 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva);
1973 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva);
1974 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva);
1975 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva);
1976 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva);
2002 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
2003 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
2004 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
2005 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
2006 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
2007 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
2008 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
2009 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
2010 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
2011 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
2012 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
2013 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
2014 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
2015 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
2016 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
2017 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
2018 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
2019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
2020 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
2021 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
2022 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
2037 dev->subsystem_device == 0x00e2) in quirk_radeon_pm()
2040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
2068 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
2069 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
2070 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
2078 return 0; in dmi_disable_ioapicreroute()
2148 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
2151 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
2170 case 0x3c28: /* Xeon E5 1600/2600/4600 */ in quirk_disable_intel_boot_interrupt()
2171 case 0x0e28: /* Xeon E5/E7 V2 */ in quirk_disable_intel_boot_interrupt()
2172 case 0x2f28: /* Xeon E5/E7 V3,V4 */ in quirk_disable_intel_boot_interrupt()
2173 case 0x6f28: /* Xeon D-1500 */ in quirk_disable_intel_boot_interrupt()
2174 case 0x2034: /* Xeon Scalable Family */ in quirk_disable_intel_boot_interrupt()
2197 * Device 5 Func 0 Device IDs of Core IO modules/hubs
2203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
2205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
2207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
2209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
2211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
2213 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
2215 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
2217 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
2219 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
2221 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
2225 #define BC_HT1000_FEATURE_REG 0x64
2226 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2227 #define BC_HT1000_MAP_IDX 0xC00
2228 #define BC_HT1000_MAP_DATA 0xC01
2242 for (irq = 0x10; irq < 0x10 + 32; irq++) { in quirk_disable_broadcom_boot_interrupt()
2244 outb(0x00, BC_HT1000_MAP_DATA); in quirk_disable_broadcom_boot_interrupt()
2262 #define AMD_813X_MISC 0x40
2263 #define AMD_813X_NOIOAMODE (1<<0)
2264 #define AMD_813X_REV_B1 0x12
2265 #define AMD_813X_REV_B2 0x13
2289 #define AMD_8111_PCI_IRQ_ROUTING 0x56
2304 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); in quirk_disable_amd_8111_boot_interrupt()
2319 struct resource *r = &dev->resource[0]; in quirk_tc86c001_ide()
2321 if (r->start & 0x8) { in quirk_tc86c001_ide()
2323 r->start = 0; in quirk_tc86c001_ide()
2324 r->end = 0xf; in quirk_tc86c001_ide()
2335 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2345 for (bar = 0; bar <= 1; bar++) in quirk_plx_pci9050()
2346 if (pci_resource_len(dev, bar) == 0x80 && in quirk_plx_pci9050()
2347 (pci_resource_start(dev, bar) & 0x80)) { in quirk_plx_pci9050()
2352 r->start = 0; in quirk_plx_pci9050()
2353 r->end = 0xff; in quirk_plx_pci9050()
2359 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2360 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2361 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2362 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2364 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2367 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2368 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2372 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; in quirk_netmos()
2373 unsigned int num_serial = dev->subsystem_device & 0xf; in quirk_netmos()
2382 * The subdevice ID is of the form 0x00PS, where <P> is the number in quirk_netmos()
2389 dev->subsystem_device == 0x0299) in quirk_netmos()
2400 (dev->class & 0xff); in quirk_netmos()
2415 case 0x1029: in quirk_e100_interrupt()
2416 case 0x1030 ... 0x1034: in quirk_e100_interrupt()
2417 case 0x1038 ... 0x103E: in quirk_e100_interrupt()
2418 case 0x1050 ... 0x1057: in quirk_e100_interrupt()
2419 case 0x1059: in quirk_e100_interrupt()
2420 case 0x1064 ... 0x106B: in quirk_e100_interrupt()
2421 case 0x1091 ... 0x1095: in quirk_e100_interrupt()
2422 case 0x1209: in quirk_e100_interrupt()
2423 case 0x1229: in quirk_e100_interrupt()
2424 case 0x2449: in quirk_e100_interrupt()
2425 case 0x2459: in quirk_e100_interrupt()
2426 case 0x245D: in quirk_e100_interrupt()
2427 case 0x27DC: in quirk_e100_interrupt()
2442 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) in quirk_e100_interrupt()
2456 csr = ioremap(pci_resource_start(dev, 0), 8); in quirk_e100_interrupt()
2463 if (cmd_hi == 0) { in quirk_e100_interrupt()
2482 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2483 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2484 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2485 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2486 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2487 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2488 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2489 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2490 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2491 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2492 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2493 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2494 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2495 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2508 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2523 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link);
2524 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link);
2525 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link);
2549 pci_read_config_word(dev, 0x40, &en1k); in quirk_p64h2_1k_io()
2551 if (en1k & 0x200) { in quirk_p64h2_1k_io()
2556 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2567 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { in quirk_nvidia_ck804_pcie_aer_ext_cap()
2568 if (!(b & 0x20)) { in quirk_nvidia_ck804_pcie_aer_ext_cap()
2569 pci_write_config_byte(dev, 0xf41, b | 0x20); in quirk_nvidia_ck804_pcie_aer_ext_cap()
2584 * bus leading to USB2.0 packet loss. in quirk_via_cx700_pci_parking_caching()
2605 if (pci_read_config_byte(dev, 0x76, &b) == 0) { in quirk_via_cx700_pci_parking_caching()
2606 if (b & 0x40) { in quirk_via_cx700_pci_parking_caching()
2608 pci_write_config_byte(dev, 0x76, b ^ 0x40); in quirk_via_cx700_pci_parking_caching()
2614 if (pci_read_config_byte(dev, 0x72, &b) == 0) { in quirk_via_cx700_pci_parking_caching()
2615 if (b != 0) { in quirk_via_cx700_pci_parking_caching()
2617 pci_write_config_byte(dev, 0x72, 0x0); in quirk_via_cx700_pci_parking_caching()
2620 pci_write_config_byte(dev, 0x75, 0x1); in quirk_via_cx700_pci_parking_caching()
2623 pci_write_config_byte(dev, 0x77, 0x0); in quirk_via_cx700_pci_parking_caching()
2629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2635 pci_read_config_dword(dev, 0xf4, &rev); in quirk_brcm_5719_limit_mrrs()
2638 if (rev == 0x05719000) { in quirk_brcm_5719_limit_mrrs()
2658 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { in quirk_unhide_mch_dev6()
2660 pci_write_config_byte(dev, 0xF4, reg | 0x02); in quirk_unhide_mch_dev6()
2688 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2689 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi);
2700 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2701 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2713 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); in quirk_amd_780_apc_msi()
2715 if (apc_bridge->device == 0x9602) in quirk_amd_780_apc_msi()
2720 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2721 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2736 &flags) == 0) { in msi_ht_cap_enabled()
2740 return (flags & HT_MSI_FLAGS_ENABLE) != 0; in msi_ht_cap_enabled()
2746 return 0; in msi_ht_cap_enabled()
2770 pdev = pci_get_slot(dev->bus, 0); in quirk_nvidia_ck804_msi_ht_cap()
2790 &flags) == 0) { in ht_enable_msi_mapping()
2827 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device
2839 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2842 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2845 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2848 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2851 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2854 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2857 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2860 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2863 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2866 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2869 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2872 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2875 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2878 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a,
2881 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c,
2884 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e,
2905 pci_read_config_dword(dev, 0x74, &cfg); in nvbridge_check_legacy_irq_routing()
2910 pci_write_config_dword(dev, 0x74, cfg); in nvbridge_check_legacy_irq_routing()
2923 int found = 0; in ht_check_msi_mapping()
2933 &flags) == 0) { in ht_check_msi_mapping()
2953 int found = 0; in host_bridge_with_leaf()
2956 for (i = dev_no + 1; i < 0x20; i++) { in host_bridge_with_leaf()
2957 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); in host_bridge_with_leaf()
2963 if (pos != 0) { in host_bridge_with_leaf()
2985 int end = 0; in is_end_of_ht_chain()
3011 int found = 0; in nv_ht_enable_msi_mapping()
3014 for (i = dev_no; i >= 0; i--) { in nv_ht_enable_msi_mapping()
3015 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); in nv_ht_enable_msi_mapping()
3020 if (pos != 0) { in nv_ht_enable_msi_mapping()
3054 &flags) == 0) { in ht_disable_msi_mapping()
3078 if (found == 0) in __nv_msi_ht_cap_quirk()
3085 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, in __nv_msi_ht_cap_quirk()
3086 PCI_DEVFN(0, 0)); in __nv_msi_ht_cap_quirk()
3093 if (pos != 0) { in __nv_msi_ht_cap_quirk()
3125 return __nv_msi_ht_cap_quirk(dev, 0); in nv_msi_ht_cap_quirk_leaf()
3149 if ((p->revision < 0x3B) && (p->revision >= 0x30)) in quirk_msi_intx_disable_ati_bug()
3156 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ in quirk_msi_intx_disable_qca_bug()
3157 if (dev->revision < 0x18) { in quirk_msi_intx_disable_qca_bug()
3181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
3183 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
3185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
3187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
3189 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
3192 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
3194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
3196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
3199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
3201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
3203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
3205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
3207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
3209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
3211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
3213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
3215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
3217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
3219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
3237 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
3252 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3272 * live on PCI function 0, which might be the CardBus controller or the
3289 * This must be done via function #0 in ricoh_mmc_fixup_rl5c476()
3294 pci_read_config_byte(dev, 0xB7, &disable); in ricoh_mmc_fixup_rl5c476()
3295 if (disable & 0x02) in ricoh_mmc_fixup_rl5c476()
3298 pci_read_config_byte(dev, 0x8E, &write_enable); in ricoh_mmc_fixup_rl5c476()
3299 pci_write_config_byte(dev, 0x8E, 0xAA); in ricoh_mmc_fixup_rl5c476()
3300 pci_read_config_byte(dev, 0x8D, &write_target); in ricoh_mmc_fixup_rl5c476()
3301 pci_write_config_byte(dev, 0x8D, 0xB7); in ricoh_mmc_fixup_rl5c476()
3302 pci_write_config_byte(dev, 0xB7, disable | 0x02); in ricoh_mmc_fixup_rl5c476()
3303 pci_write_config_byte(dev, 0x8E, write_enable); in ricoh_mmc_fixup_rl5c476()
3304 pci_write_config_byte(dev, 0x8D, write_target); in ricoh_mmc_fixup_rl5c476()
3320 * This must be done via function #0 in ricoh_mmc_fixup_r5c832()
3325 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize in ricoh_mmc_fixup_r5c832()
3329 * 0x150 - SD2.0 mode enable for changing base clock in ricoh_mmc_fixup_r5c832()
3331 * 0xe1 - Base clock frequency in ricoh_mmc_fixup_r5c832()
3332 * 0x32 - 50Mhz new clock frequency in ricoh_mmc_fixup_r5c832()
3333 * 0xf9 - Key register for 0x150 in ricoh_mmc_fixup_r5c832()
3334 * 0xfc - key register for 0xe1 in ricoh_mmc_fixup_r5c832()
3338 pci_write_config_byte(dev, 0xf9, 0xfc); in ricoh_mmc_fixup_r5c832()
3339 pci_write_config_byte(dev, 0x150, 0x10); in ricoh_mmc_fixup_r5c832()
3340 pci_write_config_byte(dev, 0xf9, 0x00); in ricoh_mmc_fixup_r5c832()
3341 pci_write_config_byte(dev, 0xfc, 0x01); in ricoh_mmc_fixup_r5c832()
3342 pci_write_config_byte(dev, 0xe1, 0x32); in ricoh_mmc_fixup_r5c832()
3343 pci_write_config_byte(dev, 0xfc, 0x00); in ricoh_mmc_fixup_r5c832()
3348 pci_read_config_byte(dev, 0xCB, &disable); in ricoh_mmc_fixup_r5c832()
3350 if (disable & 0x02) in ricoh_mmc_fixup_r5c832()
3353 pci_read_config_byte(dev, 0xCA, &write_enable); in ricoh_mmc_fixup_r5c832()
3354 pci_write_config_byte(dev, 0xCA, 0x57); in ricoh_mmc_fixup_r5c832()
3355 pci_write_config_byte(dev, 0xCB, disable | 0x02); in ricoh_mmc_fixup_r5c832()
3356 pci_write_config_byte(dev, 0xCA, write_enable); in ricoh_mmc_fixup_r5c832()
3371 #define VTUNCERRMSK_REG 0x1ac
3390 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3391 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3403 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3420 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
3444 err = pci_read_config_word(dev, 0x48, &rcc); in quirk_intel_mc_errata()
3455 err = pci_write_config_word(dev, 0x48, rcc); in quirk_intel_mc_errata()
3464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3473 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3474 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3475 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3476 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3477 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3479 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3480 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3483 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3488 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3501 rc = pci_read_config_byte(dev, 0x00D0, &val); in quirk_intel_ntb()
3507 rc = pci_read_config_byte(dev, 0x00D1, &val); in quirk_intel_ntb()
3513 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3528 #define I915_DEIER_REG 0x4400c
3531 void __iomem *regs = pci_iomap(dev, 0, 0); in disable_igfx_irq()
3538 if (readl(regs + I915_DEIER_REG) != 0) { in disable_igfx_irq()
3541 writel(0, regs + I915_DEIER_REG); in disable_igfx_irq()
3546 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3547 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3548 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3549 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3550 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3551 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3552 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3560 dev->d3hot_delay = 0; in quirk_remove_d3hot_delay()
3563 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay);
3564 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay);
3565 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay);
3567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay);
3568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay);
3569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay);
3570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay);
3571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay);
3572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay);
3573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay);
3574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay);
3575 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay);
3576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay);
3577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay);
3579 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay);
3580 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay);
3581 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay);
3582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay);
3583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay);
3584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay);
3585 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay);
3586 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay);
3587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay);
3598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3600 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3602 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3621 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3627 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3628 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3631 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3633 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3671 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { in mellanox_check_broken_intx_masking()
3695 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); in mellanox_check_broken_intx_masking()
3704 fw_major = fw_maj_min & 0xffff; in mellanox_check_broken_intx_masking()
3706 fw_subminor = fw_sub_min & 0xffff; in mellanox_check_broken_intx_masking()
3734 if ((dev->device & 0xffc0) == 0x2340) in quirk_nvidia_no_bus_reset()
3747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3748 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3749 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3750 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3751 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3752 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
3759 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3769 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
3800 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset);
3801 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset);
3802 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset);
3803 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset);
3881 acpi_execute_simple_method(SXFP, NULL, 0); in quirk_apple_poweroff_thunderbolt()
3883 acpi_execute_simple_method(SXLV, NULL, 0); in quirk_apple_poweroff_thunderbolt()
3884 acpi_execute_simple_method(SXIO, NULL, 0); in quirk_apple_poweroff_thunderbolt()
3885 acpi_execute_simple_method(SXLV, NULL, 0); in quirk_apple_poweroff_thunderbolt()
3909 return 0; in reset_intel_82599_sfp_virtfn()
3912 #define SOUTH_CHICKEN2 0xc2004
3913 #define PCH_PP_STATUS 0xc7200
3914 #define PCH_PP_CONTROL 0xc7204
3915 #define MSG_CTL 0x45010
3916 #define NSDE_PWR_STATE 0xd0100
3926 return 0; in reset_ivb_igd()
3928 mmio_base = pci_iomap(dev, 0, 0); in reset_ivb_igd()
3932 iowrite32(0x00000002, mmio_base + MSG_CTL); in reset_ivb_igd()
3940 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); in reset_ivb_igd()
3942 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; in reset_ivb_igd()
3948 if ((val & 0xb0000000) == 0) in reset_ivb_igd()
3955 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); in reset_ivb_igd()
3958 return 0; in reset_ivb_igd()
3971 if ((dev->device & 0xf000) != 0x4000) in reset_chelsio_generic_dev()
3975 * If this is the "probe" phase, return 0 indicating that we can in reset_chelsio_generic_dev()
3979 return 0; in reset_chelsio_generic_dev()
4005 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) in reset_chelsio_generic_dev()
4020 return 0; in reset_chelsio_generic_dev()
4023 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
4024 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
4025 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
4047 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) in nvme_disable_and_flr()
4051 return 0; in nvme_disable_and_flr()
4053 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); in nvme_disable_and_flr()
4105 return 0; in nvme_disable_and_flr()
4124 return 0; in delay_250ms_after_flr()
4127 #define PCI_DEVICE_ID_HINIC_VF 0x375E
4128 #define HINIC_VF_FLR_TYPE 0x1000
4130 #define HINIC_VF_OP 0xE80
4142 return 0; in reset_hinic_vf_dev()
4144 bar = pci_iomap(pdev, 0, 0); in reset_hinic_vf_dev()
4167 pci_write_config_word(pdev, PCI_VENDOR_ID, 0); in reset_hinic_vf_dev()
4187 return 0; in reset_hinic_vf_dev()
4197 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
4198 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
4199 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr },
4200 { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr },
4205 { 0 }
4230 if (PCI_FUNC(dev->devfn) != 0) in quirk_dma_func0_alias()
4231 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); in quirk_dma_func0_alias()
4237 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
4240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
4254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4259 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
4261 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4264 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4278 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
4281 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4284 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
4287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235,
4294 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4296 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4303 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4304 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4315 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4323 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4324 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4325 .driver_data = PCI_DEVFN(1, 0) },
4326 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4327 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4328 .driver_data = PCI_DEVFN(1, 0) },
4329 { 0 }
4340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4360 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4363 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4365 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4367 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4369 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4379 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); in quirk_mic_x200_dma_alias()
4380 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); in quirk_mic_x200_dma_alias()
4381 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); in quirk_mic_x200_dma_alias()
4383 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4384 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4395 * All possible slot numbers (0x20) are used, since we are unable to tell
4402 const unsigned int num_pci_slots = 0x20; in quirk_pex_vca_alias()
4405 for (slot = 0; slot < num_pci_slots; slot++) in quirk_pex_vca_alias()
4406 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); in quirk_pex_vca_alias()
4408 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4409 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4410 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4411 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4412 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4413 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4426 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4438 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; in quirk_tw686x_class()
4442 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4444 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4446 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4448 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4467 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4469 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4471 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4473 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4475 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4477 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4479 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4481 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4483 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4485 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4487 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4489 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4491 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4493 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4495 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4497 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4499 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4501 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4503 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4505 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4507 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4509 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4511 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4513 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4515 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4517 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4519 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4521 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4533 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4535 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4537 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4541 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4576 PCI_EXP_DEVCTL_NOSNOOP_EN, 0); in quirk_disable_root_port_attributes()
4588 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely in quirk_chelsio_T5_disable_root_port_attributes()
4589 * 0x54xx so we use that one. in quirk_chelsio_T5_disable_root_port_attributes()
4591 if ((pdev->device & 0xff00) == 0x5400) in quirk_chelsio_T5_disable_root_port_attributes()
4606 * caller desires. Return 0 otherwise.
4612 return 0; in pci_acs_ctrl_enabled()
4651 status = acpi_get_table("IVRS", 0, &header); in pci_quirk_amd_sb_acs()
4676 case 0xa000 ... 0xa7ff: /* ThunderX1 */ in pci_quirk_cavium_acs_match()
4677 case 0xaf84: /* ThunderX2 */ in pci_quirk_cavium_acs_match()
4678 case 0xb884: /* ThunderX3 */ in pci_quirk_cavium_acs_match()
4730 case 0x0710 ... 0x071e: in pci_quirk_zhaoxin_pcie_ports_acs()
4731 case 0x0721: in pci_quirk_zhaoxin_pcie_ports_acs()
4732 case 0x0723 ... 0x0752: in pci_quirk_zhaoxin_pcie_ports_acs()
4748 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4749 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4751 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4752 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4754 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4755 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4757 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4758 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4760 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4761 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4763 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4764 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4766 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4768 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4769 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4771 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4782 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) in pci_quirk_intel_pch_acs_match()
4798 return pci_acs_ctrl_enabled(acs_flags, 0); in pci_quirk_intel_pch_acs()
4844 return acs_flags ? 0 : 1; in pci_quirk_al_acs()
4857 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4858 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4870 * 0xa290-0xa29f PCI Express Root port #{0-16}
4871 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4882 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4898 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ in pci_quirk_intel_spt_pch_acs_match()
4899 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ in pci_quirk_intel_spt_pch_acs_match()
4900 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ in pci_quirk_intel_spt_pch_acs_match()
4982 case 0x0100 ... 0x010F: in pci_quirk_wangxun_nic_acs()
4983 case 0x1001: in pci_quirk_wangxun_nic_acs()
4984 case 0x2001: in pci_quirk_wangxun_nic_acs()
4997 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4998 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4999 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
5000 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
5001 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
5002 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
5003 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
5004 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
5005 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
5006 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
5007 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
5008 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
5009 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
5010 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
5011 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
5012 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
5013 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
5014 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
5015 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
5016 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
5017 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
5018 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
5019 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
5020 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
5021 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
5022 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
5023 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
5024 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
5025 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
5026 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
5027 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
5029 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
5030 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
5031 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
5032 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
5033 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
5034 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
5035 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
5037 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
5038 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
5039 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
5040 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
5041 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
5042 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
5043 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
5044 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
5046 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
5047 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
5048 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
5050 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
5051 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
5052 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
5053 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
5055 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
5056 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
5057 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
5058 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
5060 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
5061 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
5064 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
5065 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
5067 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
5071 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
5072 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
5076 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
5077 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
5078 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
5080 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
5082 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
5083 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
5084 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
5085 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
5086 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
5087 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
5088 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
5089 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
5091 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
5092 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs },
5093 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs },
5094 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs },
5095 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
5097 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
5099 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
5100 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
5101 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
5104 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs },
5105 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs },
5106 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs },
5108 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs },
5109 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs },
5110 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs },
5112 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs },
5113 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs },
5114 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs },
5116 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs },
5117 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs },
5118 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs },
5120 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs },
5121 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs },
5122 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs },
5124 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
5125 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs },
5126 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs },
5128 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs },
5129 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs },
5130 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs },
5132 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs },
5133 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs },
5134 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
5139 { 0 }
5150 * 0: Device does not provide all the desired controls
5151 * >0: Device provides all the controls in @acs_flags
5170 if (ret >= 0) in pci_dev_specific_acs_enabled()
5179 #define INTEL_LPC_RCBA_REG 0xf0
5181 #define INTEL_LPC_RCBA_MASK 0xffffc000
5183 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
5186 #define INTEL_BSPR_REG 0x1104
5193 #define INTEL_UPDCR_REG 0x1014
5194 /* 5:0 Peer Decode Enable bits */
5195 #define INTEL_UPDCR_REG_MASK 0x3f
5207 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), in pci_quirk_enable_intel_lpc_acs()
5236 return 0; in pci_quirk_enable_intel_lpc_acs()
5240 #define INTEL_MPC_REG 0xd8
5276 return 0; in pci_quirk_enable_intel_pch_acs()
5285 return 0; in pci_quirk_enable_intel_pch_acs()
5315 return 0; in pci_quirk_enable_intel_spt_pch_acs()
5339 return 0; in pci_quirk_disable_intel_spt_pch_acs_redir()
5362 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { in pci_dev_specific_enable_acs()
5370 if (ret >= 0) in pci_dev_specific_enable_acs()
5383 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { in pci_dev_specific_disable_acs_redir()
5391 if (ret >= 0) in pci_dev_specific_disable_acs_redir()
5400 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5403 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5408 int pos, i = 0, ret; in quirk_intel_qat_vf_cap()
5424 * is not the expected incorrect 0x00. in quirk_intel_qat_vf_cap()
5431 * PCIe Capability Structure is expected to be at 0x50 and should in quirk_intel_qat_vf_cap()
5432 * terminate the list (Next Capability pointer is 0x00). Verify in quirk_intel_qat_vf_cap()
5438 pos = 0x50; in quirk_intel_qat_vf_cap()
5440 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { in quirk_intel_qat_vf_cap()
5467 state->cap.cap_extended = 0; in quirk_intel_qat_vf_cap()
5469 cap = (u16 *)&state->cap.data[0]; in quirk_intel_qat_vf_cap()
5480 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5485 * AMD Starship/Matisse HD Audio Controller 0x1487
5486 * AMD Starship USB 3.0 Host Controller 0x148c
5487 * AMD Matisse USB 3.0 Host Controller 0x149c
5488 * Intel 82579LM Gigabit Ethernet Controller 0x1502
5489 * Intel 82579V Gigabit Ethernet Controller 0x1503
5496 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
5497 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
5498 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
5499 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr);
5500 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
5501 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
5503 /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */
5506 if (dev->revision == 0x1) in quirk_no_flr_snet()
5509 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet);
5523 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5524 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5525 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5526 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5527 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5528 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5529 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5535 pdev->ats_cap = 0; in quirk_no_ats()
5545 if (pdev->device == 0x15d8) { in quirk_amd_harvest_no_ats()
5546 if (pdev->revision == 0xcf && in quirk_amd_harvest_no_ats()
5547 pdev->subsystem_vendor == 0xea50 && in quirk_amd_harvest_no_ats()
5548 (pdev->subsystem_device == 0xce19 || in quirk_amd_harvest_no_ats()
5549 pdev->subsystem_device == 0xcc10 || in quirk_amd_harvest_no_ats()
5550 pdev->subsystem_device == 0xcc08)) in quirk_amd_harvest_no_ats()
5558 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5560 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5562 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats);
5563 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
5564 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats);
5565 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats);
5566 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats);
5567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats);
5568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats);
5569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats);
5571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
5573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats);
5574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats);
5576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);
5584 if (pdev->revision < 0x20) in quirk_intel_e2000_no_ats()
5587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats);
5588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats);
5589 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats);
5590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats);
5591 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats);
5592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats);
5593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats);
5594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats);
5595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats);
5649 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); in quirk_gpu_hda()
5664 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); in quirk_gpu_usb()
5677 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5680 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); in quirk_gpu_usb_typec_ucsi()
5702 /* Bit 25 at offset 0x488 enables the HDA controller */ in quirk_nvidia_hda()
5703 pci_read_config_dword(gpu, 0x488, &val); in quirk_nvidia_hda()
5708 pci_write_config_dword(gpu, 0x488, val | BIT(25)); in quirk_nvidia_hda()
5712 gpu->multifunction = !!(hdr_type & 0x80); in quirk_nvidia_hda()
5721 * completions for config read requests even though PCIe r4.0, sec
5734 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5747 u16 ctrl = 0; in pci_idt_bus_quirk()
5765 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); in pci_idt_bus_quirk()
5795 mmio = pci_iomap(pdev, 0, 0); in quirk_switchtec_ntb_dma_alias()
5813 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { in quirk_switchtec_ntb_dma_alias()
5815 u32 table_sz = 0; in quirk_switchtec_ntb_dma_alias()
5827 pci_warn(pdev, "Partition %d table_sz 0\n", pp); in quirk_switchtec_ntb_dma_alias()
5838 for (te = 0; te < table_sz; te++) { in quirk_switchtec_ntb_dma_alias()
5843 devfn = (rid_entry >> 1) & 0xFF; in quirk_switchtec_ntb_dma_alias()
5858 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5859 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5860 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5861 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5862 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5863 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5864 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5865 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5866 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5867 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5868 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5869 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5870 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5871 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5872 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5873 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5874 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5875 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5876 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5877 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5878 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5879 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5880 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5881 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5882 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5883 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5884 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5885 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5886 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5887 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5888 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
5889 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
5890 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
5891 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
5892 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
5893 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
5894 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
5895 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
5896 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
5897 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
5898 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
5899 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
5900 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
5901 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
5902 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
5903 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
5904 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
5905 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
5906 SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */
5907 SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */
5908 SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */
5909 SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */
5910 SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */
5911 SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */
5912 SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */
5913 SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */
5914 SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */
5915 SWITCHTEC_QUIRK(0x5000); /* PFX 100XG5 */
5916 SWITCHTEC_QUIRK(0x5084); /* PFX 84XG5 */
5917 SWITCHTEC_QUIRK(0x5068); /* PFX 68XG5 */
5918 SWITCHTEC_QUIRK(0x5052); /* PFX 52XG5 */
5919 SWITCHTEC_QUIRK(0x5036); /* PFX 36XG5 */
5920 SWITCHTEC_QUIRK(0x5028); /* PFX 28XG5 */
5921 SWITCHTEC_QUIRK(0x5100); /* PSX 100XG5 */
5922 SWITCHTEC_QUIRK(0x5184); /* PSX 84XG5 */
5923 SWITCHTEC_QUIRK(0x5168); /* PSX 68XG5 */
5924 SWITCHTEC_QUIRK(0x5152); /* PSX 52XG5 */
5925 SWITCHTEC_QUIRK(0x5136); /* PSX 36XG5 */
5926 SWITCHTEC_QUIRK(0x5128); /* PSX 28XG5 */
5927 SWITCHTEC_QUIRK(0x5200); /* PAX 100XG5 */
5928 SWITCHTEC_QUIRK(0x5284); /* PAX 84XG5 */
5929 SWITCHTEC_QUIRK(0x5268); /* PAX 68XG5 */
5930 SWITCHTEC_QUIRK(0x5252); /* PAX 52XG5 */
5931 SWITCHTEC_QUIRK(0x5236); /* PAX 36XG5 */
5932 SWITCHTEC_QUIRK(0x5228); /* PAX 28XG5 */
5933 SWITCHTEC_QUIRK(0x5300); /* PFXA 100XG5 */
5934 SWITCHTEC_QUIRK(0x5384); /* PFXA 84XG5 */
5935 SWITCHTEC_QUIRK(0x5368); /* PFXA 68XG5 */
5936 SWITCHTEC_QUIRK(0x5352); /* PFXA 52XG5 */
5937 SWITCHTEC_QUIRK(0x5336); /* PFXA 36XG5 */
5938 SWITCHTEC_QUIRK(0x5328); /* PFXA 28XG5 */
5939 SWITCHTEC_QUIRK(0x5400); /* PSXA 100XG5 */
5940 SWITCHTEC_QUIRK(0x5484); /* PSXA 84XG5 */
5941 SWITCHTEC_QUIRK(0x5468); /* PSXA 68XG5 */
5942 SWITCHTEC_QUIRK(0x5452); /* PSXA 52XG5 */
5943 SWITCHTEC_QUIRK(0x5436); /* PSXA 36XG5 */
5944 SWITCHTEC_QUIRK(0x5428); /* PSXA 28XG5 */
5945 SWITCHTEC_QUIRK(0x5500); /* PAXA 100XG5 */
5946 SWITCHTEC_QUIRK(0x5584); /* PAXA 84XG5 */
5947 SWITCHTEC_QUIRK(0x5568); /* PAXA 68XG5 */
5948 SWITCHTEC_QUIRK(0x5552); /* PAXA 52XG5 */
5949 SWITCHTEC_QUIRK(0x5536); /* PAXA 36XG5 */
5950 SWITCHTEC_QUIRK(0x5528); /* PAXA 28XG5 */
5962 pci_add_dma_alias(pdev, 0, 256); in quirk_plx_ntb_dma_alias()
5964 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
5965 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
5989 pdev->subsystem_device != 0x222e || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
6000 map = pci_iomap(pdev, 0, 0x23000); in quirk_reset_lenovo_thinkpad_p50_nvgpu()
6010 if (ioread32(map + 0x2240c) & 0x2) { in quirk_reset_lenovo_thinkpad_p50_nvgpu()
6013 if (ret < 0) in quirk_reset_lenovo_thinkpad_p50_nvgpu()
6021 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
6034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
6037 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
6053 dev->pme_support = 0; in pci_fixup_no_msi_no_pme()
6055 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme);
6056 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme);
6062 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
6074 #define PI7C9X2Gxxx_MODE_REG 0x74
6075 #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0)
6107 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404,
6109 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404,
6111 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304,
6113 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304,
6115 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303,
6117 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303,
6124 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
6131 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect);
6132 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect);
6133 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect);
6134 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect);
6150 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", in aspm_l1_acceptable_latency()
6154 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency);
6155 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency);
6156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency);
6157 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency);
6158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency);
6159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency);
6160 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency);
6161 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency);
6162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency);
6163 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency);
6164 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency);
6165 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency);
6166 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency);
6167 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency);
6168 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency);
6169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency);
6170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency);
6171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency);
6172 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency);
6173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency);
6174 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency);
6175 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency);
6176 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency);
6177 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency);
6178 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
6179 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
6205 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
6206 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
6207 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
6208 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
6209 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size);
6210 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size);
6211 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size);
6212 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size);
6213 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
6214 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
6215 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
6216 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size);
6217 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size);
6218 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
6219 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
6220 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
6231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);
6232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
6233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
6245 DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec);