Lines Matching +full:pci +full:- +full:host +full:- +full:cam +full:- +full:generic
1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
11 * Init/reset quirks for USB host controllers should be in the USB quirks
19 #include <linux/pci.h>
20 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
34 #include "pci.h"
41 * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 >
88 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) in pcie_failed_link_retrain()
95 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); in pcie_failed_link_retrain()
157 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
158 f->class == (u32) PCI_ANY_ID) && in pci_do_fixups()
159 (f->vendor == dev->vendor || in pci_do_fixups()
160 f->vendor == (u16) PCI_ANY_ID) && in pci_do_fixups()
161 (f->device == dev->device || in pci_do_fixups()
162 f->device == (u16) PCI_ANY_ID)) { in pci_do_fixups()
165 hook = offset_to_ptr(&f->hook_offset); in pci_do_fixups()
167 hook = f->hook; in pci_do_fixups()
256 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); in pci_apply_final_quirks()
263 * value shared by all PCI devices. If there's a in pci_apply_final_quirks()
281 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, in pci_apply_final_quirks()
291 * Decoding should be disabled for a PCI device during BAR sizing to avoid
292 * conflict. But doing so may cause problems on host bridge and perhaps other
293 * key system devices. For devices that need to have mmio decoding always-on,
294 * we need to set the dev->mmio_always_on bit.
298 dev->mmio_always_on = 1; in quirk_mmio_always_on()
339 * contacts at VIA ask them for me please -- Alan
386 /* Chipsets where PCI->PCI transfers vanish or hang */
390 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); in quirk_nopcipci()
403 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); in quirk_nopciamd()
413 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_triton()
423 * VIA Apollo KT133 needs PCI latency patch
424 * Made according to a Windows driver-based patch by George E. Breese;
425 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
426 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
445 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; in quirk_vialatency()
449 if (p->revision < 0x40 || p->revision > 0x42) in quirk_vialatency()
457 if (p->revision < 0x10 || p->revision > 0x12) in quirk_vialatency()
462 * Ok we have the problem. Now set the PCI master grant to occur in quirk_vialatency()
463 * every master grant. The apparent bug is that under high PCI load in quirk_vialatency()
477 * "Master priority rotation on every PCI master grant" in quirk_vialatency()
498 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_viaetbf()
507 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_vsfx()
521 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_alimagik()
532 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_natoma()
544 * This chip can cause PCI parity errors if config register 0xA0 is read
549 dev->cfg_size = 0xA0; in quirk_citrine()
559 dev->cfg_size = 0x600; in quirk_nfp6000()
572 struct resource *r = &dev->resource[i]; in quirk_extend_bar_to_page()
574 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { in quirk_extend_bar_to_page()
575 r->end = PAGE_SIZE - 1; in quirk_extend_bar_to_page()
576 r->start = 0; in quirk_extend_bar_to_page()
577 r->flags |= IORESOURCE_UNSET; in quirk_extend_bar_to_page()
587 * If it's needed, re-allocate the region.
591 struct resource *r = &dev->resource[0]; in quirk_s3_64M()
593 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { in quirk_s3_64M()
594 r->flags |= IORESOURCE_UNSET; in quirk_s3_64M()
595 r->start = 0; in quirk_s3_64M()
596 r->end = 0x3ffffff; in quirk_s3_64M()
607 struct resource *res = dev->resource + pos; in quirk_io()
614 res->name = pci_name(dev); in quirk_io()
615 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; in quirk_io()
616 res->flags |= in quirk_io()
618 region &= ~(size - 1); in quirk_io()
620 /* Convert from PCI bus to resource space */ in quirk_io()
622 bus_region.end = region + size - 1; in quirk_io()
623 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io()
631 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
635 * CS553x's ISA PCI BARs may also be read-only (ref:
636 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
657 struct resource *res = dev->resource + nr; in quirk_io_region()
660 region &= ~(size - 1); in quirk_io_region()
665 res->name = pci_name(dev); in quirk_io_region()
666 res->flags = IORESOURCE_IO; in quirk_io_region()
668 /* Convert from PCI bus to resource space */ in quirk_io_region()
670 bus_region.end = region + size - 1; in quirk_io_region()
671 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io_region()
679 * between 0x3b0->0x3bb or read 0x3d3
697 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
698 * defines as "USB device (not host controller)". The dwc3 driver can then
703 u32 class = pdev->class; in quirk_amd_dwc_class()
706 /* Use "USB Device (not host controller)" class */ in quirk_amd_dwc_class()
707 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_amd_dwc_class()
709 "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", in quirk_amd_dwc_class()
710 class, pdev->class); in quirk_amd_dwc_class()
719 * Synopsys USB 3.x host HAPS platform has a class code of
721 * devices should use dwc3-haps driver. Change these devices' class code to
722 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
727 u32 class = pdev->class; in quirk_synopsys_haps()
729 switch (pdev->device) { in quirk_synopsys_haps()
733 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_synopsys_haps()
734 …pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhc… in quirk_synopsys_haps()
735 class, pdev->class); in quirk_synopsys_haps()
782 base &= -size; in piix4_io_quirk()
783 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); in piix4_io_quirk()
808 base &= -size; in piix4_mem_quirk()
809 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); in piix4_mem_quirk()
861 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
935 base &= ~(size-1); in ich6_lpc_generic_decode()
941 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); in ich6_lpc_generic_decode()
949 /* ICH6-specific generic IO decode */ in quirk_ich6_lpc()
950 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); in quirk_ich6_lpc()
951 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); in quirk_ich6_lpc()
968 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ in ich7_lpc_generic_decode()
980 /* ICH7-10 has the same common LPC generic IO decode registers */
986 /* And have 4 ICH7+ generic decodes */ in quirk_ich7_lpc()
987 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); in quirk_ich7_lpc()
988 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); in quirk_ich7_lpc()
989 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); in quirk_ich7_lpc()
990 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); in quirk_ich7_lpc()
1012 if (dev->revision & 0x10) in quirk_vt82c586_acpi()
1029 "vt82c686 HW-mon"); in quirk_vt82c686_acpi()
1048 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
1049 * back-to-back: Disable fast back-to-back on the secondary bus segment
1056 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); in quirk_xio2000a()
1057 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { in quirk_xio2000a()
1071 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
1074 * TODO: When we have device-specific interrupt routers, this code will go
1084 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ in quirk_via_ioapic()
1096 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
1108 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); in quirk_via_vt8237_bypass_apic_deassert()
1116 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1126 if (dev->revision >= 0x02) { in quirk_amd_ioapic()
1138 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ in quirk_cavium_sriov_rnm_link()
1139 if (dev->subsystem_device == 0xa118) in quirk_cavium_sriov_rnm_link()
1140 dev->sriov->link = dev->devfn; in quirk_cavium_sriov_rnm_link()
1147 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1151 if (dev->subordinate && dev->revision <= 0x12) { in quirk_amd_8131_mmrbc()
1152 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", in quirk_amd_8131_mmrbc()
1153 dev->revision); in quirk_amd_8131_mmrbc()
1154 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; in quirk_amd_8131_mmrbc()
1164 * -jgarzik
1170 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ in quirk_via_acpi()
1174 d->irq = irq; in quirk_via_acpi()
1180 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1185 switch (dev->device) { in quirk_via_bridge()
1188 * The VT82C686 is special; it attaches to PCI and can have in quirk_via_bridge()
1192 via_vlink_dev_lo = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1193 via_vlink_dev_hi = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1220 * quirk_via_vlink - VIA VLink IRQ number update
1221 * @dev: PCI device
1224 * the IRQ line register which usually is not relevant for PCI cards, is
1235 if (via_vlink_dev_lo == -1) in quirk_via_vlink()
1238 new_irq = dev->irq; in quirk_via_vlink()
1245 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || in quirk_via_vlink()
1246 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) in quirk_via_vlink()
1271 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); in quirk_vt82c598_id()
1291 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1303 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); in quirk_amd_ordering()
1314 * DreamWorks-provided workaround for Dunord I-3000 problem
1322 struct resource *r = &dev->resource[1]; in quirk_dunord()
1324 r->flags |= IORESOURCE_UNSET; in quirk_dunord()
1325 r->start = 0; in quirk_dunord()
1326 r->end = 0xffffff; in quirk_dunord()
1331 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1333 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1337 dev->transparent = 1; in quirk_transparent_bridge()
1343 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1344 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1372 if (pdev->revision != 0x04) /* Only C0 requires this */ in quirk_disable_pxb()
1378 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); in quirk_disable_pxb()
1386 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ in quirk_amd_ide_mode()
1397 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; in quirk_amd_ide_mode()
1417 pdev->class &= ~5; in quirk_svwks_csb5ide()
1419 /* PCI layer will sort out resources */ in quirk_svwks_csb5ide()
1424 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1434 pdev->class &= ~5; in quirk_ide_samemode()
1443 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; in quirk_no_ata_d3()
1459 * This was originally an Alpha-specific thing, but it really fits here.
1460 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1464 dev->class = PCI_CLASS_BRIDGE_EISA << 8; in quirk_eisa_bridge()
1469 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1471 * users to be irritated by just another PCI Device in the Win98 device
1475 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1477 * becomes necessary to do this tweak in two steps -- the chosen trigger
1478 * is either the Host bridge (preferred) or on-board VGA controller.
1491 * the DSDT and double-check that there is no code accessing the SMBus.
1497 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_smbus_hostbridge()
1498 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) in asus_hides_smbus_hostbridge()
1499 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1500 case 0x8025: /* P4B-LX */ in asus_hides_smbus_hostbridge()
1506 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) in asus_hides_smbus_hostbridge()
1507 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1508 case 0x80b1: /* P4GE-V */ in asus_hides_smbus_hostbridge()
1510 case 0x8093: /* P4B533-V */ in asus_hides_smbus_hostbridge()
1513 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) in asus_hides_smbus_hostbridge()
1514 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1518 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) in asus_hides_smbus_hostbridge()
1519 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1523 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) in asus_hides_smbus_hostbridge()
1524 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1525 case 0x80c9: /* PU-DLS */ in asus_hides_smbus_hostbridge()
1528 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) in asus_hides_smbus_hostbridge()
1529 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1535 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1536 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1541 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1542 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1543 case 0x80f2: /* P4P800-X */ in asus_hides_smbus_hostbridge()
1546 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) in asus_hides_smbus_hostbridge()
1547 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1552 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { in asus_hides_smbus_hostbridge()
1553 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1554 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1559 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1560 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1566 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) in asus_hides_smbus_hostbridge()
1567 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1571 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { in asus_hides_smbus_hostbridge()
1572 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1573 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1577 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { in asus_hides_smbus_hostbridge()
1578 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1579 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1583 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) in asus_hides_smbus_hostbridge()
1584 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1585 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ in asus_hides_smbus_hostbridge()
1586 /* Motherboard doesn't have Host bridge in asus_hides_smbus_hostbridge()
1588 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1591 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) in asus_hides_smbus_hostbridge()
1592 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1596 /* Motherboard doesn't have Host bridge in asus_hides_smbus_hostbridge()
1597 * subvendor/subdevice IDs and on-board VGA in asus_hides_smbus_hostbridge()
1603 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) in asus_hides_smbus_hostbridge()
1604 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1606 /* Motherboard doesn't have host bridge in asus_hides_smbus_hostbridge()
1608 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1760 dev->device = devid; in quirk_sis_503()
1768 * and MC97 modem controller are disabled when a second PCI soundcard is
1770 * -- bjd
1777 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_ac97_lpc()
1778 if (dev->device == PCI_DEVICE_ID_VIA_8237) in asus_hides_ac97_lpc()
1803 * early on to make the additional device appear during the PCI scanning.
1811 if (PCI_FUNC(pdev->devfn)) in quirk_jmicron_ata()
1817 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ in quirk_jmicron_ata()
1820 switch (pdev->device) { in quirk_jmicron_ata()
1852 pdev->hdr_type = hdr & 0x7f; in quirk_jmicron_ata()
1853 pdev->multifunction = !!(hdr & 0x80); in quirk_jmicron_ata()
1856 pdev->class = class >> 8; in quirk_jmicron_ata()
1881 if (dev->multifunction) { in quirk_jmicron_async_suspend()
1882 device_disable_async_suspend(&dev->dev); in quirk_jmicron_async_suspend()
1883 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); in quirk_jmicron_async_suspend()
1896 if ((pdev->class >> 8) != 0xff00) in quirk_alder_ioapic()
1900 * The first BAR is the location of the IO-APIC... we must in quirk_alder_ioapic()
1905 insert_resource(&iomem_resource, &pdev->resource[0]); in quirk_alder_ioapic()
1912 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); in quirk_alder_ioapic()
1920 dev->no_msi = 1; in quirk_no_msi()
1931 pdev->no_msi = 1; in quirk_pcie_mch()
1940 * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are
1941 * actually on the AMBA bus. These fake PCI devices can support SVA via
1942 * SMMU stall feature, by setting dma-can-stall for ACPI platforms.
1944 * Normally stalling must not be enabled for PCI devices, since it would
1945 * break the PCI requirement for free-flowing writes and may lead to
1946 * deadlock. We expect PCI devices to support ATS and PRI if they want to
1947 * be fault-tolerant, so there's no ACPI binding to describe anything else,
1948 * even when a "PCI" device turns out to be a regular old SoC device
1954 PROPERTY_ENTRY_BOOL("dma-can-stall"), in quirk_huawei_pcie_sva()
1958 if (pdev->revision != 0x21 && pdev->revision != 0x30) in quirk_huawei_pcie_sva()
1961 pdev->pasid_no_tlp = 1; in quirk_huawei_pcie_sva()
1964 * Set the dma-can-stall property on ACPI platforms. Device tree in quirk_huawei_pcie_sva()
1967 if (!pdev->dev.of_node && in quirk_huawei_pcie_sva()
1968 device_create_managed_software_node(&pdev->dev, properties, NULL)) in quirk_huawei_pcie_sva()
1980 * together on certain PXH-based systems.
1984 dev->no_msi = 1; in quirk_pcie_pxh()
1994 * Some Intel PCI Express chipsets have trouble with downstream device
2000 dev->no_d1d2 = 1; in quirk_intel_pcie_pm()
2026 if (dev->d3hot_delay >= delay) in quirk_d3hot_delay()
2029 dev->d3hot_delay = delay; in quirk_d3hot_delay()
2030 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", in quirk_d3hot_delay()
2031 dev->d3hot_delay); in quirk_d3hot_delay()
2036 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && in quirk_radeon_pm()
2037 dev->subsystem_device == 0x00e2) in quirk_radeon_pm()
2043 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus
2060 * to be ineffective on the platforms in question; the PCI device appears to
2061 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
2076 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); in dmi_disable_ioapicreroute()
2087 .ident = "ASUSTek Computer INC. M2N-LR",
2090 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
2099 * that a PCI device's interrupt handler is installed on the boot interrupt
2108 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; in quirk_reroute_to_boot_interrupts_intel()
2110 dev->vendor, dev->device); in quirk_reroute_to_boot_interrupts_intel()
2135 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
2136 * 300641-004US, section 5.7.3.
2138 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
2139 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
2140 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
2141 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
2142 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
2143 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
2144 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
2145 * Core IO on Xeon D-1500, see Intel order no 332051-001.
2162 switch (dev->device) { in quirk_disable_intel_boot_interrupt()
2173 case 0x6f28: /* Xeon D-1500 */ in quirk_disable_intel_boot_interrupt()
2185 dev->vendor, dev->device); in quirk_disable_intel_boot_interrupt()
2188 * Device 29 Func 5 Device IDs of IO-APIC
2224 /* Disable boot interrupts on HT-1000 */
2250 dev->vendor, dev->device); in quirk_disable_broadcom_boot_interrupt()
2259 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2273 if ((dev->revision == AMD_813X_REV_B1) || in quirk_disable_amd_813x_boot_interrupt()
2274 (dev->revision == AMD_813X_REV_B2)) in quirk_disable_amd_813x_boot_interrupt()
2282 dev->vendor, dev->device); in quirk_disable_amd_813x_boot_interrupt()
2301 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2306 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2313 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2315 * Re-allocate the region if needed...
2319 struct resource *r = &dev->resource[0]; in quirk_tc86c001_ide()
2321 if (r->start & 0x8) { in quirk_tc86c001_ide()
2322 r->flags |= IORESOURCE_UNSET; in quirk_tc86c001_ide()
2323 r->start = 0; in quirk_tc86c001_ide()
2324 r->end = 0xf; in quirk_tc86c001_ide()
2332 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2336 * Re-allocate the regions to a 256-byte boundary if necessary.
2342 /* Fixed in revision 2 (PCI 9052). */ in quirk_plx_pci9050()
2343 if (dev->revision >= 2) in quirk_plx_pci9050()
2348 struct resource *r = &dev->resource[bar]; in quirk_plx_pci9050()
2349 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", in quirk_plx_pci9050()
2351 r->flags |= IORESOURCE_UNSET; in quirk_plx_pci9050()
2352 r->start = 0; in quirk_plx_pci9050()
2353 r->end = 0xff; in quirk_plx_pci9050()
2360 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2372 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; in quirk_netmos()
2373 unsigned int num_serial = dev->subsystem_device & 0xf; in quirk_netmos()
2385 switch (dev->device) { in quirk_netmos()
2388 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && in quirk_netmos()
2389 dev->subsystem_device == 0x0299) in quirk_netmos()
2398 dev->device, num_parallel, num_serial); in quirk_netmos()
2399 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | in quirk_netmos()
2400 (dev->class & 0xff); in quirk_netmos()
2413 switch (dev->device) { in quirk_e100_interrupt()
2414 /* PCI IDs taken from drivers/net/e100.c */ in quirk_e100_interrupt()
2438 * re-enable them when it's ready. in quirk_e100_interrupt()
2449 if (dev->pm_cap) { in quirk_e100_interrupt()
2450 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in quirk_e100_interrupt()
2455 /* Convert from PCI bus to resource space. */ in quirk_e100_interrupt()
2504 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2511 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2520 dev->clear_retrain_link = 1; in quirk_enable_clear_retrain_link()
2529 u32 class = dev->class; in fixup_rev1_53c810()
2538 dev->class = PCI_CLASS_STORAGE_SCSI << 8; in fixup_rev1_53c810()
2539 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", in fixup_rev1_53c810()
2540 class, dev->class); in fixup_rev1_53c810()
2553 dev->io_window_1k = 1; in quirk_p64h2_1k_io()
2582 * Disable PCI Bus Parking and PCI Master read caching on CX700 in quirk_via_cx700_pci_parking_caching()
2583 * which causes unspecified timing errors with a VT6212L on the PCI in quirk_via_cx700_pci_parking_caching()
2586 * This quirk is only enabled if a second (on the external PCI bus) in quirk_via_cx700_pci_parking_caching()
2587 * VT6212L is found -- the CX700 core itself also contains a USB in quirk_via_cx700_pci_parking_caching()
2588 * host controller with the same PCI ID as the VT6212L. in quirk_via_cx700_pci_parking_caching()
2597 * p should contain the first (internal) VT6212L -- see if we have in quirk_via_cx700_pci_parking_caching()
2607 /* Turn off PCI Bus Parking */ in quirk_via_cx700_pci_parking_caching()
2610 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); in quirk_via_cx700_pci_parking_caching()
2616 /* Turn off PCI Master read caching */ in quirk_via_cx700_pci_parking_caching()
2619 /* Set PCI Master Bus time-out to "1x16 PCLK" */ in quirk_via_cx700_pci_parking_caching()
2625 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); in quirk_via_cx700_pci_parking_caching()
2651 * DRBs - this is where we expose device 6.
2652 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2694 if (dev->subordinate) { in quirk_disable_msi()
2696 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_disable_msi()
2706 * we use the possible vendor/device IDs of the host bridge for the
2713 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); in quirk_amd_780_apc_msi()
2715 if (apc_bridge->device == 0x9602) in quirk_amd_780_apc_msi()
2732 while (pos && ttl--) { in msi_ht_cap_enabled()
2770 pdev = pci_get_slot(dev->bus, 0); in quirk_nvidia_ck804_msi_ht_cap()
2786 while (pos && ttl--) { in ht_enable_msi_mapping()
2807 * The P5N32-SLI motherboards from Asus have a problem with MSI
2816 (strstr(board_name, "P5N32-SLI PREMIUM") || in nvenet_msi_disable()
2817 strstr(board_name, "P5N32-E SLI"))) { in nvenet_msi_disable()
2818 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); in nvenet_msi_disable()
2819 dev->no_msi = 1; in nvenet_msi_disable()
2827 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device
2832 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2837 dev->no_msi = 1; in pci_quirk_nvidia_tegra_disable_rp_msi()
2927 while (pos && ttl--) { in ht_check_msi_mapping()
2955 dev_no = host_bridge->devfn >> 3; in host_bridge_with_leaf()
2957 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); in host_bridge_with_leaf()
2961 /* found next host bridge? */ in host_bridge_with_leaf()
3013 dev_no = dev->devfn >> 3; in nv_ht_enable_msi_mapping()
3014 for (i = dev_no; i >= 0; i--) { in nv_ht_enable_msi_mapping()
3015 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); in nv_ht_enable_msi_mapping()
3050 while (pos && ttl--) { in ht_disable_msi_mapping()
3083 * a non-HyperTransport host bridge. Locate the host bridge. in __nv_msi_ht_cap_quirk()
3085 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, in __nv_msi_ht_cap_quirk()
3088 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); in __nv_msi_ht_cap_quirk()
3094 /* Host bridge is to HT */ in __nv_msi_ht_cap_quirk()
3109 /* Host bridge is not to HT, disable HT MSI mapping on this device */ in __nv_msi_ht_cap_quirk()
3132 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_bug()
3141 * we need check PCI REVISION ID of SMBus controller to get SB700 in quirk_msi_intx_disable_ati_bug()
3149 if ((p->revision < 0x3B) && (p->revision >= 0x30)) in quirk_msi_intx_disable_ati_bug()
3150 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_ati_bug()
3157 if (dev->revision < 0x18) { in quirk_msi_intx_disable_qca_bug()
3159 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_qca_bug()
3223 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3227 * tested), since currently there is no standard way to disable only MSI-X.
3234 dev->no_msi = 1; in quirk_al_msi_disable()
3235 pci_warn(dev, "Disabling MSI/MSI-X\n"); in quirk_al_msi_disable()
3242 * Allow manual resource allocation for PCI hotplug bridges via
3243 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3245 * allocate resources when hotplug device is inserted and PCI bus is
3250 dev->is_hotplug_bridge = 1; in quirk_hotplug_bridge()
3265 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3267 * MMC controller - so the SDHCI driver never sees them.
3271 * case that the relevant PCI registers to deactivate the MMC controller
3272 * live on PCI function 0, which might be the CardBus controller or the
3276 * other PCI functions shift up one level, e.g. function #2 becomes function
3277 * #1, and this will confuse the PCI core.
3291 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_rl5c476()
3322 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_r5c832()
3329 * 0x150 - SD2.0 mode enable for changing base clock in ricoh_mmc_fixup_r5c832()
3331 * 0xe1 - Base clock frequency in ricoh_mmc_fixup_r5c832()
3332 * 0x32 - 50Mhz new clock frequency in ricoh_mmc_fixup_r5c832()
3333 * 0xf9 - Key register for 0x150 in ricoh_mmc_fixup_r5c832()
3334 * 0xfc - key register for 0xe1 in ricoh_mmc_fixup_r5c832()
3336 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || in ricoh_mmc_fixup_r5c832()
3337 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { in ricoh_mmc_fixup_r5c832()
3374 * This is a quirk for masking VT-d spec-defined errors to platform error
3377 * on the RAS config settings of the platform) when a VT-d fault happens.
3380 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3396 u32 class = dev->class; in fixup_ti816x_class()
3399 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; in fixup_ti816x_class()
3400 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", in fixup_ti816x_class()
3401 class, dev->class); in fixup_ti816x_class()
3412 dev->pcie_mpss = 1; /* 256 bytes */ in fixup_mpss_256()
3427 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3463 /* Intel 5000 series memory controllers and ports 2-7 */
3478 /* Intel 5100 series memory controllers and ports 2-7 */
3505 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3511 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3520 * and the interrupt ends up -somewhere-.
3533 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); in disable_igfx_irq()
3555 * PCI devices which are on Intel chips can skip the 10ms delay
3560 dev->d3hot_delay = 0; in quirk_remove_d3hot_delay()
3566 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3596 dev->broken_intx_masking = 1; in quirk_broken_intx_masking()
3600 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3606 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3607 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3609 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3616 * DisINTx can be set but the interrupt status bit is non-functional.
3656 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3672 if (pdev->device == mellanox_broken_intx_devs[i]) { in mellanox_check_broken_intx_masking()
3673 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3679 * Getting here means Connect-IB cards and up. Connect-IB has no INTx in mellanox_check_broken_intx_masking()
3682 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) in mellanox_check_broken_intx_masking()
3685 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && in mellanox_check_broken_intx_masking()
3686 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) in mellanox_check_broken_intx_masking()
3689 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ in mellanox_check_broken_intx_masking()
3697 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); in mellanox_check_broken_intx_masking()
3709 …pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW… in mellanox_check_broken_intx_masking()
3710 fw_major, fw_minor, fw_subminor, pdev->device == in mellanox_check_broken_intx_masking()
3712 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3725 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; in quirk_no_bus_reset()
3734 if ((dev->device & 0xffc0) == 0x2340) in quirk_nvidia_no_bus_reset()
3742 * The device will throw a Link Down error on AER-capable systems and
3777 if (!pci_is_root_bus(dev->bus)) in quirk_no_pm_reset()
3778 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; in quirk_no_pm_reset()
3782 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3783 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3793 * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset
3794 * (i.e., they advertise NoSoftRst-). However, this transition does not have
3812 if (pdev->is_hotplug_bridge && in quirk_thunderbolt_hotplug_msi()
3813 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || in quirk_thunderbolt_hotplug_msi()
3814 pdev->revision <= 1)) in quirk_thunderbolt_hotplug_msi()
3815 pdev->no_msi = 1; in quirk_thunderbolt_hotplug_msi()
3833 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3837 * bridges leading to the NHI and to the tunnel PCI bridges.
3862 bridge = ACPI_HANDLE(&dev->dev); in quirk_apple_poweroff_thunderbolt()
3869 * device ID as those on the host, but they will not have the in quirk_apple_poweroff_thunderbolt()
3893 * Following are device-specific reset methods which can be used to
3894 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3900 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf in reset_intel_82599_sfp_virtfn()
3930 return -ENOMEM; in reset_ivb_igd()
3961 /* Device-specific reset method for Chelsio T4-based adapters */
3968 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating in reset_chelsio_generic_dev()
3969 * that we have no device-specific reset method. in reset_chelsio_generic_dev()
3971 if ((dev->device & 0xf000) != 0x4000) in reset_chelsio_generic_dev()
3972 return -ENOTTY; in reset_chelsio_generic_dev()
3998 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts in reset_chelsio_generic_dev()
3999 * are disabled when an MSI-X interrupt message needs to be delivered. in reset_chelsio_generic_dev()
4000 * So we briefly re-enable MSI-X interrupts for the duration of the in reset_chelsio_generic_dev()
4002 * MSI-X state. in reset_chelsio_generic_dev()
4004 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); in reset_chelsio_generic_dev()
4006 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, in reset_chelsio_generic_dev()
4015 * the original PCI Configuration Space Command word, and return in reset_chelsio_generic_dev()
4029 * FLR where config space reads from the device return -1. We seem to be
4031 * FLR. This quirk is generic for any NVMe class device requiring similar
4036 * Chapter 2: Required and optional PCI config registers
4046 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || in nvme_disable_and_flr()
4048 return -ENOTTY; in nvme_disable_and_flr()
4055 return -ENOTTY; in nvme_disable_and_flr()
4134 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
4146 return -ENOTTY; in reset_hinic_vf_dev()
4152 return -ENOTTY; in reset_hinic_vf_dev()
4209 * These device-specific reset methods are here rather than in a driver
4210 * because when a host assigns a device to a guest VM, the host may need
4217 for (i = pci_dev_reset_methods; i->reset; i++) { in pci_dev_specific_reset()
4218 if ((i->vendor == dev->vendor || in pci_dev_specific_reset()
4219 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_reset()
4220 (i->device == dev->device || in pci_dev_specific_reset()
4221 i->device == (u16)PCI_ANY_ID)) in pci_dev_specific_reset()
4222 return i->reset(dev, probe); in pci_dev_specific_reset()
4225 return -ENOTTY; in pci_dev_specific_reset()
4230 if (PCI_FUNC(dev->devfn) != 0) in quirk_dma_func0_alias()
4231 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); in quirk_dma_func0_alias()
4244 if (PCI_FUNC(dev->devfn) != 1) in quirk_dma_func1_alias()
4245 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); in quirk_dma_func1_alias()
4303 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4313 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4317 * controller supports private devices, which can be hidden from PCI config
4338 pci_add_dma_alias(dev, id->driver_data, 1); in quirk_fixed_dma_alias()
4343 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4348 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4349 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4353 if (!pci_is_root_bus(pdev->bus) && in quirk_use_pcie_bridge_dma_alias()
4354 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && in quirk_use_pcie_bridge_dma_alias()
4355 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && in quirk_use_pcie_bridge_dma_alias()
4356 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) in quirk_use_pcie_bridge_dma_alias()
4357 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; in quirk_use_pcie_bridge_dma_alias()
4374 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4387 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4392 * host memory. These aliases mark the whole VCA device as one IOMMU
4396 * what slot is used on other side. This quirk is intended for both host
4422 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; in quirk_bridge_cavm_thrx2_pcie_root()
4430 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4435 u32 class = pdev->class; in quirk_tw686x_class()
4438 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; in quirk_tw686x_class()
4439 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", in quirk_tw686x_class()
4440 class, pdev->class); in quirk_tw686x_class()
4458 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; in quirk_relaxedordering_disable()
4529 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4545 * If a non-compliant device generates a completion with a different
4547 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4551 * If the non-compliant device generates completions with zero attributes
4573 dev_name(&pdev->dev)); in quirk_disable_root_port_attributes()
4588 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely in quirk_chelsio_T5_disable_root_port_attributes()
4591 if ((pdev->device & 0xff00) == 0x5400) in quirk_chelsio_T5_disable_root_port_attributes()
4598 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4616 * AMD has indicated that the devices below do not support peer-to-peer
4619 * peer-to-peer between functions can claim to support a subset of ACS.
4631 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4632 * 1002:4384 SBx00 PCI to PCI Bridge
4637 * 1022:780f [AMD] FCH PCI Bridge
4647 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) in pci_quirk_amd_sb_acs()
4648 return -ENODEV; in pci_quirk_amd_sb_acs()
4653 return -ENODEV; in pci_quirk_amd_sb_acs()
4662 return -ENODEV; in pci_quirk_amd_sb_acs()
4671 switch (dev->device) { in pci_quirk_cavium_acs_match()
4688 return -ENOTTY; in pci_quirk_cavium_acs()
4705 * X-Gene Root Ports matching this quirk do not allow peer-to-peer in pci_quirk_xgene_acs()
4715 * But the implementation could block peer-to-peer transactions between them
4716 * and provide ACS-like functionality.
4723 return -ENOTTY; in pci_quirk_zhaoxin_pcie_ports_acs()
4729 switch (dev->device) { in pci_quirk_zhaoxin_pcie_ports_acs()
4741 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4756 /* Lynxpoint-H PCH */
4759 /* Lynxpoint-LP PCH */
4778 /* Filter out a few obvious non-matches first */ in pci_quirk_intel_pch_acs_match()
4783 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) in pci_quirk_intel_pch_acs_match()
4792 return -ENOTTY; in pci_quirk_intel_pch_acs()
4794 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) in pci_quirk_intel_pch_acs()
4802 * These QCOM Root Ports do provide ACS-like features to disable peer
4806 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4832 return -ENOTTY; in pci_quirk_al_acs()
4836 * but do include ACS-like functionality. The hardware doesn't support in pci_quirk_al_acs()
4837 * peer-to-peer transactions via the root port and each has a unique in pci_quirk_al_acs()
4854 * dword accesses to them. This applies to the following PCI Device IDs, as
4857 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4858 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4866 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4867 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4870 * 0xa290-0xa29f PCI Express Root port #{0-16}
4871 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4877 * August 2017, Revision 002, Document#: 334660-002)[6]
4880 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4882 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4884 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4885 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4886 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4887 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4888 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4889 …ww.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-…
4890 …tel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datas…
4897 switch (dev->device) { in pci_quirk_intel_spt_pch_acs_match()
4915 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4917 pos = dev->acs_cap; in pci_quirk_intel_spt_pch_acs()
4919 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4936 * in their ACS capability if they support peer-to-peer transactions. in pci_quirk_mf_endpoint_acs()
4938 * perform peer-to-peer with other functions, allowing us to mask out in pci_quirk_mf_endpoint_acs()
4950 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, in pci_quirk_rciep_acs()
4951 * "Root-Complex Peer to Peer Considerations". in pci_quirk_rciep_acs()
4954 return -ENOTTY; in pci_quirk_rciep_acs()
4964 * they do not allow peer-to-peer transactions between Root Ports. in pci_quirk_brcm_acs()
4973 * Wangxun 10G/1G NICs have no ACS capability, and on multi-function
4974 * devices, peer-to-peer transactions are not be used between the functions.
4981 switch (dev->device) { in pci_quirk_wangxun_nic_acs()
5054 /* 82571 (Quads omitted due to non-ACS switch) */
5071 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
5072 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
5075 /* Cavium multi-function devices */
5079 /* APM X-Gene */
5090 /* Broadcom multi-function device */
5098 /* Zhaoxin multi-function devices */
5103 /* LX2xx0A : without security features + CAN-FD */
5107 /* LX2xx0C : security features + CAN-FD */
5119 /* LX2xx2A : without security features + CAN-FD */
5123 /* LX2xx2C : security features + CAN-FD */
5143 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
5144 * @dev: PCI device
5148 * -ENOTTY: No quirk applies to this device; we can't tell whether the
5160 * or control to indicate their support here. Multi-function express in pci_dev_specific_acs_enabled()
5161 * devices which do not allow internal peer-to-peer between functions, in pci_dev_specific_acs_enabled()
5164 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { in pci_dev_specific_acs_enabled()
5165 if ((i->vendor == dev->vendor || in pci_dev_specific_acs_enabled()
5166 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_acs_enabled()
5167 (i->device == dev->device || in pci_dev_specific_acs_enabled()
5168 i->device == (u16)PCI_ANY_ID)) { in pci_dev_specific_acs_enabled()
5169 ret = i->acs_enabled(dev, acs_flags); in pci_dev_specific_acs_enabled()
5175 return -ENOTTY; in pci_dev_specific_acs_enabled()
5187 /* Backbone Peer Non-Posted Disable */
5207 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), in pci_quirk_enable_intel_lpc_acs()
5210 return -EINVAL; in pci_quirk_enable_intel_lpc_acs()
5215 return -ENOMEM; in pci_quirk_enable_intel_lpc_acs()
5219 * therefore read-only. If both posted and non-posted peer cycles are in pci_quirk_enable_intel_lpc_acs()
5250 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which in pci_quirk_enable_intel_rp_mpc_acs()
5267 * if dev->external_facing || dev->untrusted
5272 return -ENOTTY; in pci_quirk_enable_intel_pch_acs()
5281 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; in pci_quirk_enable_intel_pch_acs()
5294 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
5296 pos = dev->acs_cap; in pci_quirk_enable_intel_spt_pch_acs()
5298 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
5308 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) in pci_quirk_enable_intel_spt_pch_acs()
5324 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
5326 pos = dev->acs_cap; in pci_quirk_disable_intel_spt_pch_acs_redir()
5328 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
5364 if ((p->vendor == dev->vendor || in pci_dev_specific_enable_acs()
5365 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
5366 (p->device == dev->device || in pci_dev_specific_enable_acs()
5367 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
5368 p->enable_acs) { in pci_dev_specific_enable_acs()
5369 ret = p->enable_acs(dev); in pci_dev_specific_enable_acs()
5375 return -ENOTTY; in pci_dev_specific_enable_acs()
5385 if ((p->vendor == dev->vendor || in pci_dev_specific_disable_acs_redir()
5386 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5387 (p->device == dev->device || in pci_dev_specific_disable_acs_redir()
5388 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5389 p->disable_acs_redir) { in pci_dev_specific_disable_acs_redir()
5390 ret = p->disable_acs_redir(dev); in pci_dev_specific_disable_acs_redir()
5396 return -ENOTTY; in pci_dev_specific_disable_acs_redir()
5400 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5414 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) in quirk_intel_qat_vf_cap()
5434 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() in quirk_intel_qat_vf_cap()
5447 pdev->pcie_cap = pos; in quirk_intel_qat_vf_cap()
5449 pdev->pcie_flags_reg = reg16; in quirk_intel_qat_vf_cap()
5451 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; in quirk_intel_qat_vf_cap()
5453 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; in quirk_intel_qat_vf_cap()
5456 pdev->cfg_size = PCI_CFG_SPACE_SIZE; in quirk_intel_qat_vf_cap()
5466 state->cap.cap_nr = PCI_CAP_ID_EXP; in quirk_intel_qat_vf_cap()
5467 state->cap.cap_extended = 0; in quirk_intel_qat_vf_cap()
5468 state->cap.size = size; in quirk_intel_qat_vf_cap()
5469 cap = (u16 *)&state->cap.data[0]; in quirk_intel_qat_vf_cap()
5477 hlist_add_head(&state->next, &pdev->saved_cap_space); in quirk_intel_qat_vf_cap()
5486 * AMD Starship USB 3.0 Host Controller 0x148c
5487 * AMD Matisse USB 3.0 Host Controller 0x149c
5494 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; in quirk_no_flr()
5506 if (dev->revision == 0x1) in quirk_no_flr_snet()
5513 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); in quirk_no_ext_tags()
5518 bridge->no_ext_tags = 1; in quirk_no_ext_tags()
5521 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); in quirk_no_ext_tags()
5535 pdev->ats_cap = 0; in quirk_no_ats()
5545 if (pdev->device == 0x15d8) { in quirk_amd_harvest_no_ats()
5546 if (pdev->revision == 0xcf && in quirk_amd_harvest_no_ats()
5547 pdev->subsystem_vendor == 0xea50 && in quirk_amd_harvest_no_ats()
5548 (pdev->subsystem_device == 0xce19 || in quirk_amd_harvest_no_ats()
5549 pdev->subsystem_device == 0xcc10 || in quirk_amd_harvest_no_ats()
5550 pdev->subsystem_device == 0xcc08)) in quirk_amd_harvest_no_ats()
5584 if (pdev->revision < 0x20) in quirk_intel_e2000_no_ats()
5602 pdev->no_msi = 1; in quirk_fsl_no_msi()
5607 * Although not allowed by the spec, some multi-function devices have
5620 if (PCI_FUNC(pdev->devfn) != consumer) in pci_create_device_link()
5623 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), in pci_create_device_link()
5624 pdev->bus->number, in pci_create_device_link()
5625 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); in pci_create_device_link()
5626 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { in pci_create_device_link()
5631 if (device_link_add(&pdev->dev, &supplier_pdev->dev, in pci_create_device_link()
5639 pm_runtime_allow(&pdev->dev); in pci_create_device_link()
5659 * Create device link for GPUs with integrated USB xHCI Host
5672 * Create device link for GPUs with integrated Type-C UCSI controller
5673 * to VGA. Currently there is no class code defined for UCSI device over PCI
5675 * over PCI gets a class code.
5699 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) in quirk_nvidia_hda()
5710 /* The GPU becomes a multi-function device when the HDA is enabled */ in quirk_nvidia_hda()
5712 gpu->multifunction = !!(hdr_type & 0x80); in quirk_nvidia_hda()
5723 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5725 * Item #36 - Downstream port applies ACS Source Validation to Completions
5726 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5738 * write, so we do config reads until we receive a non-Config Request Retry
5749 struct pci_dev *bridge = bus->self; in pci_idt_bus_quirk()
5751 pos = bridge->acs_cap; in pci_idt_bus_quirk()
5763 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ in pci_idt_bus_quirk()
5767 /* Re-enable ACS_SV if it was previously enabled */ in pci_idt_bus_quirk()
5777 * originating Requester ID TLPs which access host memory on peer NTB
5807 partition = ioread8(&mmio_ntb->partition_id); in quirk_switchtec_ntb_dma_alias()
5809 partition_map = ioread32(&mmio_ntb->ep_map); in quirk_switchtec_ntb_dma_alias()
5810 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; in quirk_switchtec_ntb_dma_alias()
5825 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); in quirk_switchtec_ntb_dma_alias()
5842 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); in quirk_switchtec_ntb_dma_alias()
5988 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5989 pdev->subsystem_device != 0x222e || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
6032 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); in pci_fixup_no_d0_pme()
6044 * 7.3.27, 7.3.29-7.3.31.
6050 dev->no_msi = 1; in pci_fixup_no_msi_no_pme()
6053 dev->pme_support = 0; in pci_fixup_no_msi_no_pme()
6060 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; in apex_pci_fixup_class()
6066 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 -
6086 if (!pdev->acs_cap) in pci_fixup_pericom_acs_store_forward()
6088 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val); in pci_fixup_pericom_acs_store_forward()
6098 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); in pci_fixup_pericom_acs_store_forward()
6122 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; in nvidia_ion_ahci_fixup()
6129 dev->rom_bar_overlap = 1; in rom_bar_overlap_defect()
6146 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); in aspm_l1_acceptable_latency()
6149 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); in aspm_l1_acceptable_latency()
6202 dev->dpc_rp_log_size = 4; in dpc_log_size()
6224 * For a PCI device with multiple downstream devices, its driver may use
6226 * To overlay the flattened device tree, the PCI device and all its ancestor
6243 pdev->d3cold_delay = 1000; in pci_fixup_d3cold_delay_1sec()