Lines Matching +full:1 +full:- +full:lane
1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
43 #define COMPHY_LANE_REG_DIRECT(reg) (((reg) & 0x7FF) << 1)
129 #define PRD_TXMARGIN_MASK GENMASK(3, 1)
149 #define PIPE_REG_RESET BIT(1)
160 #define BUNDLE_PERIOD_SEL BIT(1)
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) argument
187 * lane0: USB3/GbE1 PHY Configuration 1
188 * lane1: PCIe/GbE0 PHY Configuration 1
192 #define PIN_PU_IVREF_BIT BIT(1)
208 * lane0: USB3/GbE1 PHY Status 1
209 * lane1: PCIe/GbE0 PHY Status 1
219 /* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIe */
221 /* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */
223 /* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */
227 unsigned int lane; member
234 .lane = _lane, \
246 /* lane 0 */
251 /* lane 1 */
252 MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE),
253 MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII),
254 MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_1000BASEX),
255 MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX),
256 /* lane 2 */
300 /* 0 1 2 3 4 5 6 7 */
301 /*-----------------------------------------------------------*/
355 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */
356 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */
357 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */
358 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */
359 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */
360 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */
361 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */
362 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */
363 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */
364 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */
365 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */
366 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
387 /* Used for accessing lane 2 registers (SATA/USB3 PHY) */
392 priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR); in comphy_set_indirect()
393 comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA, in comphy_set_indirect()
397 static void comphy_lane_reg_set(struct mvebu_a3700_comphy_lane *lane, in comphy_lane_reg_set() argument
400 if (lane->id == 2) { in comphy_lane_reg_set()
401 /* lane 2 PHY registers are accessed indirectly */ in comphy_lane_reg_set()
402 comphy_set_indirect(lane->priv, in comphy_lane_reg_set()
406 void __iomem *base = lane->id == 1 ? in comphy_lane_reg_set()
407 lane->priv->lane1_phy_regs : in comphy_lane_reg_set()
408 lane->priv->lane0_phy_regs; in comphy_lane_reg_set()
415 static int comphy_lane_reg_poll(struct mvebu_a3700_comphy_lane *lane, in comphy_lane_reg_poll() argument
421 if (lane->id == 2) { in comphy_lane_reg_poll()
424 /* lane 2 PHY registers are accessed indirectly */ in comphy_lane_reg_poll()
426 lane->priv->lane2_phy_indirect + in comphy_lane_reg_poll()
429 ret = readl_poll_timeout(lane->priv->lane2_phy_indirect + in comphy_lane_reg_poll()
434 void __iomem *base = lane->id == 1 ? in comphy_lane_reg_poll()
435 lane->priv->lane1_phy_regs : in comphy_lane_reg_poll()
436 lane->priv->lane0_phy_regs; in comphy_lane_reg_poll()
447 static void comphy_periph_reg_set(struct mvebu_a3700_comphy_lane *lane, in comphy_periph_reg_set() argument
450 comphy_reg_set(lane->priv->comphy_regs + COMPHY_PHY_REG(lane->id, reg), in comphy_periph_reg_set()
454 static int comphy_periph_reg_poll(struct mvebu_a3700_comphy_lane *lane, in comphy_periph_reg_poll() argument
460 return readl_poll_timeout(lane->priv->comphy_regs + in comphy_periph_reg_poll()
461 COMPHY_PHY_REG(lane->id, reg), in comphy_periph_reg_poll()
468 mvebu_a3700_comphy_set_phy_selector(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_set_phy_selector() argument
473 switch (lane->mode) { in mvebu_a3700_comphy_set_phy_selector()
476 if (lane->id == 2) in mvebu_a3700_comphy_set_phy_selector()
483 if (lane->id == 0) in mvebu_a3700_comphy_set_phy_selector()
485 else if (lane->id == 1) in mvebu_a3700_comphy_set_phy_selector()
492 if (lane->id == 2) in mvebu_a3700_comphy_set_phy_selector()
494 else if (lane->id == 0) in mvebu_a3700_comphy_set_phy_selector()
502 if (lane->id == 1) in mvebu_a3700_comphy_set_phy_selector()
512 spin_lock_irqsave(&lane->priv->lock, flags); in mvebu_a3700_comphy_set_phy_selector()
514 old = readl(lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG); in mvebu_a3700_comphy_set_phy_selector()
516 writel(new, lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG); in mvebu_a3700_comphy_set_phy_selector()
518 spin_unlock_irqrestore(&lane->priv->lock, flags); in mvebu_a3700_comphy_set_phy_selector()
520 dev_dbg(lane->dev, in mvebu_a3700_comphy_set_phy_selector()
521 "COMPHY[%d] mode[%d] changed PHY selector 0x%08x -> 0x%08x\n", in mvebu_a3700_comphy_set_phy_selector()
522 lane->id, lane->mode, old, new); in mvebu_a3700_comphy_set_phy_selector()
526 dev_err(lane->dev, "COMPHY[%d] mode[%d] is invalid\n", lane->id, in mvebu_a3700_comphy_set_phy_selector()
527 lane->mode); in mvebu_a3700_comphy_set_phy_selector()
528 return -EINVAL; in mvebu_a3700_comphy_set_phy_selector()
532 mvebu_a3700_comphy_sata_power_on(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_sata_power_on() argument
538 ret = mvebu_a3700_comphy_set_phy_selector(lane); in mvebu_a3700_comphy_sata_power_on()
543 comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL, in mvebu_a3700_comphy_sata_power_on()
548 if (lane->invert_tx) in mvebu_a3700_comphy_sata_power_on()
550 if (lane->invert_rx) in mvebu_a3700_comphy_sata_power_on()
553 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); in mvebu_a3700_comphy_sata_power_on()
555 /* 1. Select 40-bit data width */ in mvebu_a3700_comphy_sata_power_on()
556 comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, in mvebu_a3700_comphy_sata_power_on()
560 if (lane->priv->xtal_is_40m) in mvebu_a3700_comphy_sata_power_on()
567 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); in mvebu_a3700_comphy_sata_power_on()
570 comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, in mvebu_a3700_comphy_sata_power_on()
574 comphy_set_indirect(lane->priv, COMPHY_RESERVED_REG, in mvebu_a3700_comphy_sata_power_on()
577 /* 5. Set vendor-specific configuration (It is done in sata driver) */ in mvebu_a3700_comphy_sata_power_on()
578 /* XXX: in U-Boot below sequence was executed in this place, in Linux in mvebu_a3700_comphy_sata_power_on()
579 * not. Now it is done only in U-Boot before this comphy in mvebu_a3700_comphy_sata_power_on()
580 * initialization - tests shows that it works ok, but in case of any in mvebu_a3700_comphy_sata_power_on()
590 ret = comphy_lane_reg_poll(lane, COMPHY_DIG_LOOPBACK_EN, in mvebu_a3700_comphy_sata_power_on()
594 dev_err(lane->dev, "Failed to lock SATA PLL\n"); in mvebu_a3700_comphy_sata_power_on()
599 static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane, in comphy_gbe_phy_init() argument
623 comphy_lane_reg_set(lane, addr, val, 0xFFFF); in comphy_gbe_phy_init()
628 mvebu_a3700_comphy_ethernet_power_on(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_ethernet_power_on() argument
634 ret = mvebu_a3700_comphy_set_phy_selector(lane); in mvebu_a3700_comphy_ethernet_power_on()
639 * 1. Reset PHY by setting PHY input port PIN_RESET=1. in mvebu_a3700_comphy_ethernet_power_on()
640 * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep in mvebu_a3700_comphy_ethernet_power_on()
647 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
652 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
658 switch (lane->submode) { in mvebu_a3700_comphy_ethernet_power_on()
661 /* SGMII 1G, SerDes speed 1.25G */ in mvebu_a3700_comphy_ethernet_power_on()
665 /* 2500Base-X, SerDes speed 3.125G */ in mvebu_a3700_comphy_ethernet_power_on()
670 dev_err(lane->dev, in mvebu_a3700_comphy_ethernet_power_on()
671 "unsupported phy speed %d on comphy lane%d\n", in mvebu_a3700_comphy_ethernet_power_on()
672 lane->submode, lane->id); in mvebu_a3700_comphy_ethernet_power_on()
673 return -EINVAL; in mvebu_a3700_comphy_ethernet_power_on()
677 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
688 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
696 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
702 if (lane->priv->xtal_is_40m) in mvebu_a3700_comphy_ethernet_power_on()
708 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
711 * 10. Program COMPHY register PHY_GEN_MAX[1:0] in mvebu_a3700_comphy_ethernet_power_on()
724 comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
738 * the related GEN table during real chip bring-up. We only required to in mvebu_a3700_comphy_ethernet_power_on()
743 dev_dbg(lane->dev, "Running C-DPI phy init %s mode\n", in mvebu_a3700_comphy_ethernet_power_on()
744 lane->submode == PHY_INTERFACE_MODE_2500BASEX ? "2G5" : "1G"); in mvebu_a3700_comphy_ethernet_power_on()
745 if (lane->priv->xtal_is_40m) in mvebu_a3700_comphy_ethernet_power_on()
746 comphy_gbe_phy_init(lane, in mvebu_a3700_comphy_ethernet_power_on()
747 lane->submode != PHY_INTERFACE_MODE_2500BASEX); in mvebu_a3700_comphy_ethernet_power_on()
753 if (lane->invert_tx) in mvebu_a3700_comphy_ethernet_power_on()
755 if (lane->invert_rx) in mvebu_a3700_comphy_ethernet_power_on()
758 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
761 * 15. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to in mvebu_a3700_comphy_ethernet_power_on()
763 * be done before PIN_PU_PLL=1. There should be no register programming in mvebu_a3700_comphy_ethernet_power_on()
768 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); in mvebu_a3700_comphy_ethernet_power_on()
772 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. in mvebu_a3700_comphy_ethernet_power_on()
774 ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, in mvebu_a3700_comphy_ethernet_power_on()
779 dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n", in mvebu_a3700_comphy_ethernet_power_on()
780 lane->id); in mvebu_a3700_comphy_ethernet_power_on()
787 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 0x0, PIN_TX_IDLE_BIT); in mvebu_a3700_comphy_ethernet_power_on()
790 * 18. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To in mvebu_a3700_comphy_ethernet_power_on()
793 * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please in mvebu_a3700_comphy_ethernet_power_on()
796 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, in mvebu_a3700_comphy_ethernet_power_on()
799 ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, in mvebu_a3700_comphy_ethernet_power_on()
804 dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n", in mvebu_a3700_comphy_ethernet_power_on()
805 lane->id); in mvebu_a3700_comphy_ethernet_power_on()
809 ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, in mvebu_a3700_comphy_ethernet_power_on()
813 dev_err(lane->dev, "Failed to init RX of SERDES PHY %d\n", in mvebu_a3700_comphy_ethernet_power_on()
814 lane->id); in mvebu_a3700_comphy_ethernet_power_on()
820 mvebu_a3700_comphy_usb3_power_on(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_usb3_power_on() argument
826 ret = mvebu_a3700_comphy_set_phy_selector(lane); in mvebu_a3700_comphy_usb3_power_on()
831 comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST); in mvebu_a3700_comphy_usb3_power_on()
839 * 1. Set PRD_TXDEEMPH (3.5db de-emph) in mvebu_a3700_comphy_usb3_power_on()
844 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG0, data, mask); in mvebu_a3700_comphy_usb3_power_on()
850 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db in mvebu_a3700_comphy_usb3_power_on()
856 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, data, mask); in mvebu_a3700_comphy_usb3_power_on()
861 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG4, in mvebu_a3700_comphy_usb3_power_on()
866 * Use margining signals from lane configuration in mvebu_a3700_comphy_usb3_power_on()
868 comphy_lane_reg_set(lane, COMPHY_PIPE_TEST_MODE_CTRL, in mvebu_a3700_comphy_usb3_power_on()
872 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles in mvebu_a3700_comphy_usb3_power_on()
878 comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, data, mask); in mvebu_a3700_comphy_usb3_power_on()
883 comphy_lane_reg_set(lane, COMPHY_GEN2_SET2, in mvebu_a3700_comphy_usb3_power_on()
893 comphy_lane_reg_set(lane, COMPHY_GEN3_SET2, data, mask); in mvebu_a3700_comphy_usb3_power_on()
899 if (lane->priv->xtal_is_40m) { in mvebu_a3700_comphy_usb3_power_on()
912 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); in mvebu_a3700_comphy_usb3_power_on()
917 comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask); in mvebu_a3700_comphy_usb3_power_on()
922 comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN, in mvebu_a3700_comphy_usb3_power_on()
928 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, CLK500M_EN, CLK500M_EN); in mvebu_a3700_comphy_usb3_power_on()
931 * 11. Set 20-bit data width in mvebu_a3700_comphy_usb3_power_on()
933 comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, in mvebu_a3700_comphy_usb3_power_on()
941 comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, data, mask); in mvebu_a3700_comphy_usb3_power_on()
947 if (lane->invert_tx) in mvebu_a3700_comphy_usb3_power_on()
949 if (lane->invert_rx) in mvebu_a3700_comphy_usb3_power_on()
952 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); in mvebu_a3700_comphy_usb3_power_on()
957 comphy_lane_reg_set(lane, COMPHY_SYNC_MASK_GEN, in mvebu_a3700_comphy_usb3_power_on()
963 comphy_lane_reg_set(lane, COMPHY_GEN2_SET3, in mvebu_a3700_comphy_usb3_power_on()
971 comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask); in mvebu_a3700_comphy_usb3_power_on()
976 ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN, in mvebu_a3700_comphy_usb3_power_on()
979 dev_err(lane->dev, "Failed to lock USB3 PLL\n"); in mvebu_a3700_comphy_usb3_power_on()
985 mvebu_a3700_comphy_pcie_power_on(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_pcie_power_on() argument
991 ret = mvebu_a3700_comphy_set_phy_selector(lane); in mvebu_a3700_comphy_pcie_power_on()
995 /* 1. Enable max PLL. */ in mvebu_a3700_comphy_pcie_power_on()
996 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, in mvebu_a3700_comphy_pcie_power_on()
1000 comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, in mvebu_a3700_comphy_pcie_power_on()
1004 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL1, in mvebu_a3700_comphy_pcie_power_on()
1011 comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask); in mvebu_a3700_comphy_pcie_power_on()
1014 comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN, in mvebu_a3700_comphy_pcie_power_on()
1020 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask); in mvebu_a3700_comphy_pcie_power_on()
1024 * PCI-E driver in mvebu_a3700_comphy_pcie_power_on()
1032 if (lane->priv->xtal_is_40m) in mvebu_a3700_comphy_pcie_power_on()
1040 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); in mvebu_a3700_comphy_pcie_power_on()
1043 comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, in mvebu_a3700_comphy_pcie_power_on()
1049 if (lane->invert_tx) in mvebu_a3700_comphy_pcie_power_on()
1051 if (lane->invert_rx) in mvebu_a3700_comphy_pcie_power_on()
1054 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); in mvebu_a3700_comphy_pcie_power_on()
1059 comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask); in mvebu_a3700_comphy_pcie_power_on()
1064 ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN, in mvebu_a3700_comphy_pcie_power_on()
1067 dev_err(lane->dev, "Failed to lock PCIE PLL\n"); in mvebu_a3700_comphy_pcie_power_on()
1073 mvebu_a3700_comphy_sata_power_off(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_sata_power_off() argument
1076 comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL, in mvebu_a3700_comphy_sata_power_off()
1080 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, in mvebu_a3700_comphy_sata_power_off()
1085 mvebu_a3700_comphy_ethernet_power_off(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_ethernet_power_off() argument
1092 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); in mvebu_a3700_comphy_ethernet_power_off()
1096 mvebu_a3700_comphy_pcie_power_off(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_pcie_power_off() argument
1099 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, in mvebu_a3700_comphy_pcie_power_off()
1103 static void mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane) in mvebu_a3700_comphy_usb3_power_off() argument
1111 static bool mvebu_a3700_comphy_check_mode(int lane, in mvebu_a3700_comphy_check_mode() argument
1122 if (mvebu_a3700_comphy_modes[i].lane == lane && in mvebu_a3700_comphy_check_mode()
1137 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); in mvebu_a3700_comphy_set_mode() local
1139 if (!mvebu_a3700_comphy_check_mode(lane->id, mode, submode)) { in mvebu_a3700_comphy_set_mode()
1140 dev_err(lane->dev, "invalid COMPHY mode\n"); in mvebu_a3700_comphy_set_mode()
1141 return -EINVAL; in mvebu_a3700_comphy_set_mode()
1145 if (phy->power_count && in mvebu_a3700_comphy_set_mode()
1146 (lane->mode != mode || lane->submode != submode)) in mvebu_a3700_comphy_set_mode()
1147 return -EBUSY; in mvebu_a3700_comphy_set_mode()
1149 /* Just remember the mode, ->power_on() will do the real setup */ in mvebu_a3700_comphy_set_mode()
1150 lane->mode = mode; in mvebu_a3700_comphy_set_mode()
1151 lane->submode = submode; in mvebu_a3700_comphy_set_mode()
1158 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); in mvebu_a3700_comphy_power_on() local
1160 if (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode, in mvebu_a3700_comphy_power_on()
1161 lane->submode)) { in mvebu_a3700_comphy_power_on()
1162 dev_err(lane->dev, "invalid COMPHY mode\n"); in mvebu_a3700_comphy_power_on()
1163 return -EINVAL; in mvebu_a3700_comphy_power_on()
1166 switch (lane->mode) { in mvebu_a3700_comphy_power_on()
1168 dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id); in mvebu_a3700_comphy_power_on()
1169 return mvebu_a3700_comphy_usb3_power_on(lane); in mvebu_a3700_comphy_power_on()
1171 dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id); in mvebu_a3700_comphy_power_on()
1172 return mvebu_a3700_comphy_sata_power_on(lane); in mvebu_a3700_comphy_power_on()
1174 dev_dbg(lane->dev, "set lane %d to Ethernet mode\n", lane->id); in mvebu_a3700_comphy_power_on()
1175 return mvebu_a3700_comphy_ethernet_power_on(lane); in mvebu_a3700_comphy_power_on()
1177 dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id); in mvebu_a3700_comphy_power_on()
1178 return mvebu_a3700_comphy_pcie_power_on(lane); in mvebu_a3700_comphy_power_on()
1180 dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode); in mvebu_a3700_comphy_power_on()
1181 return -EOPNOTSUPP; in mvebu_a3700_comphy_power_on()
1187 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); in mvebu_a3700_comphy_power_off() local
1189 switch (lane->id) { in mvebu_a3700_comphy_power_off()
1191 mvebu_a3700_comphy_usb3_power_off(lane); in mvebu_a3700_comphy_power_off()
1192 mvebu_a3700_comphy_ethernet_power_off(lane); in mvebu_a3700_comphy_power_off()
1194 case 1: in mvebu_a3700_comphy_power_off()
1195 mvebu_a3700_comphy_pcie_power_off(lane); in mvebu_a3700_comphy_power_off()
1196 mvebu_a3700_comphy_ethernet_power_off(lane); in mvebu_a3700_comphy_power_off()
1199 mvebu_a3700_comphy_usb3_power_off(lane); in mvebu_a3700_comphy_power_off()
1200 mvebu_a3700_comphy_sata_power_off(lane); in mvebu_a3700_comphy_power_off()
1203 dev_err(lane->dev, "invalid COMPHY mode\n"); in mvebu_a3700_comphy_power_off()
1204 return -EINVAL; in mvebu_a3700_comphy_power_off()
1218 struct mvebu_a3700_comphy_lane *lane; in mvebu_a3700_comphy_xlate() local
1226 lane = phy_get_drvdata(phy); in mvebu_a3700_comphy_xlate()
1228 port = args->args[0]; in mvebu_a3700_comphy_xlate()
1229 if (port != 0 && (port != 1 || lane->id != 0)) { in mvebu_a3700_comphy_xlate()
1230 dev_err(lane->dev, "invalid port number %u\n", port); in mvebu_a3700_comphy_xlate()
1231 return ERR_PTR(-EINVAL); in mvebu_a3700_comphy_xlate()
1234 lane->invert_tx = args->args[1] & BIT(0); in mvebu_a3700_comphy_xlate()
1235 lane->invert_rx = args->args[1] & BIT(1); in mvebu_a3700_comphy_xlate()
1249 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in mvebu_a3700_comphy_probe()
1251 return -ENOMEM; in mvebu_a3700_comphy_probe()
1253 spin_lock_init(&priv->lock); in mvebu_a3700_comphy_probe()
1256 priv->comphy_regs = devm_ioremap_resource(&pdev->dev, res); in mvebu_a3700_comphy_probe()
1257 if (IS_ERR(priv->comphy_regs)) in mvebu_a3700_comphy_probe()
1258 return PTR_ERR(priv->comphy_regs); in mvebu_a3700_comphy_probe()
1262 priv->lane1_phy_regs = devm_ioremap_resource(&pdev->dev, res); in mvebu_a3700_comphy_probe()
1263 if (IS_ERR(priv->lane1_phy_regs)) in mvebu_a3700_comphy_probe()
1264 return PTR_ERR(priv->lane1_phy_regs); in mvebu_a3700_comphy_probe()
1268 priv->lane0_phy_regs = devm_ioremap_resource(&pdev->dev, res); in mvebu_a3700_comphy_probe()
1269 if (IS_ERR(priv->lane0_phy_regs)) in mvebu_a3700_comphy_probe()
1270 return PTR_ERR(priv->lane0_phy_regs); in mvebu_a3700_comphy_probe()
1274 priv->lane2_phy_indirect = devm_ioremap_resource(&pdev->dev, res); in mvebu_a3700_comphy_probe()
1275 if (IS_ERR(priv->lane2_phy_indirect)) in mvebu_a3700_comphy_probe()
1276 return PTR_ERR(priv->lane2_phy_indirect); in mvebu_a3700_comphy_probe()
1283 clk = clk_get(&pdev->dev, "xtal"); in mvebu_a3700_comphy_probe()
1285 if (PTR_ERR(clk) == -EPROBE_DEFER) in mvebu_a3700_comphy_probe()
1286 return -EPROBE_DEFER; in mvebu_a3700_comphy_probe()
1287 dev_warn(&pdev->dev, "missing 'xtal' clk (%ld)\n", in mvebu_a3700_comphy_probe()
1292 dev_warn(&pdev->dev, "enabling xtal clk failed (%d)\n", in mvebu_a3700_comphy_probe()
1296 priv->xtal_is_40m = true; in mvebu_a3700_comphy_probe()
1302 dev_set_drvdata(&pdev->dev, priv); in mvebu_a3700_comphy_probe()
1304 for_each_available_child_of_node(pdev->dev.of_node, child) { in mvebu_a3700_comphy_probe()
1305 struct mvebu_a3700_comphy_lane *lane; in mvebu_a3700_comphy_probe() local
1312 dev_err(&pdev->dev, "missing 'reg' property (%d)\n", in mvebu_a3700_comphy_probe()
1318 dev_err(&pdev->dev, "invalid 'reg' property\n"); in mvebu_a3700_comphy_probe()
1322 lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL); in mvebu_a3700_comphy_probe()
1323 if (!lane) { in mvebu_a3700_comphy_probe()
1325 return -ENOMEM; in mvebu_a3700_comphy_probe()
1328 phy = devm_phy_create(&pdev->dev, child, in mvebu_a3700_comphy_probe()
1335 lane->priv = priv; in mvebu_a3700_comphy_probe()
1336 lane->dev = &pdev->dev; in mvebu_a3700_comphy_probe()
1337 lane->mode = PHY_MODE_INVALID; in mvebu_a3700_comphy_probe()
1338 lane->submode = PHY_INTERFACE_MODE_NA; in mvebu_a3700_comphy_probe()
1339 lane->id = lane_id; in mvebu_a3700_comphy_probe()
1340 lane->invert_tx = false; in mvebu_a3700_comphy_probe()
1341 lane->invert_rx = false; in mvebu_a3700_comphy_probe()
1342 phy_set_drvdata(phy, lane); in mvebu_a3700_comphy_probe()
1351 provider = devm_of_phy_provider_register(&pdev->dev, in mvebu_a3700_comphy_probe()
1358 { .compatible = "marvell,comphy-a3700" },
1366 .name = "mvebu-a3700-comphy",