Lines Matching +full:0 +full:x000c
3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
24 #define PHYREG6 0x14
29 #define PHYREG7 0x18
33 #define PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
34 #define PHYREG7_RX_RTERM_SHIFT 0
37 #define PHYREG8 0x1C
40 #define PHYREG11 0x28
41 #define PHYREG11_SU_TRIM_0_7 0xF0
43 #define PHYREG12 0x2C
46 #define PHYREG13 0x30
48 #define PHYREG13_RESISTER_SHIFT 0x4
52 #define PHYREG14 0x34
53 #define PHYREG14_CKRCV_AMP1 BIT(0)
55 #define PHYREG15 0x38
56 #define PHYREG15_CTLE_EN BIT(0)
61 #define PHYREG16 0x3C
62 #define PHYREG16_SSC_CNT_VALUE 0x5f
64 #define PHYREG18 0x44
65 #define PHYREG18_PLL_LOOP 0x32
67 #define PHYREG27 0x6C
68 #define PHYREG27_RX_TRIM_RK3588 0x4C
70 #define PHYREG32 0x7C
73 #define PHYREG32_SSC_UPWARD 0
78 #define PHYREG33 0x80
230 return 0; in rockchip_combphy_init()
245 return 0; in rockchip_combphy_exit()
263 if (priv->type != PHY_NONE && priv->type != args->args[0]) in rockchip_combphy_xlate()
265 args->args[0], priv->type); in rockchip_combphy_xlate()
267 priv->type = args->args[0]; in rockchip_combphy_xlate()
281 for (i = 0; i < priv->num_clks; i++) { in rockchip_combphy_parse_dt()
313 return 0; in rockchip_combphy_parse_dt()
335 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rockchip_combphy_probe()
394 /* Enable adaptive CTLE for USB3.0 Rx. */ in rk3568_combphy_cfg()
428 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) in rk3568_combphy_cfg()
466 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ in rk3568_combphy_cfg()
528 return 0; in rk3568_combphy_cfg()
533 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
534 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
535 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 },
536 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 },
537 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
538 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
539 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
540 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
541 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
542 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
543 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
544 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
545 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
546 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
547 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
548 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
549 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 },
550 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
551 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
552 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
553 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
554 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
555 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 },
556 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 },
557 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 },
558 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 },
560 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
561 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },
590 /* Enable adaptive CTLE for USB3.0 Rx. */ in rk3588_combphy_cfg()
622 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) in rk3588_combphy_cfg()
647 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ in rk3588_combphy_cfg()
706 return 0; in rk3588_combphy_cfg()
711 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
712 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
713 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
714 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
715 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
716 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
717 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
718 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
719 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
720 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
721 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
722 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
723 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
724 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
725 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
726 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
727 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
728 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
729 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
730 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
732 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 },
733 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 },
734 .pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 },
735 .pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 },