1 // SPDX-License-Identifier: GPL-2.0+
12 #include <dt-bindings/reset/mt2712-resets.h>
13 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
14 #include <dt-bindings/reset/mt7986-resets.h>
15 #include <dt-bindings/reset/mt8183-resets.h>
16 #include <dt-bindings/reset/mt8186-resets.h>
17 #include <dt-bindings/reset/mt8188-resets.h>
18 #include <dt-bindings/reset/mt8192-resets.h>
19 #include <dt-bindings/reset/mt8195-resets.h>
29 #include <linux/reset-controller.h>
61 #define DRV_NAME		"mtk-wdt"
120 	spin_lock_irqsave(&data->lock, flags);  in toprgu_reset_update()
122 	tmp = readl(data->wdt_base + WDT_SWSYSRST);  in toprgu_reset_update()
128 	writel(tmp, data->wdt_base + WDT_SWSYSRST);  in toprgu_reset_update()
130 	spin_unlock_irqrestore(&data->lock, flags);  in toprgu_reset_update()
162 	.reset = toprgu_reset,
171 	spin_lock_init(&mtk_wdt->lock);  in toprgu_register_reset_controller()
173 	mtk_wdt->rcdev.owner = THIS_MODULE;  in toprgu_register_reset_controller()
174 	mtk_wdt->rcdev.nr_resets = rst_num;  in toprgu_register_reset_controller()
175 	mtk_wdt->rcdev.ops = &toprgu_reset_ops;  in toprgu_register_reset_controller()
176 	mtk_wdt->rcdev.of_node = pdev->dev.of_node;  in toprgu_register_reset_controller()
177 	ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev);  in toprgu_register_reset_controller()
179 		dev_err(&pdev->dev,  in toprgu_register_reset_controller()
180 			"couldn't register wdt reset controller: %d\n", ret);  in toprgu_register_reset_controller()
190 	wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_restart()
203 	void __iomem *wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_ping()
214 	void __iomem *wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_set_timeout()
217 	wdt_dev->timeout = timeout;  in mtk_wdt_set_timeout()
222 	if (wdt_dev->pretimeout)  in mtk_wdt_set_timeout()
223 		wdt_dev->pretimeout = timeout / 2;  in mtk_wdt_set_timeout()
229 	reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6)  in mtk_wdt_set_timeout()
243 	wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_init()
246 		set_bit(WDOG_HW_RUNNING, &wdt_dev->status);  in mtk_wdt_init()
247 		mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);  in mtk_wdt_init()
254 	void __iomem *wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_stop()
269 	void __iomem *wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_start()
272 	ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);  in mtk_wdt_start()
277 	if (wdt_dev->pretimeout)  in mtk_wdt_start()
281 	if (mtk_wdt->disable_wdt_extrst)  in mtk_wdt_start()
283 	if (mtk_wdt->reset_by_toprgu)  in mtk_wdt_start()
295 	void __iomem *wdt_base = mtk_wdt->wdt_base;  in mtk_wdt_set_pretimeout()
298 	if (timeout && !wdd->pretimeout) {  in mtk_wdt_set_pretimeout()
299 		wdd->pretimeout = wdd->timeout / 2;  in mtk_wdt_set_pretimeout()
301 	} else if (!timeout && wdd->pretimeout) {  in mtk_wdt_set_pretimeout()
302 		wdd->pretimeout = 0;  in mtk_wdt_set_pretimeout()
311 	return mtk_wdt_set_timeout(wdd, wdd->timeout);  in mtk_wdt_set_pretimeout()
350 	struct device *dev = &pdev->dev;  in mtk_wdt_probe()
357 		return -ENOMEM;  in mtk_wdt_probe()
361 	mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);  in mtk_wdt_probe()
362 	if (IS_ERR(mtk_wdt->wdt_base))  in mtk_wdt_probe()
363 		return PTR_ERR(mtk_wdt->wdt_base);  in mtk_wdt_probe()
367 		err = devm_request_irq(&pdev->dev, irq, mtk_wdt_isr, 0, "wdt_bark",  in mtk_wdt_probe()
368 				       &mtk_wdt->wdt_dev);  in mtk_wdt_probe()
372 		mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info;  in mtk_wdt_probe()
373 		mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2;  in mtk_wdt_probe()
375 		if (irq == -EPROBE_DEFER)  in mtk_wdt_probe()
376 			return -EPROBE_DEFER;  in mtk_wdt_probe()
378 		mtk_wdt->wdt_dev.info = &mtk_wdt_info;  in mtk_wdt_probe()
381 	mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;  in mtk_wdt_probe()
382 	mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;  in mtk_wdt_probe()
383 	mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000;  in mtk_wdt_probe()
384 	mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;  in mtk_wdt_probe()
385 	mtk_wdt->wdt_dev.parent = dev;  in mtk_wdt_probe()
387 	watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev);  in mtk_wdt_probe()
388 	watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);  in mtk_wdt_probe()
389 	watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);  in mtk_wdt_probe()
391 	watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);  in mtk_wdt_probe()
393 	mtk_wdt_init(&mtk_wdt->wdt_dev);  in mtk_wdt_probe()
395 	watchdog_stop_on_reboot(&mtk_wdt->wdt_dev);  in mtk_wdt_probe()
396 	err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev);  in mtk_wdt_probe()
401 		 mtk_wdt->wdt_dev.timeout, nowayout);  in mtk_wdt_probe()
406 						       wdt_data->toprgu_sw_rst_num);  in mtk_wdt_probe()
411 	mtk_wdt->disable_wdt_extrst =  in mtk_wdt_probe()
412 		of_property_read_bool(dev->of_node, "mediatek,disable-extrst");  in mtk_wdt_probe()
414 	mtk_wdt->reset_by_toprgu =  in mtk_wdt_probe()
415 		of_property_read_bool(dev->of_node, "mediatek,reset-by-toprgu");  in mtk_wdt_probe()
424 	if (watchdog_active(&mtk_wdt->wdt_dev))  in mtk_wdt_suspend()
425 		mtk_wdt_stop(&mtk_wdt->wdt_dev);  in mtk_wdt_suspend()
434 	if (watchdog_active(&mtk_wdt->wdt_dev)) {  in mtk_wdt_resume()
435 		mtk_wdt_start(&mtk_wdt->wdt_dev);  in mtk_wdt_resume()
436 		mtk_wdt_ping(&mtk_wdt->wdt_dev);  in mtk_wdt_resume()
443 	{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
444 	{ .compatible = "mediatek,mt6589-wdt" },
445 	{ .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data },
446 	{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
447 	{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
448 	{ .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
449 	{ .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },
450 	{ .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
451 	{ .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data },