Lines Matching +full:enum +full:- +full:as +full:- +full:flags
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
18 * typedef dma_cookie_t - an opaque DMA cookie
31 * enum dma_status - DMA transaction status
37 enum dma_status {
46 * enum dma_transaction_type - DMA transaction types/indexes
49 * automatically set as dma devices are registered.
51 enum dma_transaction_type {
73 * enum dma_transfer_direction - dma transfer mode and direction indicator
79 enum dma_transfer_direction {
89 * ----------------------------
91 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
96 * it is to be repeated and other per-transfer attributes.
103 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
111 * struct data_chunk - Element of scatter-gather list that makes a frame.
133 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
153 enum dma_transfer_direction dir;
164 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
166 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
168 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
171 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
172 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
173 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
176 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
188 * active repeated (as indicated by DMA_PREP_REPEAT) transaction when the
194 enum dma_ctrl_flags {
208 * enum sum_check_bits - bit position of pq_check_flags
210 enum sum_check_bits {
216 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
217 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
218 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
220 enum sum_check_flags {
227 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
233 * enum dma_desc_metadata_mode - per descriptor metadata mode types supported
234 * @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the
239 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
245 * - DMA_DEV_TO_MEM:
253 * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA
257 * provided as helper functions.
264 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
272 * - DMA_DEV_TO_MEM:
282 enum dma_desc_metadata_mode {
289 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
300 * struct dma_router - DMA router structure
310 * struct dma_chan - devices supply DMA channels, clients use them
321 * @local: per-cpu pointer to a struct dma_chan_percpu
323 * @table_count: number of appearances in the mem-to-mem allocation table
326 * @private: private data for certain client-channel associations
355 * struct dma_chan_dev - relate sysfs device node to backing channel device
359 * @chan_dma_dev: The channel is using custom/different dma-mapping
370 * enum dma_slave_buswidth - defines bus width of the DMA slave
373 enum dma_slave_buswidth {
387 * struct dma_slave_config - dma slave channel runtime config
403 * @dst_addr_width: same as src_addr_width but for destination
405 * @src_maxburst: the maximum number of words (note: words, as in
410 * @dst_maxburst: same as src_maxburst but for destination target
416 * @dst_port_window_size: same as src_port_window_size but for the destination
425 * This struct is passed in as configuration data to a DMA engine
429 * will then be passed in as an argument to the function.
431 * The rationale for adding configuration information to this struct is as
438 enum dma_transfer_direction direction;
441 enum dma_slave_buswidth src_addr_width;
442 enum dma_slave_buswidth dst_addr_width;
453 * enum dma_residue_granularity - Granularity of the reported transfer residue
463 * the hardware supports scatter-gather and the segment descriptor has a field
472 enum dma_residue_granularity {
479 * struct dma_slave_caps - expose capabilities of a slave channel only
485 * Since the enum dma_transfer_direction is not defined as bit flag for
487 * should be checked by controller as well
488 * @min_burst: min burst capability per-transfer
489 * @max_burst: max burst capability per-transfer
511 enum dma_residue_granularity residue_granularity;
517 return dev_name(&chan->dev->device); in dma_chan_name()
523 * typedef dma_filter_fn - callback filter for dma_request_channel
529 * being returned. Where 'suitable' indicates a non-busy channel that
537 enum dmaengine_tx_result {
545 enum dmaengine_tx_result result;
580 * struct dma_async_tx_descriptor - async transaction descriptor
581 * ---dma generic offload fields---
582 * @cookie: tracking cookie for this transaction, set to -EBUSY if
584 * @flags: flags to augment operation preparation, control completion, and
597 * ---async_tx api specific fields---
604 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ member
613 enum dma_desc_metadata_mode desc_metadata_mode;
626 kref_get(&unmap->kref); in dma_set_unmap()
627 tx->unmap = unmap; in dma_set_unmap()
631 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
639 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags) in dmaengine_get_unmap_data() argument
650 if (!tx->unmap) in dma_descriptor_unmap()
653 dmaengine_unmap_put(tx->unmap); in dma_descriptor_unmap()
654 tx->unmap = NULL; in dma_descriptor_unmap()
686 spin_lock_bh(&txd->lock); in txd_lock()
690 spin_unlock_bh(&txd->lock); in txd_unlock()
694 txd->next = next; in txd_chain()
695 next->parent = txd; in txd_chain()
699 txd->parent = NULL; in txd_clear_parent()
703 txd->next = NULL; in txd_clear_next()
707 return txd->parent; in txd_parent()
711 return txd->next; in txd_next()
716 * struct dma_tx_state - filled in to report the status of
733 * enum dmaengine_alignment - defines alignment of the DMA async tx
736 enum dmaengine_alignment {
749 * struct dma_slave_map - associates slave device and it's slave channel with
762 * struct dma_filter - information for slave device/channel to filter_fn/param
775 * struct dma_device - info on the entity supplying DMA services
782 * @cap_mask: one or more dma_capability flags
785 * @max_pq: maximum number of PQ sources and PQ-continue capability
799 * Since the enum dma_transfer_direction is not defined as bit flag for
801 * should be checked by controller as well
802 * @min_burst: min burst capability per-transfer
803 * @max_burst: max burst capability per-transfer
829 * with per-channel specific ones
862 enum dma_desc_metadata_mode desc_metadata_modes;
865 enum dmaengine_alignment copy_align;
866 enum dmaengine_alignment xor_align;
867 enum dmaengine_alignment pq_align;
868 enum dmaengine_alignment fill_align;
883 enum dma_residue_granularity residue_granularity;
891 size_t len, unsigned long flags);
894 unsigned int src_cnt, size_t len, unsigned long flags);
897 size_t len, enum sum_check_flags *result, unsigned long flags);
901 size_t len, unsigned long flags);
905 enum sum_check_flags *pqres, unsigned long flags);
908 unsigned long flags);
911 unsigned int nents, int value, unsigned long flags);
913 struct dma_chan *chan, unsigned long flags);
917 unsigned int sg_len, enum dma_transfer_direction direction,
918 unsigned long flags, void *context);
921 size_t period_len, enum dma_transfer_direction direction,
922 unsigned long flags);
925 unsigned long flags);
928 unsigned long flags);
937 enum dma_status (*device_tx_status)(struct dma_chan *chan,
950 if (chan->device->device_config) in dmaengine_slave_config()
951 return chan->device->device_config(chan, config); in dmaengine_slave_config()
953 return -ENOSYS; in dmaengine_slave_config()
956 static inline bool is_slave_direction(enum dma_transfer_direction direction) in is_slave_direction()
964 enum dma_transfer_direction dir, unsigned long flags) in dmaengine_prep_slave_single() argument
971 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) in dmaengine_prep_slave_single()
974 return chan->device->device_prep_slave_sg(chan, &sg, 1, in dmaengine_prep_slave_single()
975 dir, flags, NULL); in dmaengine_prep_slave_single()
980 enum dma_transfer_direction dir, unsigned long flags) in dmaengine_prep_slave_sg() argument
982 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) in dmaengine_prep_slave_sg()
985 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, in dmaengine_prep_slave_sg()
986 dir, flags, NULL); in dmaengine_prep_slave_sg()
993 enum dma_transfer_direction dir, unsigned long flags, in dmaengine_prep_rio_sg() argument
996 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) in dmaengine_prep_rio_sg()
999 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, in dmaengine_prep_rio_sg()
1000 dir, flags, rio_ext); in dmaengine_prep_rio_sg()
1006 size_t period_len, enum dma_transfer_direction dir, in dmaengine_prep_dma_cyclic()
1007 unsigned long flags) in dmaengine_prep_dma_cyclic() argument
1009 if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic) in dmaengine_prep_dma_cyclic()
1012 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, in dmaengine_prep_dma_cyclic()
1013 period_len, dir, flags); in dmaengine_prep_dma_cyclic()
1018 unsigned long flags) in dmaengine_prep_interleaved_dma() argument
1020 if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma) in dmaengine_prep_interleaved_dma()
1022 if (flags & DMA_PREP_REPEAT && in dmaengine_prep_interleaved_dma()
1023 !test_bit(DMA_REPEAT, chan->device->cap_mask.bits)) in dmaengine_prep_interleaved_dma()
1026 return chan->device->device_prep_interleaved_dma(chan, xt, flags); in dmaengine_prep_interleaved_dma()
1030 * dmaengine_prep_dma_memset() - Prepare a DMA memset descriptor.
1033 * @value: Treated as a single byte value that fills the destination buffer
1035 * @flags: DMA engine flags
1039 unsigned long flags) in dmaengine_prep_dma_memset() argument
1041 if (!chan || !chan->device || !chan->device->device_prep_dma_memset) in dmaengine_prep_dma_memset()
1044 return chan->device->device_prep_dma_memset(chan, dest, value, in dmaengine_prep_dma_memset()
1045 len, flags); in dmaengine_prep_dma_memset()
1050 size_t len, unsigned long flags) in dmaengine_prep_dma_memcpy() argument
1052 if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy) in dmaengine_prep_dma_memcpy()
1055 return chan->device->device_prep_dma_memcpy(chan, dest, src, in dmaengine_prep_dma_memcpy()
1056 len, flags); in dmaengine_prep_dma_memcpy()
1060 enum dma_desc_metadata_mode mode) in dmaengine_is_metadata_mode_supported()
1065 return !!(chan->device->desc_metadata_modes & mode); in dmaengine_is_metadata_mode_supported()
1079 return -EINVAL; in dmaengine_desc_attach_metadata()
1090 return -EINVAL; in dmaengine_desc_set_metadata_len()
1095 * dmaengine_terminate_all() - Terminate all active DMA transfers
1103 if (chan->device->device_terminate_all) in dmaengine_terminate_all()
1104 return chan->device->device_terminate_all(chan); in dmaengine_terminate_all()
1106 return -ENOSYS; in dmaengine_terminate_all()
1110 * dmaengine_terminate_async() - Terminate all active DMA transfers
1124 * This function can be called from atomic context as well as from within a
1132 if (chan->device->device_terminate_all) in dmaengine_terminate_async()
1133 return chan->device->device_terminate_all(chan); in dmaengine_terminate_async()
1135 return -EINVAL; in dmaengine_terminate_async()
1139 * dmaengine_synchronize() - Synchronize DMA channel termination
1152 * This function must only be called from non-atomic context and must not be
1160 if (chan->device->device_synchronize) in dmaengine_synchronize()
1161 chan->device->device_synchronize(chan); in dmaengine_synchronize()
1165 * dmaengine_terminate_sync() - Terminate all active DMA transfers
1174 * This function must only be called from non-atomic context and must not be
1193 if (chan->device->device_pause) in dmaengine_pause()
1194 return chan->device->device_pause(chan); in dmaengine_pause()
1196 return -ENOSYS; in dmaengine_pause()
1201 if (chan->device->device_resume) in dmaengine_resume()
1202 return chan->device->device_resume(chan); in dmaengine_resume()
1204 return -ENOSYS; in dmaengine_resume()
1207 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan, in dmaengine_tx_status()
1210 return chan->device->device_tx_status(chan, cookie, state); in dmaengine_tx_status()
1215 return desc->tx_submit(desc); in dmaengine_submit()
1218 static inline bool dmaengine_check_align(enum dmaengine_alignment align, in dmaengine_check_align()
1221 return !(((1 << align) - 1) & (off1 | off2 | len)); in dmaengine_check_align()
1227 return dmaengine_check_align(dev->copy_align, off1, off2, len); in is_dma_copy_aligned()
1233 return dmaengine_check_align(dev->xor_align, off1, off2, len); in is_dma_xor_aligned()
1239 return dmaengine_check_align(dev->pq_align, off1, off2, len); in is_dma_pq_aligned()
1245 return dmaengine_check_align(dev->fill_align, off1, off2, len); in is_dma_fill_aligned()
1251 dma->max_pq = maxpq; in dma_set_maxpq()
1253 dma->max_pq |= DMA_HAS_PQ_CONTINUE; in dma_set_maxpq()
1256 static inline bool dmaf_continue(enum dma_ctrl_flags flags) in dmaf_continue() argument
1258 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; in dmaf_continue()
1261 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) in dmaf_p_disabled_continue() argument
1263 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; in dmaf_p_disabled_continue()
1265 return (flags & mask) == mask; in dmaf_p_disabled_continue()
1270 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; in dma_dev_has_pq_continue()
1275 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; in dma_dev_to_maxpq()
1278 /* dma_maxpq - reduce maxpq in the face of continued operations
1279 * @dma - dma device with PQ capability
1280 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1284 * 1/ {00} * P : remove P from Q', but use it as a source for P'
1291 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) in dma_maxpq() argument
1293 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) in dma_maxpq()
1295 if (dmaf_p_disabled_continue(flags)) in dma_maxpq()
1296 return dma_dev_to_maxpq(dma) - 1; in dma_maxpq()
1297 if (dmaf_continue(flags)) in dma_maxpq()
1298 return dma_dev_to_maxpq(dma) - 3; in dma_maxpq()
1318 return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl, in dmaengine_get_dst_icg()
1319 chunk->icg, chunk->dst_icg); in dmaengine_get_dst_icg()
1325 return dmaengine_get_icg(xt->src_inc, xt->src_sgl, in dmaengine_get_src_icg()
1326 chunk->icg, chunk->src_icg); in dmaengine_get_src_icg()
1329 /* --- public DMA engine API --- */
1359 async_dma_find_channel(enum dma_transaction_type type) in async_dma_find_channel()
1369 tx->flags |= DMA_CTRL_ACK; in async_tx_ack()
1374 tx->flags &= ~DMA_CTRL_ACK; in async_tx_clear_ack()
1379 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; in async_tx_test_ack()
1384 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) in __dma_cap_set()
1386 set_bit(tx_type, dstp->bits); in __dma_cap_set()
1391 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) in __dma_cap_clear()
1393 clear_bit(tx_type, dstp->bits); in __dma_cap_clear()
1399 bitmap_zero(dstp->bits, DMA_TX_TYPE_END); in __dma_cap_zero()
1404 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) in __dma_has_cap()
1406 return test_bit(tx_type, srcp->bits); in __dma_has_cap()
1413 * dma_async_issue_pending - flush pending transactions to HW
1421 chan->device->device_issue_pending(chan); in dma_async_issue_pending()
1425 * dma_async_is_tx_complete - poll for transaction completion
1433 * the status of multiple cookies without re-checking hardware state.
1435 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, in dma_async_is_tx_complete()
1439 enum dma_status status; in dma_async_is_tx_complete()
1441 status = chan->device->device_tx_status(chan, cookie, &state); in dma_async_is_tx_complete()
1450 * dma_async_is_complete - test a cookie against chan state
1458 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, in dma_async_is_complete()
1477 st->last = last; in dma_set_tx_state()
1478 st->used = used; in dma_set_tx_state()
1479 st->residue = residue; in dma_set_tx_state()
1483 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
1484 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
1485 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
1497 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) in dma_find_channel()
1501 static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) in dma_sync_wait()
1505 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) in dma_wait_for_async_tx()
1522 return ERR_PTR(-ENODEV); in dma_request_chan()
1527 return ERR_PTR(-ENODEV); in dma_request_chan_by_mask()
1535 return -ENXIO; in dma_get_slave_caps()
1544 ret = dma_get_slave_caps(tx->chan, &caps); in dmaengine_desc_set_reuse()
1549 return -EPERM; in dmaengine_desc_set_reuse()
1551 tx->flags |= DMA_CTRL_REUSE; in dmaengine_desc_set_reuse()
1557 tx->flags &= ~DMA_CTRL_REUSE; in dmaengine_desc_clear_reuse()
1562 return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE; in dmaengine_desc_test_reuse()
1569 return -EPERM; in dmaengine_desc_free()
1571 return desc->desc_free(desc); in dmaengine_desc_free()
1574 /* --- DMA device --- */
1614 dmaengine_get_direction_text(enum dma_transfer_direction dir) in dmaengine_get_direction_text()
1632 if (chan->dev->chan_dma_dev) in dmaengine_get_dma_device()
1633 return &chan->dev->device; in dmaengine_get_dma_device()
1635 return chan->device->dev; in dmaengine_get_dma_device()