Lines Matching full:ccs

551  * Intel color control surface (CCS) for render compression
555  * the CCS will be plane index 1.
557  * Each CCS tile matches a 1024x512 pixel area of the main surface.
558  * To match certain aspects of the 3D hardware the CCS is
560  * the CCS pitch must be specified in multiples of 128 bytes.
562  * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
571  * Intel color control surfaces (CCS) for Gen-12 render compression.
573  * The main surface is Y-tiled and at plane index 0, the CCS is linear and
574  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
575  * main surface. In other words, 4 bits in CCS map to a main surface cache
582  * Intel color control surfaces (CCS) for Gen-12 media compression
584  * The main surface is Y-tiled and at plane index 0, the CCS is linear and
585  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
586  * main surface. In other words, 4 bits in CCS map to a main surface cache
588  * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
590  * planes 2 and 3 for the respective CCS.
595  * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
598  * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
607  * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
625  * Intel color control surfaces (CCS) for DG2 render compression.
627  * The main surface is Tile 4 and at plane index 0. The CCS data is stored
629  * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
635  * Intel color control surfaces (CCS) for DG2 media compression.
639  * 0 and 1, respectively. The CCS for all planes are stored outside of the
641  * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
647  * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
649  * The main surface is Tile 4 and at plane index 0. The CCS data is stored
651  * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
661  * Intel Color Control Surfaces (CCS) for display ver. 14 render compression.
663  * The main surface is tile4 and at plane index 0, the CCS is linear and
664  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
665  * main surface. In other words, 4 bits in CCS map to a main surface cache
672  * Intel Color Control Surfaces (CCS) for display ver. 14 media compression
674  * The main surface is tile4 and at plane index 0, the CCS is linear and
675  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
676  * main surface. In other words, 4 bits in CCS map to a main surface cache
678  * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
680  * planes 2 and 3 for the respective CCS.
685  * Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render
688  * The main surface is tile4 and is at plane index 0 whereas CCS is linear
697  * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line