Lines Matching +full:6 +full:- +full:11
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5640.h -- RT5640 ALSA SoC audio driver
15 #include <dt-bindings/sound/rt5640.h>
22 /* I/O - Output */
27 /* I/O - Input */
31 /* I/O - ADC/DAC/DMIC */
38 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
78 /* Format - ADC/DAC */
84 /* Function - Analog */
102 /* Function - Digital */
189 #define RT5640_VOL_R_MUTE (0x1 << 6)
190 #define RT5640_VOL_R_SFT 6
209 #define RT5640_IN_DF2 (0x1 << 6)
210 #define RT5640_IN_SFT2 6
278 #define RT5640_M_ADC_R1 (0x1 << 6)
279 #define RT5640_M_ADC_R1_SFT 6
297 #define RT5640_M_MONO_ADC_R1 (0x1 << 6)
298 #define RT5640_M_MONO_ADC_R1_SFT 6
318 #define RT5640_M_IF1_DAC_R (0x1 << 6)
319 #define RT5640_M_IF1_DAC_R_SFT 6
328 #define RT5640_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
329 #define RT5640_DAC_L2_STO_L_VOL_SFT 11
332 #define RT5640_M_DAC_R1 (0x1 << 6)
333 #define RT5640_M_DAC_R1_SFT 6
350 #define RT5640_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
351 #define RT5640_DAC_L2_MONO_L_VOL_SFT 11
356 #define RT5640_M_DAC_R1_MONO_R (0x1 << 6)
357 #define RT5640_M_DAC_R1_MONO_R_SFT 6
378 #define RT5640_M_STO_R_DAC_R (0x1 << 11)
379 #define RT5640_M_STO_R_DAC_R_SFT 11
409 #define RT5640_IF2_ADC_L_SEL_MASK (0x1 << 11)
410 #define RT5640_IF2_ADC_L_SEL_SFT 11
411 #define RT5640_IF2_ADC_L_SEL_TXDP (0x0 << 11)
412 #define RT5640_IF2_ADC_L_SEL_PASS (0x1 << 11)
423 #define RT5640_RXDP_SEL_MASK (0x3 << 6)
424 #define RT5640_RXDP_SEL_SFT 6
425 #define RT5640_RXDP_SEL_NOR (0x0 << 6)
426 #define RT5640_RXDP_SEL_L2R (0x1 << 6)
427 #define RT5640_RXDP_SEL_R2L (0x2 << 6)
428 #define RT5640_RXDP_SEL_SWAP (0x3 << 6)
467 #define RT5640_IF3_DAC_SEL_MASK (0x3 << 6)
468 #define RT5640_IF3_DAC_SEL_SFT 6
469 #define RT5640_IF3_DAC_SEL_NOR (0x0 << 6)
470 #define RT5640_IF3_DAC_SEL_SWAP (0x1 << 6)
471 #define RT5640_IF3_DAC_SEL_L2R (0x2 << 6)
472 #define RT5640_IF3_DAC_SEL_R2L (0x3 << 6)
497 #define RT5640_M_HP_L_RM_L (0x1 << 6)
498 #define RT5640_M_HP_L_RM_L_SFT 6
529 #define RT5640_M_HP_R_RM_R (0x1 << 6)
530 #define RT5640_M_HP_R_RM_R_SFT 6
563 #define RT5640_G_OM_L_SM_L_MASK (0x3 << 6)
564 #define RT5640_G_OM_L_SM_L_SFT 6
585 #define RT5640_G_OM_R_SM_R_MASK (0x3 << 6)
586 #define RT5640_G_OM_R_SM_R_SFT 6
607 #define RT5640_M_BST1_SPM_L (0x1 << 11)
608 #define RT5640_M_BST1_SPM_L_SFT 11
615 #define RT5640_M_BST1_SPM_R (0x1 << 11)
616 #define RT5640_M_BST1_SPM_R_SFT 11
631 #define RT5640_M_BST1_MM (0x1 << 11)
632 #define RT5640_M_BST1_MM_SFT 11
661 #define RT5640_M_BST2_OM_L (0x1 << 6)
662 #define RT5640_M_BST2_OM_L_SFT 6
701 #define RT5640_M_BST2_OM_R (0x1 << 6)
702 #define RT5640_M_BST2_OM_R_SFT 6
725 #define RT5640_G_LOUTMIX_MASK (0x1 << 11)
726 #define RT5640_G_LOUTMIX_SFT 11
735 #define RT5640_PWR_DAC_R1 (0x1 << 11)
736 #define RT5640_PWR_DAC_R1_BIT 11
739 #define RT5640_PWR_DAC_R2 (0x1 << 6)
740 #define RT5640_PWR_DAC_R2_BIT 6
767 #define RT5640_PWR_BG (0x1 << 11)
768 #define RT5640_PWR_BG_BIT 11
775 #define RT5640_PWR_HP_R (0x1 << 6)
776 #define RT5640_PWR_HP_R_BIT 6
795 #define RT5640_PWR_MB1 (0x1 << 11)
796 #define RT5640_PWR_MB1_BIT 11
809 #define RT5640_PWR_RM_L (0x1 << 11)
810 #define RT5640_PWR_RM_L_BIT 11
823 #define RT5640_PWR_HV_L (0x1 << 11)
824 #define RT5640_PWR_HV_L_BIT 11
867 #define RT5640_I2S2_SDI_MASK (0x1 << 6)
868 #define RT5640_I2S2_SDI_SFT 6
869 #define RT5640_I2S2_SDI_I2S1 (0x0 << 6)
870 #define RT5640_I2S2_SDI_I2S2 (0x1 << 6)
887 #define RT5640_I2S_BCLK_MS2_MASK (0x1 << 11)
888 #define RT5640_I2S_BCLK_MS2_SFT 11
889 #define RT5640_I2S_BCLK_MS2_32 (0x0 << 11)
890 #define RT5640_I2S_BCLK_MS2_64 (0x1 << 11)
941 #define RT5640_DAHPF_EN (0x1 << 11)
942 #define RT5640_DAHPF_EN_SFT 11
963 #define RT5640_DMIC_1_DP_MASK (0x1 << 11)
964 #define RT5640_DMIC_1_DP_SFT 11
965 #define RT5640_DMIC_1_DP_GPIO3 (0x0 << 11)
966 #define RT5640_DMIC_1_DP_IN1P (0x1 << 11)
1013 #define RT5640_PLL_M_BP (0x1 << 11)
1014 #define RT5640_PLL_M_BP_SFT 11
1059 #define RT5640_ADC_M_MASK (0x1 << 11)
1060 #define RT5640_ADC_M_SFT 11
1061 #define RT5640_ADC_M_NOR (0x0 << 11)
1062 #define RT5640_ADC_M_ASYN (0x1 << 11)
1120 #define RT5640_CLSD_OM_MASK (0x1 << 11)
1121 #define RT5640_CLSD_OM_SFT 11
1122 #define RT5640_CLSD_OM_MONO (0x0 << 11)
1123 #define RT5640_CLSD_OM_STO (0x1 << 11)
1146 #define RT5640_RSTN_MASK (0x1 << 6)
1147 #define RT5640_RSTN_SFT 6
1148 #define RT5640_RSTN_DIS (0x0 << 6)
1149 #define RT5640_RSTN_EN (0x1 << 6)
1184 #define RT5640_BPS_MASK (0x1 << 11)
1185 #define RT5640_BPS_SFT 11
1186 #define RT5640_BPS_DIS (0x0 << 11)
1187 #define RT5640_BPS_EN (0x1 << 11)
1202 #define RT5640_DIG_DP_MASK (0x1 << 6)
1203 #define RT5640_DIG_DP_SFT 6
1204 #define RT5640_DIG_DP_DIS (0x0 << 6)
1205 #define RT5640_DIG_DP_EN (0x1 << 6)
1224 #define RT5640_CP_FQ_96_KHZ 6
1228 #define RT5640_OSW_L_MASK (0x1 << 11)
1229 #define RT5640_OSW_L_SFT 11
1230 #define RT5640_OSW_L_DIS (0x0 << 11)
1231 #define RT5640_OSW_L_EN (0x1 << 11)
1241 #define RT5640_IB_HP_MASK (0x3 << 6)
1242 #define RT5640_IB_HP_SFT 6
1243 #define RT5640_IB_HP_125IL (0x0 << 6)
1244 #define RT5640_IB_HP_25IL (0x1 << 6)
1245 #define RT5640_IB_HP_5IL (0x2 << 6)
1246 #define RT5640_IB_HP_1IL (0x3 << 6)
1275 #define RT5640_MIC1_OVCD_MASK (0x1 << 11)
1276 #define RT5640_MIC1_OVCD_SFT 11
1277 #define RT5640_MIC1_OVCD_DIS (0x0 << 11)
1278 #define RT5640_MIC1_OVCD_EN (0x1 << 11)
1288 #define RT5640_MIC2_OVTH_MASK (0x3 << 6)
1289 #define RT5640_MIC2_OVTH_SFT 6
1290 #define RT5640_MIC2_OVTH_600UA (0x0 << 6)
1291 #define RT5640_MIC2_OVTH_1500UA (0x1 << 6)
1292 #define RT5640_MIC2_OVTH_2000UA (0x2 << 6)
1329 #define RT5640_EQ_HPF2_MASK (0x1 << 6)
1330 #define RT5640_EQ_HPF2_SFT 6
1331 #define RT5640_EQ_HPF2_DIS (0x0 << 6)
1332 #define RT5640_EQ_HPF2_EN (0x1 << 6)
1409 #define RT5640_DRC_AGC_NG_MASK (0x1 << 6)
1410 #define RT5640_DRC_AGC_NG_SFT 6
1411 #define RT5640_DRC_AGC_NG_DIS (0x0 << 6)
1412 #define RT5640_DRC_AGC_NG_EN (0x1 << 6)
1435 #define RT5640_ANC_SN_MASK (0x1 << 11)
1436 #define RT5640_ANC_SN_SFT 11
1437 #define RT5640_ANC_SN_DIS (0x0 << 11)
1438 #define RT5640_ANC_SN_EN (0x1 << 11)
1453 #define RT5640_ANC_SW_MASK (0x1 << 6)
1454 #define RT5640_ANC_SW_SFT 6
1455 #define RT5640_ANC_SW_NOR (0x0 << 6)
1456 #define RT5640_ANC_SW_AUTO (0x1 << 6)
1471 #define RT5640_ANC_CD_MASK (0x1 << 6)
1472 #define RT5640_ANC_CD_SFT 6
1473 #define RT5640_ANC_CD_BOTH (0x0 << 6)
1474 #define RT5640_ANC_CD_IND (0x1 << 6)
1488 #define RT5640_JD_HP_MASK (0x1 << 11)
1489 #define RT5640_JD_HP_SFT 11
1490 #define RT5640_JD_HP_DIS (0x0 << 11)
1491 #define RT5640_JD_HP_EN (0x1 << 11)
1508 #define RT5640_JD_SPR_TRG_MASK (0x1 << 6)
1509 #define RT5640_JD_SPR_TRG_SFT 6
1510 #define RT5640_JD_SPR_TRG_LO (0x0 << 6)
1511 #define RT5640_JD_SPR_TRG_HI (0x1 << 6)
1576 #define RT5640_JD_P_MASK (0x1 << 11)
1577 #define RT5640_JD_P_SFT 11
1578 #define RT5640_JD_P_NOR (0x0 << 11)
1579 #define RT5640_JD_P_INV (0x1 << 11)
1594 #define RT5640_MB1_OC_STKY_MASK (0x1 << 11)
1595 #define RT5640_MB1_OC_STKY_SFT 11
1596 #define RT5640_MB1_OC_STKY_DIS (0x0 << 11)
1597 #define RT5640_MB1_OC_STKY_EN (0x1 << 11)
1606 #define RT5640_MB2_OC_P_MASK (0x1 << 6)
1607 #define RT5640_MB2_OC_P_SFT 6
1608 #define RT5640_MB2_OC_P_NOR (0x0 << 6)
1609 #define RT5640_MB2_OC_P_INV (0x1 << 6)
1636 #define RT5640_GP4_PIN_MASK (0x1 << 11)
1637 #define RT5640_GP4_PIN_SFT 11
1638 #define RT5640_GP4_PIN_GPIO4 (0x0 << 11)
1639 #define RT5640_GP4_PIN_DMIC2_SDA (0x1 << 11)
1650 #define RT5640_GP4_PF_MASK (0x1 << 11)
1651 #define RT5640_GP4_PF_SFT 11
1652 #define RT5640_GP4_PF_IN (0x0 << 11)
1653 #define RT5640_GP4_PF_OUT (0x1 << 11)
1670 #define RT5640_GP3_P_MASK (0x1 << 6)
1671 #define RT5640_GP3_P_SFT 6
1672 #define RT5640_GP3_P_NOR (0x0 << 6)
1673 #define RT5640_GP3_P_INV (0x1 << 6)
1699 /* FM34-500 Register Control 1 (0xc4) */
1702 /* FM34-500 Register Control 2 (0xc5) */
1705 /* FM34-500 Register Control 3 (0xc6) */
1718 #define RT5640_DSP_PD_PIN_MASK (0x1 << 11)
1719 #define RT5640_DSP_PD_PIN_SFT 11
1720 #define RT5640_DSP_PD_PIN_LO (0x0 << 11)
1721 #define RT5640_DSP_PD_PIN_HI (0x1 << 11)
1740 #define RT5640_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1741 #define RT5640_SEQ1_ST_SFT 11
1742 #define RT5640_SEQ1_ST_RUN (0x0 << 11)
1743 #define RT5640_SEQ1_ST_FIN (0x1 << 11)
1768 #define RT5640_SEQ1_PT_RUN (0x1 << 6)
1769 #define RT5640_SEQ1_PT_RUN_BIT 6
1816 #define RT5640_M_BB_HPF_R_MASK (0x1 << 6)
1817 #define RT5640_M_BB_HPF_R_SFT 6
1836 #define RT5640_M_MP3_ORG_L_MASK (0x1 << 6)
1837 #define RT5640_M_MP3_ORG_L_SFT 6
1864 #define RT5640_3D_1F_MIX_MASK (0x3 << 11)
1865 #define RT5640_3D_1F_MIX_SFT 11
1876 #define RT5640_M_3D_REVB_MASK (0x1 << 6)
1877 #define RT5640_M_3D_REVB_SFT 6
1886 #define RT5640_1ST_HPF_MASK (0x1 << 11)
1887 #define RT5640_1ST_HPF_SFT 11
1888 #define RT5640_1ST_HPF_DIS (0x0 << 11)
1889 #define RT5640_1ST_HPF_EN (0x1 << 11)
1892 #define RT5640_ZD_T_MASK (0x3 << 6)
1893 #define RT5640_ZD_T_SFT 6
1902 #define RT5640_SI_DAC_MASK (0x1 << 11)
1903 #define RT5640_SI_DAC_SFT 11
1904 #define RT5640_SI_DAC_AUTO (0x0 << 11)
1905 #define RT5640_SI_DAC_TEST (0x1 << 11)
1914 #define RT5640_HPD_RCV_MASK (0x7 << 6)
1915 #define RT5640_HPD_RCV_SFT 6
1955 #define RT5640_ZCD_DIG_MASK (0x1 << 11)
1956 #define RT5640_ZCD_DIG_SFT 11
1957 #define RT5640_ZCD_DIG_DIS (0x0 << 11)
1958 #define RT5640_ZCD_DIG_EN (0x1 << 11)
1968 #define RT5640_M_ZCD_SM_R (0x1 << 6)
1987 #define RT5640_MCLK_DET (0x1 << 11)
2038 #define RT5640_HPF_FC_MASK (0x3f << 6)
2039 #define RT5640_HPF_FC_SFT 6
2052 #define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2054 #define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */