Lines Matching +full:xcvr +full:- +full:setup
1 // SPDX-License-Identifier: GPL-2.0
18 #include "imx-pcm.h"
61 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
98 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_arc_mode_put() local
99 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in fsl_xcvr_arc_mode_put()
100 unsigned int *item = ucontrol->value.enumerated.item; in fsl_xcvr_arc_mode_put()
102 xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]); in fsl_xcvr_arc_mode_put()
111 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_arc_mode_get() local
113 ucontrol->value.enumerated.item[0] = xcvr->arc_mode; in fsl_xcvr_arc_mode_get()
133 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in fsl_xcvr_type_capds_bytes_info()
134 uinfo->count = FSL_XCVR_CAPDS_SIZE; in fsl_xcvr_type_capds_bytes_info()
143 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_capds_get() local
145 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE); in fsl_xcvr_capds_get()
154 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_capds_put() local
156 memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE); in fsl_xcvr_capds_put()
173 struct snd_soc_card *card = dai->component->card; in fsl_xcvr_activate_ctl()
177 lockdep_assert_held(&card->snd_card->controls_rwsem); in fsl_xcvr_activate_ctl()
181 return -ENOENT; in fsl_xcvr_activate_ctl()
183 enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0); in fsl_xcvr_activate_ctl()
188 kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_WRITE; in fsl_xcvr_activate_ctl()
190 kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE; in fsl_xcvr_activate_ctl()
192 snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id); in fsl_xcvr_activate_ctl()
201 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_mode_put() local
202 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in fsl_xcvr_mode_put()
203 unsigned int *item = ucontrol->value.enumerated.item; in fsl_xcvr_mode_put()
204 struct snd_soc_card *card = dai->component->card; in fsl_xcvr_mode_put()
207 xcvr->mode = snd_soc_enum_item_to_val(e, item[0]); in fsl_xcvr_mode_put()
210 (xcvr->mode == FSL_XCVR_MODE_ARC)); in fsl_xcvr_mode_put()
212 (xcvr->mode == FSL_XCVR_MODE_EARC)); in fsl_xcvr_mode_put()
214 rtd = snd_soc_get_pcm_runtime(card, card->dai_link); in fsl_xcvr_mode_put()
215 rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count = in fsl_xcvr_mode_put()
216 (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0); in fsl_xcvr_mode_put()
224 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_mode_get() local
226 ucontrol->value.enumerated.item[0] = xcvr->mode; in fsl_xcvr_mode_get()
235 SOC_ENUM_EXT("XCVR Mode", fsl_xcvr_mode_enum,
239 static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy) in fsl_xcvr_ai_write() argument
241 struct device *dev = &xcvr->pdev->dev; in fsl_xcvr_ai_write()
248 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF); in fsl_xcvr_ai_write()
249 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg); in fsl_xcvr_ai_write()
250 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data); in fsl_xcvr_ai_write()
251 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); in fsl_xcvr_ai_write()
253 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val, in fsl_xcvr_ai_write()
262 static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx) in fsl_xcvr_en_phy_pll() argument
264 struct device *dev = &xcvr->pdev->dev; in fsl_xcvr_en_phy_pll()
268 if (xcvr->soc_data->spdif_only) in fsl_xcvr_en_phy_pll()
279 return -EINVAL; in fsl_xcvr_en_phy_pll()
284 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, in fsl_xcvr_en_phy_pll()
292 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_BANDGAP_SET, in fsl_xcvr_en_phy_pll()
296 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi, 0); in fsl_xcvr_en_phy_pll()
298 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn, 0); in fsl_xcvr_en_phy_pll()
300 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd, 0); in fsl_xcvr_en_phy_pll()
302 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, in fsl_xcvr_en_phy_pll()
306 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_CLR, in fsl_xcvr_en_phy_pll()
311 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, in fsl_xcvr_en_phy_pll()
314 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, in fsl_xcvr_en_phy_pll()
316 } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */ in fsl_xcvr_en_phy_pll()
318 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, in fsl_xcvr_en_phy_pll()
321 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, in fsl_xcvr_en_phy_pll()
325 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, in fsl_xcvr_en_phy_pll()
328 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, in fsl_xcvr_en_phy_pll()
332 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ in fsl_xcvr_en_phy_pll()
334 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, in fsl_xcvr_en_phy_pll()
338 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET, in fsl_xcvr_en_phy_pll()
341 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) in fsl_xcvr_en_phy_pll()
343 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, in fsl_xcvr_en_phy_pll()
345 else /* PHY: CTRL_SET: ARC RX setup */ in fsl_xcvr_en_phy_pll()
346 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, in fsl_xcvr_en_phy_pll()
349 fsl_xcvr_phy_arc_cfg[xcvr->arc_mode], 1); in fsl_xcvr_en_phy_pll()
358 static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq) in fsl_xcvr_en_aud_pll() argument
360 struct device *dev = &xcvr->pdev->dev; in fsl_xcvr_en_aud_pll()
363 freq = xcvr->soc_data->spdif_only ? freq / 5 : freq; in fsl_xcvr_en_aud_pll()
364 clk_disable_unprepare(xcvr->phy_clk); in fsl_xcvr_en_aud_pll()
365 ret = clk_set_rate(xcvr->phy_clk, freq); in fsl_xcvr_en_aud_pll()
370 ret = clk_prepare_enable(xcvr->phy_clk); in fsl_xcvr_en_aud_pll()
376 if (xcvr->soc_data->spdif_only) in fsl_xcvr_en_aud_pll()
379 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, in fsl_xcvr_en_aud_pll()
386 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ in fsl_xcvr_en_aud_pll()
388 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, in fsl_xcvr_en_aud_pll()
392 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET, in fsl_xcvr_en_aud_pll()
396 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, in fsl_xcvr_en_aud_pll()
410 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_prepare() local
411 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_xcvr_prepare()
413 u32 r = substream->runtime->rate, ch = substream->runtime->channels; in fsl_xcvr_prepare()
417 switch (xcvr->mode) { in fsl_xcvr_prepare()
419 if (xcvr->soc_data->spdif_only && tx) { in fsl_xcvr_prepare()
420 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET, in fsl_xcvr_prepare()
424 dev_err(dai->dev, "Failed to set bypass fem: %d\n", ret); in fsl_xcvr_prepare()
431 ret = fsl_xcvr_en_aud_pll(xcvr, fout); in fsl_xcvr_prepare()
433 dev_err(dai->dev, "Failed to set TX freq %u: %d\n", in fsl_xcvr_prepare()
438 ret = regmap_write(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET, in fsl_xcvr_prepare()
441 dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret); in fsl_xcvr_prepare()
446 * set SPDIF MODE - this flag is used to gate in fsl_xcvr_prepare()
456 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET, in fsl_xcvr_prepare()
462 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); in fsl_xcvr_prepare()
466 ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx); in fsl_xcvr_prepare()
468 dev_err(dai->dev, "Failed to set RX freq %u: %d\n", in fsl_xcvr_prepare()
477 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET, in fsl_xcvr_prepare()
481 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); in fsl_xcvr_prepare()
486 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_CLR, in fsl_xcvr_prepare()
490 dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret); in fsl_xcvr_prepare()
503 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, in fsl_xcvr_prepare()
506 dev_err(dai->dev, "Error while setting IER0: %d\n", ret); in fsl_xcvr_prepare()
513 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl); in fsl_xcvr_prepare()
515 dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret); in fsl_xcvr_prepare()
526 struct snd_pcm_runtime *rt = substream->runtime; in fsl_xcvr_constr()
545 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_startup() local
546 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_xcvr_startup()
549 if (xcvr->streams & BIT(substream->stream)) { in fsl_xcvr_startup()
550 dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R"); in fsl_xcvr_startup()
551 return -EBUSY; in fsl_xcvr_startup()
558 if (xcvr->soc_data->use_edma) in fsl_xcvr_startup()
559 snd_pcm_hw_constraint_step(substream->runtime, 0, in fsl_xcvr_startup()
561 tx ? xcvr->dma_prms_tx.maxburst : in fsl_xcvr_startup()
562 xcvr->dma_prms_rx.maxburst); in fsl_xcvr_startup()
564 switch (xcvr->mode) { in fsl_xcvr_startup()
578 xcvr->streams |= BIT(substream->stream); in fsl_xcvr_startup()
580 if (!xcvr->soc_data->spdif_only) { in fsl_xcvr_startup()
581 struct snd_soc_card *card = dai->component->card; in fsl_xcvr_startup()
583 /* Disable XCVR controls if there is stream started */ in fsl_xcvr_startup()
584 down_read(&card->snd_card->controls_rwsem); in fsl_xcvr_startup()
588 up_read(&card->snd_card->controls_rwsem); in fsl_xcvr_startup()
597 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_shutdown() local
598 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_xcvr_shutdown()
602 xcvr->streams &= ~BIT(substream->stream); in fsl_xcvr_shutdown()
604 /* Enable XCVR controls if there is no stream started */ in fsl_xcvr_shutdown()
605 if (!xcvr->streams) { in fsl_xcvr_shutdown()
606 if (!xcvr->soc_data->spdif_only) { in fsl_xcvr_shutdown()
607 struct snd_soc_card *card = dai->component->card; in fsl_xcvr_shutdown()
609 down_read(&card->snd_card->controls_rwsem); in fsl_xcvr_shutdown()
612 (xcvr->mode == FSL_XCVR_MODE_ARC)); in fsl_xcvr_shutdown()
614 (xcvr->mode == FSL_XCVR_MODE_EARC)); in fsl_xcvr_shutdown()
615 up_read(&card->snd_card->controls_rwsem); in fsl_xcvr_shutdown()
617 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, in fsl_xcvr_shutdown()
620 dev_err(dai->dev, "Failed to set IER0: %d\n", ret); in fsl_xcvr_shutdown()
625 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) in fsl_xcvr_shutdown()
629 if (xcvr->mode == FSL_XCVR_MODE_EARC) { in fsl_xcvr_shutdown()
635 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); in fsl_xcvr_shutdown()
637 dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret); in fsl_xcvr_shutdown()
645 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_trigger() local
646 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_xcvr_trigger()
654 switch (xcvr->mode) { in fsl_xcvr_trigger()
657 ret = regmap_write(xcvr->regmap, in fsl_xcvr_trigger()
661 dev_err(dai->dev, "err updating isr %d\n", ret); in fsl_xcvr_trigger()
666 ret = regmap_write(xcvr->regmap, in fsl_xcvr_trigger()
670 dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret); in fsl_xcvr_trigger()
678 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_trigger()
681 dev_err(dai->dev, "Failed to enable DMA: %d\n", ret); in fsl_xcvr_trigger()
686 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_trigger()
690 dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret); in fsl_xcvr_trigger()
699 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_trigger()
703 dev_err(dai->dev, "Failed to disable DMA: %d\n", ret); in fsl_xcvr_trigger()
708 switch (xcvr->mode) { in fsl_xcvr_trigger()
710 ret = regmap_write(xcvr->regmap, in fsl_xcvr_trigger()
714 dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret); in fsl_xcvr_trigger()
717 if (xcvr->soc_data->spdif_only) in fsl_xcvr_trigger()
723 ret = regmap_write(xcvr->regmap, in fsl_xcvr_trigger()
727 dev_err(dai->dev, in fsl_xcvr_trigger()
736 return -EINVAL; in fsl_xcvr_trigger()
742 static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr) in fsl_xcvr_load_firmware() argument
744 struct device *dev = &xcvr->pdev->dev; in fsl_xcvr_load_firmware()
749 ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev); in fsl_xcvr_load_firmware()
755 rem = fw->size; in fsl_xcvr_load_firmware()
761 return -ENOMEM; in fsl_xcvr_load_firmware()
765 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_load_firmware()
779 memcpy_toio(xcvr->ram_addr, fw->data + off, out); in fsl_xcvr_load_firmware()
780 rem -= out; in fsl_xcvr_load_firmware()
784 memset_io(xcvr->ram_addr + out, 0, size - out); in fsl_xcvr_load_firmware()
788 memset_io(xcvr->ram_addr, 0, size); in fsl_xcvr_load_firmware()
808 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); in fsl_xcvr_load_firmware()
815 memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds, in fsl_xcvr_load_firmware()
823 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; in fsl_xcvr_type_iec958_info()
824 uinfo->count = 1; in fsl_xcvr_type_iec958_info()
832 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in fsl_xcvr_type_iec958_bytes_info()
833 uinfo->count = sizeof_field(struct snd_aes_iec958, status); in fsl_xcvr_type_iec958_bytes_info()
842 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_rx_cs_get() local
844 memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24); in fsl_xcvr_rx_cs_get()
853 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_tx_cs_get() local
855 memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24); in fsl_xcvr_tx_cs_get()
864 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_tx_cs_put() local
866 memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 24); in fsl_xcvr_tx_cs_put()
913 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); in fsl_xcvr_dai_probe() local
915 snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx); in fsl_xcvr_dai_probe()
917 if (xcvr->soc_data->spdif_only) in fsl_xcvr_dai_probe()
918 xcvr->mode = FSL_XCVR_MODE_SPDIF; in fsl_xcvr_dai_probe()
942 .stream_name = "CPU-Playback",
951 .stream_name = "CPU-Capture",
962 .name = "fsl-xcvr-dai",
1018 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); in fsl_xcvr_readable_reg() local
1020 if (xcvr->soc_data->spdif_only) in fsl_xcvr_readable_reg()
1091 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); in fsl_xcvr_writeable_reg() local
1093 if (xcvr->soc_data->spdif_only) in fsl_xcvr_writeable_reg()
1161 struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid; in irq0_isr() local
1162 struct device *dev = &xcvr->pdev->dev; in irq0_isr()
1163 struct regmap *regmap = xcvr->regmap; in irq0_isr()
1172 if (!xcvr->soc_data->spdif_only) { in irq0_isr()
1174 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in irq0_isr()
1179 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0; in irq0_isr()
1180 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0; in irq0_isr()
1183 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1; in irq0_isr()
1184 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1; in irq0_isr()
1190 memcpy_fromio(&xcvr->rx_iec958.status, reg_buff, in irq0_isr()
1191 sizeof(xcvr->rx_iec958.status)); in irq0_isr()
1193 val = *(u32 *)(xcvr->rx_iec958.status + i*4); in irq0_isr()
1194 *(u32 *)(xcvr->rx_iec958.status + i*4) = in irq0_isr()
1236 .fw_name = "imx/xcvr/xcvr-imx8mp.bin",
1245 { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data },
1246 { .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data},
1253 struct device *dev = &pdev->dev; in fsl_xcvr_probe()
1254 struct fsl_xcvr *xcvr; in fsl_xcvr_probe() local
1259 xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL); in fsl_xcvr_probe()
1260 if (!xcvr) in fsl_xcvr_probe()
1261 return -ENOMEM; in fsl_xcvr_probe()
1263 xcvr->pdev = pdev; in fsl_xcvr_probe()
1264 xcvr->soc_data = of_device_get_match_data(&pdev->dev); in fsl_xcvr_probe()
1266 xcvr->ipg_clk = devm_clk_get(dev, "ipg"); in fsl_xcvr_probe()
1267 if (IS_ERR(xcvr->ipg_clk)) { in fsl_xcvr_probe()
1269 return PTR_ERR(xcvr->ipg_clk); in fsl_xcvr_probe()
1272 xcvr->phy_clk = devm_clk_get(dev, "phy"); in fsl_xcvr_probe()
1273 if (IS_ERR(xcvr->phy_clk)) { in fsl_xcvr_probe()
1275 return PTR_ERR(xcvr->phy_clk); in fsl_xcvr_probe()
1278 xcvr->spba_clk = devm_clk_get(dev, "spba"); in fsl_xcvr_probe()
1279 if (IS_ERR(xcvr->spba_clk)) { in fsl_xcvr_probe()
1281 return PTR_ERR(xcvr->spba_clk); in fsl_xcvr_probe()
1284 xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg"); in fsl_xcvr_probe()
1285 if (IS_ERR(xcvr->pll_ipg_clk)) { in fsl_xcvr_probe()
1287 return PTR_ERR(xcvr->pll_ipg_clk); in fsl_xcvr_probe()
1290 xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram"); in fsl_xcvr_probe()
1291 if (IS_ERR(xcvr->ram_addr)) in fsl_xcvr_probe()
1292 return PTR_ERR(xcvr->ram_addr); in fsl_xcvr_probe()
1298 xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs, in fsl_xcvr_probe()
1300 if (IS_ERR(xcvr->regmap)) { in fsl_xcvr_probe()
1301 dev_err(dev, "failed to init XCVR regmap: %ld\n", in fsl_xcvr_probe()
1302 PTR_ERR(xcvr->regmap)); in fsl_xcvr_probe()
1303 return PTR_ERR(xcvr->regmap); in fsl_xcvr_probe()
1306 xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL); in fsl_xcvr_probe()
1307 if (IS_ERR(xcvr->reset)) { in fsl_xcvr_probe()
1308 dev_err(dev, "failed to get XCVR reset control\n"); in fsl_xcvr_probe()
1309 return PTR_ERR(xcvr->reset); in fsl_xcvr_probe()
1317 ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr); in fsl_xcvr_probe()
1327 return -EINVAL; in fsl_xcvr_probe()
1329 xcvr->dma_prms_rx.chan_name = "rx"; in fsl_xcvr_probe()
1330 xcvr->dma_prms_tx.chan_name = "tx"; in fsl_xcvr_probe()
1331 xcvr->dma_prms_rx.addr = rx_res->start; in fsl_xcvr_probe()
1332 xcvr->dma_prms_tx.addr = tx_res->start; in fsl_xcvr_probe()
1333 xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX; in fsl_xcvr_probe()
1334 xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX; in fsl_xcvr_probe()
1336 platform_set_drvdata(pdev, xcvr); in fsl_xcvr_probe()
1338 regcache_cache_only(xcvr->regmap, true); in fsl_xcvr_probe()
1364 pm_runtime_disable(&pdev->dev); in fsl_xcvr_remove()
1369 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); in fsl_xcvr_runtime_suspend() local
1377 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, in fsl_xcvr_runtime_suspend()
1382 if (!xcvr->soc_data->spdif_only) { in fsl_xcvr_runtime_suspend()
1384 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_runtime_suspend()
1391 regcache_cache_only(xcvr->regmap, true); in fsl_xcvr_runtime_suspend()
1393 clk_disable_unprepare(xcvr->spba_clk); in fsl_xcvr_runtime_suspend()
1394 clk_disable_unprepare(xcvr->phy_clk); in fsl_xcvr_runtime_suspend()
1395 clk_disable_unprepare(xcvr->pll_ipg_clk); in fsl_xcvr_runtime_suspend()
1396 clk_disable_unprepare(xcvr->ipg_clk); in fsl_xcvr_runtime_suspend()
1403 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); in fsl_xcvr_runtime_resume() local
1406 ret = reset_control_assert(xcvr->reset); in fsl_xcvr_runtime_resume()
1412 ret = clk_prepare_enable(xcvr->ipg_clk); in fsl_xcvr_runtime_resume()
1418 ret = clk_prepare_enable(xcvr->pll_ipg_clk); in fsl_xcvr_runtime_resume()
1424 ret = clk_prepare_enable(xcvr->phy_clk); in fsl_xcvr_runtime_resume()
1430 ret = clk_prepare_enable(xcvr->spba_clk); in fsl_xcvr_runtime_resume()
1436 regcache_cache_only(xcvr->regmap, false); in fsl_xcvr_runtime_resume()
1437 regcache_mark_dirty(xcvr->regmap); in fsl_xcvr_runtime_resume()
1438 ret = regcache_sync(xcvr->regmap); in fsl_xcvr_runtime_resume()
1445 if (xcvr->soc_data->spdif_only) in fsl_xcvr_runtime_resume()
1448 ret = reset_control_deassert(xcvr->reset); in fsl_xcvr_runtime_resume()
1454 ret = fsl_xcvr_load_firmware(xcvr); in fsl_xcvr_runtime_resume()
1461 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_runtime_resume()
1474 clk_disable_unprepare(xcvr->spba_clk); in fsl_xcvr_runtime_resume()
1476 clk_disable_unprepare(xcvr->phy_clk); in fsl_xcvr_runtime_resume()
1478 clk_disable_unprepare(xcvr->pll_ipg_clk); in fsl_xcvr_runtime_resume()
1480 clk_disable_unprepare(xcvr->ipg_clk); in fsl_xcvr_runtime_resume()
1496 .name = "fsl,imx8mp-audio-xcvr",
1505 MODULE_DESCRIPTION("NXP Audio Transceiver (XCVR) driver");