Lines Matching +full:816 +full:v
1181 @@ -497,7 +816,11 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
13325 +static int dw_hdmi_status_show(struct seq_file *s, void *v)
13485 +static int dw_hdmi_ctrl_show(struct seq_file *s, void *v)
13546 +static int dw_hdmi_phy_show(struct seq_file *s, void *v)
14820 @@ -815,6 +816,48 @@ void drm_send_event_locked(struct drm_device *dev, struct drm_pending_event *e)
15261 @@ -794,6 +816,7 @@ static const struct dma_buf_ops drm_gem_prime_dmabuf_ops = {
23205 +#define ROCKCHIP_PROP_ATTACH(prop, v) \
23206 + drm_object_attach_property(&connector->base, prop, v)
23813 +#define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
23817 +#define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
25530 -#define VOP_WIN_SET(vop, win, name, v) \
25531 - vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
25532 -#define VOP_SCL_SET(vop, win, name, v) \
25533 - vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
25534 -#define VOP_SCL_SET_EXT(vop, win, name, v) \
25536 - win->base, ~0, v, #name)
25544 -#define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \
25547 - vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
25556 -#define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \
25563 +#define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
25564 + vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
25566 +#define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
25569 - vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
25572 + v, reg.write_mask, relaxed); \
25577 +#define REG_SET(x, name, off, reg, v, relaxed) \
25578 + _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
25579 +#define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
25580 + _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
25582 +#define VOP_WIN_SET(x, win, name, v) \
25583 + REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
25584 +#define VOP_WIN_SET_EXT(x, win, ext, name, v) \
25585 + REG_SET(x, name, 0, win->ext->name, v, true)
25586 +#define VOP_SCL_SET(x, win, name, v) \
25587 + REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
25588 +#define VOP_SCL_SET_EXT(x, win, name, v) \
25589 + REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
25591 +#define VOP_CTRL_SET(x, name, v) \
25592 + REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
25597 +#define VOP_INTR_SET(vop, name, v) \
25599 + v, false)
25600 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
25601 - vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
25603 + mask, v, false)
25606 #define VOP_REG_SET(vop, group, name, v) \
25607 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
25630 -#define VOP_AFBC_SET(vop, name, v) \
25631 +#define VOP_GRF_SET(vop, reg, v) \
25635 - 0, ~0, v, #name); \
25637 + vop_grf_writel(vop, vop->data->grf_ctrl->reg, v); \
25868 +static inline void vop_grf_writel(struct vop *vop, struct vop_reg reg, u32 v)
25876 + val = (v << reg.shift) | (reg.mask << (reg.shift + 16));
25881 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
25883 writel(v, vop->regs + offset);
25889 - uint32_t _offset, uint32_t _mask, uint32_t v,
25892 + uint32_t mask, uint32_t shift, uint32_t v,
25908 - v = ((v << shift) & 0xffff) | (mask << (shift + 16));
25910 + v = ((v & mask) << shift) | (mask << (shift + 16));
25915 vop->regsbak[offset >> 2] = v;
25920 writel_relaxed(v, vop->regs + offset);
25922 writel(v, vop->regs + offset);
26075 +static inline void vop_write_lut(struct vop *vop, uint32_t offset, uint32_t v)
26077 + writel(v, vop->lut_regs + offset);
26741 * v v
30447 +#define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
30448 + drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
32330 +#define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK(h, l) << 16))
33492 +#define HIWORD_UPDATE(v, l, h) (((v) << (l)) | (GENMASK(h, l) << 16))
33495 +#define PX30_RGB_DATA_SYNC_BYPASS(v) HIWORD_UPDATE(v, 3, 3)
33496 +#define PX30_RGB_VOP_SEL(v) HIWORD_UPDATE(v, 2, 2)
33499 +#define RK1808_RGB_DATA_SYNC_BYPASS(v) HIWORD_UPDATE(v, 3, 3)
33502 +#define RV1106_IO_BYPASS_SEL(v) HIWORD_UPDATE(v, 0, 1)
33504 +#define RV1106_VOP_PIPE_BYPASS(v) HIWORD_UPDATE(v, 0, 1)
33507 +#define RV1126_LCDC_IO_BYPASS(v) HIWORD_UPDATE(v, 0, 0)
33519 +#define RK3568_RGB_DATA_BYPASS(v) HIWORD_UPDATE(v, 6, 6)
41498 /* enable HDMI 5V */
41512 + /* set bat 3.4v low and act irq */
41518 + /* set bat 3.0v low and act shutdown */
41564 + /* set bat 3.4v low and act irq */
41570 + /* set bat 3.0v low and act shutdown */
46547 @@ -597,6 +816,7 @@ static int inno_dsidphy_probe(struct platform_device *pdev)
52177 + * Generate a bitmask for setting a value (v) with a write mask bit in hiword
52180 +#define WRITE_MASK_VAL(h, l, v) \
52181 + (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
56140 +static int reg_debug_consumers_show(struct seq_file *m, void *v)
57105 + REGULATOR_LINEAR_RANGE(712500, 0, 59, 12500), /* 0.7125v - 1.45v */
57106 + REGULATOR_LINEAR_RANGE(1800000, 60, 62, 200000),/* 1.8v - 2.2v */
57107 + REGULATOR_LINEAR_RANGE(2300000, 63, 63, 0), /* 2.3v - 2.3v */
57111 + REGULATOR_LINEAR_RANGE(800000, 0, 26, 100000), /* 0.8v - 3.4v */
57112 + REGULATOR_LINEAR_RANGE(3500000, 27, 31, 0), /* 3.5v */
57121 + REGULATOR_LINEAR_RANGE(712500, 0, 59, 12500), /* 0.7125v - 1.45v */
57122 + REGULATOR_LINEAR_RANGE(1800000, 60, 62, 200000),/* 1.8v - 2.2v */
57123 + REGULATOR_LINEAR_RANGE(2300000, 63, 63, 0), /* 2.3v - 2.3v */
57127 + REGULATOR_LINEAR_RANGE(800000, 0, 26, 100000), /* 0.8v - 3.4 */
57128 + REGULATOR_LINEAR_RANGE(3500000, 27, 31, 0), /* 3.5v */