Lines Matching full:intel

40 -  VK_ANDROID_external_memory_android_hardware_buffer on Intel
41 -  Fixed and re-exposed VK_EXT_pci_bus_info on Intel and RADV
42 -  VK_EXT_scalar_block_layout on Intel and RADV
43 -  VK_KHR_depth_stencil_resolve on Intel
44 -  VK_KHR_draw_indirect_count on Intel
45 -  VK_EXT_conditional_rendering on Intel
222    - totem assert failure: totem: src/intel/genxml/gen9_pack.h:72:
312 -  intel/tools: avoid 'unused variable' warnings
316 -  intel/tools: make sure the binary file is properly read
318 -  intel/batch-decoder: fix vertex buffer size calculation for gen<8
319 -  intel/batch-decoder: fix a vb end address calculation
329 -  intel/icl: Set way_size_per_bank to 4
422 -  src/intel: use new hash table and set creation helpers
550 -  Revert "intel/compiler: More peephole_select for pre-Gen6"
553 -  Revert "intel/compiler: More peephole select"
741 -  nir: Pull some of intel's image load/store format conversion to
743 -  intel: Simplify the half-float packing in image load/store lowering.
746 -  Revert "intel: Simplify the half-float packing in image load/store
748 -  nir: Move intel's half-float image store lowering to to nir_format.h.
1004 -  intel/fs: Prevent emission of IR instructions not aligned to their
1006 -  intel/fs: Handle source modifiers in lower_integer_multiplication().
1007 -  intel/fs: Implement quad swizzles on ICL+.
1008 -  intel/fs: Fix bug in lower_simd_width while splitting an instruction
1010 -  intel/eu/gen7: Fix brw_MOV() with DF destination and strided source.
1011 -  intel/fs: Respect CHV/BXT regioning restrictions in copy propagation
1013 -  intel/fs: Constify fs_inst::can_do_source_mods().
1014 -  intel/fs: Introduce regioning lowering pass.
1015 -  intel/fs: Remove existing lower_conversions pass.
1016 -  intel/fs: Remove nasty open-coded CHV/BXT 64-bit workarounds.
1017 -  intel/fs: Remove FS_OPCODE_UNPACK_HALF_2x16_SPLIT opcodes.
1018 -  intel/fs: Promote execution type to 32-bit when any half-float
1020 -  intel/fs: Exclude control sources from execution type and region
1022 -  intel/fs: Implement extended strides greater than 4 for IR source
1104 -  intel/compiler: fix node interference of simd16 instructions
1108 -  intel/compiler: fix indentation style in opt_algebraic()
1109 -  intel/compiler: fix register allocation in opt_peephole_sel
1110 -  intel/compiler: do not copy-propagate strided regions to ddx/ddy
1112 -  intel/compiler: move nir_lower_bool_to_int32 before
1153 -  intel/compiler: More peephole select
1156 -  intel/compiler: More peephole_select for pre-Gen6
1162 -  intel/fs: nir_op_extract_i8 extracts a byte, not a word
1163 -  intel/fs: Fix extract_u8 of an odd byte from a 64-bit integer
1224 -  intel/fs,vec4: Clean up a repeated pattern with SSBOs
1225 -  intel/fs: Use the new nir_src_is_const and friends
1227 -  intel/vec4: Use the new nir_src_is_const and friends
1228 -  intel/analyze_ubo_ranges: Use nir_src_is_const and friends
1230 -  intel/fs: Add an assert to optimize_frontfacing_ternary
1239 -  intel/compiler: Lower SSBO and shared loads/stores in NIR
1240 -  intel,nir: Move gl_LocalInvocationID lowering to
1242 -  intel/fs,vec4: Fix a compiler warning
1259 -  intel/ir: Don't allow allocating zero registers
1264 -  intel/fs: Support min_lod parameters on texture instructions
1267 -  intel/blorp: Assert that we don't re-layout a compressed surface
1304 -  intel/blorp: Be more conservative about copying clear colors
1350 -  intel/peephole_ffma: Fix swizzle propagation
1353 -  intel/nir: Call nir_opt_deref in brw_nir_optimize
1356 -  intel/blorp: Add two more filter modes
1362 -  intel/eu: Stop overriding exec sizes in send_indirect_message
1363 -  intel/fs: Don't touch accumulator destination while applying
1394 -  intel/fs: Get rid of fs_inst::equals
1395 -  intel/defines: Explicitly cast to uint32_t in SET_FIELD and SET_BITS
1396 -  intel/fs: Handle IMAGE_SIZE in size_read() and is_send_from_grf()
1397 -  intel/fs: Take an explicit exec size in brw_surface_payload_size()
1398 -  intel/eu: Add has_simd4x2 bools to surface_write functions
1399 -  intel/eu: Rework surface descriptor helpers
1400 -  intel/fs: Add a generic SEND opcode
1401 -  intel/fs: Use SHADER_OPCODE_SEND for surface messages
1402 -  intel/fs: Use a logical opcode for IMAGE_SIZE
1403 -  intel/fs: Use SHADER_OPCODE_SEND for texturing on gen7+
1404 -  intel/fs: Use SHADER_OPCODE_SEND for varying UBO pulls on gen7+
1405 -  intel/eu: Use GET_BITS in brw_inst_set_send_ex_desc
1406 -  intel/eu/validate: SEND restrictions also apply to SENDC
1407 -  intel/eu: Add more message descriptor helpers
1408 -  intel/disasm: Rework SEND decoding to use descriptors
1409 -  intel/inst: Fix the ia16_addr_imm helpers
1410 -  intel/inst: Indent some code
1411 -  intel/eu: Add support for the SENDS[C] messages
1412 -  intel/disasm: Properly disassemble split sends
1413 -  intel/fs: Support SENDS in SHADER_OPCODE_SEND
1414 -  intel/fs: Add interference between SENDS sources
1415 -  intel/fs: Use split sends for surface writes on gen9+
1416 -  intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 mode
1419 -  intel/fs: Bail in optimize_extract_to_float if we have modifiers
1430 -  intel,nir: Lower TXD with min_lod when the sampler index is not < 16
1435 -  intel/nir: Vectorize all IO
1581 -  intel: Use a URB start offset of 0 for disabled stages.
1595 -  intel/compiler: Use nir's info when checking uses_streams.
1596 -  intel/blorp: Expand blorp_address::offset to be 64 bits.
1656 -  intel/dump_gpu: add missing gdb option
1657 -  intel/sanitize_gpu: add help/gdb options to wrapper
1658 -  intel/sanitize_gpu: deal with non page multiple buffer sizes
1659 -  intel/sanitize_gpu: add debug message on mmap fail
1660 -  intel/decoders: fix instruction base address parsing
1663 -  intel/dump_gpu: move output option together
1664 -  intel/dump_gpu: add platform option
1665 -  intel/aub_read: remove useless breaks
1677 -  intel/decoders: read ring buffer length
1678 -  intel/aubinator: fix ring buffer pointer
1679 -  intel/aub_viewer: fix dynamic state printing
1680 -  intel/aub_viewer: Print blend states properly
1684 -  intel/aub_viewer: fix shader get_bo
1685 -  intel/aub_viewer: fixup 0x address prefix
1686 -  intel/aub_viewer: print address of missing shader
1687 -  intel/aub_viewer: fix shader view
1688 -  intel/aub_viewer: fold binding/sampler table items
1689 -  intel/aub_viewer: highlight true booleans
1691 -  intel/blorp: emit VF caching workaround before 3DSTATE_VERTEX_BUFFERS
1699 -  intel/genxml: add missing MI_PREDICATE compare operations
1701 -  intel: fix urb size for CFL GT1
1702 -  intel/compiler: use correct swizzle for replacement
1891 -  intel/compiler: Lower 64-bit MOV/SEL operations
1892 -  intel/compiler: Split 64-bit MOV-indirects if needed
1893 -  intel/compiler: Avoid false positive assertions
1894 -  intel/compiler: Rearrange code to avoid future problems
1895 -  intel/compiler: Prevent warnings in the following patch
1896 -  intel/compiler: Expand size of the 'nr' field
1897 -  intel/compiler: Heap-allocate temporary storage
1902 -  intel/compiler: Reset default flag register in
1907 -  intel/compiler: Add a file-level description of brw_eu_validate.c
1910 -  intel/compiler: Avoid propagating inequality cmods if types are
1912 -  intel/compiler/test: Add unit test for mismatched signedness
2031 -  intel/genxml: Add register for object preemption.
2183 -  intel: Add more PCI Device IDs for Coffee Lake and Ice Lake.
2198 -  intel/compiler: Disassemble GEN6_SFID_DATAPORT_SAMPLER_CACHE as
2200 -  intel/compiler: Set swizzle to BRW_SWIZZLE_XXXX for scalar region
2201 -  intel/compiler: Always print flag subregister number
2361 -  intel/isl: move tiled_memcpy static libs from i965 to isl
2461 -  intel/decoder: Engine parameter for instructions
2462 -  intel/decoder: tools: gen_engine to drm_i915_gem_engine_class
2463 -  intel/decoder: tools: Use engine for decoding batch instructions
2464 -  intel/genxml: Add engine definition to render engine instructions
2466 -  intel/genxml: Add engine definition to render engine instructions
2468 -  intel/genxml: Add engine definition to render engine instructions
2470 -  intel/genxml: Add engine definition to render engine instructions
2472 -  intel/genxml: Add engine definition to render engine instructions
2474 -  intel/genxml: Add engine definition to render engine instructions
2476 -  intel/genxml: Add engine definition to render engine instructions
2478 -  intel/genxml: Add engine definition to render engine instructions
2480 -  intel/genxml: Add engine definition to render engine instructions
2482 -  intel/genxml: Add engine definition to render engine instructions
2484 -  intel/aubinator_error_decode: Get rid of warning for missing switch