Lines Matching full:intel
36 - VK_KHR_shader_clock on Intel, RADV.
37 - VK_KHR_shader_float_controls on Intel, RADV.
38 - VK_KHR_spirv_1_4 on Intel, RADV.
40 - VK_KHR_vulkan_memory_model on Intel.
41 - VK_EXT_shader_subgroup_ballot on Intel.
42 - VK_EXT_shader_subgroup_vote on Intel.
44 - VK_INTEL_performance_query on Intel.
47 - Initial Intel gen12 (Tigerlake) support on anvil and iris
178 - intel/common: include unistd.h for ioctl() prototype on Solaris
463 - intel/gen12: Add L3 configurations
464 - intel: Add few Ice Lake brand strings
466 - intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WM
467 - intel/isl/icl: Use halign 8 instead of 4 hw workaround
638 - intel/compiler: Silence maybe-uninitialized warning in GCC 9.1.1
641 - intel/decoders: Avoid uninitialized variable warnings
665 - intel/fs: Add Fall-through comment
680 - docs: Update recently enabled VK extensions on Intel
681 - intel: Add INTEL_DEBUG=nofc for disabling fast clears
687 - intel/fs/gen12: Add tests for scoreboard pass
690 - intel/fs: Implement scoped_memory_barrier
721 - etnaviv: output the same shader-db format as freedreno, v3d and intel
849 - intel/compiler: Fix C++ one definition rule violations
1509 - intel/fs: Teach fs_inst::is_send_from_grf() about some missing
1511 - intel/fs: Define is_payload() method of the IR instruction class.
1512 - intel/fs: Define is_send() convenience IR helper.
1513 - intel/fs: Fix constness of implied_mrf_writes() argument.
1514 - intel/eu: Split brw_inst ex_desc accessors for SEND(C) vs. SENDS(C).
1515 - intel/eu: Fix up various type conversions in brw_eu.c that are
1517 - intel/eu: Rework opcode description tables to allow efficient look-up
1519 - intel/eu: Encode and decode native instruction opcodes from/to IR
1521 - intel/ir: Drop hard-coded correspondence between IR and HW opcodes.
1522 - intel/ir: Represent physical and logical subsets of the CFG.
1523 - intel/ir: Add helper function to push block onto CFG analysis stack.
1524 - intel/ir: Represent logical edge of BREAK instruction.
1525 - intel/ir: Represent physical edge of ELSE instruction.
1526 - intel/ir: Represent physical edge of unconditional CONTINUE
1528 - intel/eu/gen12: Extend brw_inst.h macros for Gen12 support.
1529 - intel/eu/gen12: Add sanity-check asserts to brw_inst_bits() and
1531 - intel/eu/gen12: Implement basic instruction binary encoding.
1532 - intel/eu/gen12: Implement three-source instruction binary encoding.
1533 - intel/eu/gen12: Implement control flow instruction binary encoding.
1534 - intel/eu/gen12: Implement SEND instruction binary encoding.
1535 - intel/eu/gen12: Implement indirect region binary encoding.
1536 - intel/eu/gen12: Implement compact instruction binary encoding.
1537 - intel/eu/gen12: Implement datatype binary encoding.
1538 - intel/eu/gen11+: Mark dot product opcodes as unsupported on
1540 - intel/eu/gen12: Add Gen12 opcode descriptions to the table.
1541 - intel/eu/gen12: Fix codegen of immediate source regions.
1542 - intel/eu/gen12: Codegen three-source instruction source and
1544 - intel/eu/gen12: Codegen control flow instructions correctly.
1545 - intel/eu/gen12: Codegen pathological SEND source and destination
1547 - intel/eu/gen12: Codegen SEND descriptor regions correctly.
1548 - intel/eu/gen12: Use SEND instruction for split sends.
1549 - intel/eu/gen12: Don't set DD control, it's gone.
1550 - intel/eu/gen12: Don't set thread control, it's gone.
1551 - intel/ir/gen12: Add SYNC hardware instruction.
1552 - intel/fs/gen12: Add codegen support for the SYNC instruction.
1553 - intel/eu/gen12: Add auxiliary type to represent SWSB information
1555 - intel/eu/gen12: Add tracking of default SWSB state to the current
1557 - intel/eu/gen12: Set SWSB annotations in hand-crafted assembly.
1558 - intel/fs/gen12: Add scheduling information to the IR.
1559 - intel/fs/gen12: Introduce software scoreboard lowering pass.
1560 - intel/fs/gen12: Demodernize software scoreboard lowering pass.
1561 - intel/disasm/gen12: Disassemble software scoreboard information.
1562 - intel/disasm/gen12: Fix disassembly of some common instruction
1564 - intel/disasm/gen12: Disassemble three-source instruction source and
1566 - intel/disasm/gen12: Disassemble Gen12 SYNC instruction.
1567 - intel/disasm/gen12: Disassemble Gen12 SEND instructions.
1568 - intel/disasm: Don't disassemble saturate control on SEND
1570 - intel/disasm: Disassemble register file of split SEND sources.
1571 - intel/fs/gen12: Don't support source mods for 32x16 integer multiply.
1572 - intel/eu/validate/gen12: Implement integer multiply restrictions in
1574 - intel/eu/validate/gen12: Fix validation of SYNC instruction.
1575 - intel/eu/validate/gen12: Validation fixes for SEND instruction.
1576 - intel/ir/gen12: Update assert in brw_stage_has_packed_dispatch().
1577 - intel/eu: Don't set notify descriptor field of gateway barrier
1579 - intel/fs/gen12: Fix barrier codegen.
1580 - intel/fs/gen11+: Fix CS_OPCODE_CS_TERMINATE codegen.
1671 - intel/compiler: Request bitfield_reverse lowering on pre-Gen7
1695 - intel/vec4: Don't try both sources as immediates for DPH
1696 - intel/compiler: Report the number of non-spill/fill SEND messages on
1700 - intel/fs: Disable conditional discard optimization on Gen4 and Gen5
1701 - intel/compiler: Fix 'comparison is always true' warning
1754 - intel/nir: Add a helper for getting BRW_AOP from an intrinsic
1756 - intel/fs: Drop the gl_program from fs_visitor
1757 - intel/fs: Fix FB write inst groups
1758 - Revert "intel/fs: Move the scalar-region conversion to the
1761 - intel/tools: Decode 3DSTATE_BINDING_TABLE_POINTERS on SNB
1762 - intel/tools: Decode PS kernels on SNB
1764 - intel/blorp: Expose surf_retile_w_to_y internally
1765 - intel/blorp: Expose surf_fake_interleaved_msaa internally
1766 - intel/blorp: Use wide formats for nicely aligned stencil clears
1773 - intel/fs: Handle UNDEF in split_virtual_grfs
1778 - intel/fs: Allow UB, B, and HF types in brw_nir_reduction_op_identity
1779 - intel/fs: Allow CLUSTER_BROADCAST to do type conversion
1780 - intel/fs: Do 8-bit subgroup scan operations in 16 bits
1786 - intel/fs: Fix fs_inst::flags_read for ANY/ALL predicates
1788 - intel/eu/validate/gen12: Don't blow up on indirect src0.
1789 - intel/fs/gen12: Implement gl_FrontFacing on gen12+.
1790 - intel/genxml: Remove W-tiling on gen12
1791 - intel/isl: Select Y-tiling for stencil on gen12
1792 - intel/isl: Add isl_aux_usage_has_ccs
1795 - intel/blorp: Use surf instead of aux_surf for image dimensions
1796 - intel/isl: Add new aux modes available on gen12
1797 - intel/isl/fill_state: Separate aux_mode handling from aux_surf
1798 - intel/isl: Update surf_fill_state for gen12
1799 - intel/isl: Support HIZ_CCS in emit_depth_stencil_hiz
1802 - intel/vec4: Set brw_stage_prog_data::has_ubo_pull
1937 - intel/genxml: Handle field names with different spacing/hyphen
1938 - intel/genxml/gen11: Add spaces in EnableUnormPathInColorPipe
1939 - intel/genxml: Run sort_xml.sh to tidy gen9.xml and gen11.xml
1940 - intel/genxml: Add gen12.xml as a copy of gen11.xml
1941 - intel/genxml: Build gen12 genxml
1942 - intel/isl: Build gen12 using gen11 code paths
1943 - intel/compiler: Disable compaction on gen12 for now
1944 - intel/l3: Don't assert on gen12 (use gen11 config temporarily)
1951 - intel/ir: Lower fpow on Gen12.
1952 - intel/genxml,isl: Add gen12 render surface state changes
1953 - intel/genxml,isl: Add gen12 depth buffer changes
1954 - intel/genxml,isl: Add gen12 stencil buffer changes
1955 - intel/isl: Add gen12 depth/stencil surface alignments
1957 - intel/isl: Add R10G10B10_FLOAT_A2_UNORM format
1959 - intel/common: Add interface to allocate device buffers
1961 - intel/common: Add surface to aux map translation table support
1970 - intel: Update alignment restrictions for HiZ surfaces.
1972 - intel/genxml: Add gen12 tile cache flush bit
1973 - intel/dev: Add preliminary device info for Tigerlake
1974 - intel/eu/validate/gen12: Add TGL to eu_validate tests.
2056 - intel/compiler: Fix src0/desc setter ordering
2057 - intel/compiler: Handle bits 15:12 in
2059 - intel/compiler: Refactor FB write message control setup into a
2061 - intel/compiler: Use generic SEND for Gen7+ FB writes
2062 - intel/compiler: Use new Gen11 headerless RT writes for MRT cases
2073 - intel: Stop redirecting state cache to command streamer cache section
2088 - intel/compiler: Set "Null Render Target" ex_desc bit on Gen11
2094 - intel/compiler: Record whether any pull constant loads occur
2102 - intel/genxml: Stop manually scrubbing 'α' -> "alpha"
2104 - Revert "intel/gen11+: Enable Hardware filtering of Semi-Pipelined
2106 - intel: Increase Gen11 compute shader scratch IDs to 64.
2122 - intel/fs/gen12: Use TCS 8_PATCH mode.
2127 - intel/compiler: Report the number of non-spill/fill SEND messages
2133 - drirc: Set vs_position_always_invariant for Shadow of Mordor on Intel
2246 - intel: update product names for WHL
2253 - intel: use proper label for Comet Lake skus
2254 - intel: Add new Comet Lake PCI-ids
2256 - intel: fix topology query
2257 - intel/error2aub: add support for platforms without PPGTT
2258 - intel: fix subslice computation from topology data
2259 - intel/isl: Set null surface format to R32_UINT
2260 - intel/isl: set surface array appropriately
2261 - intel/isl: set vertical surface alignment on null surfaces
2266 - intel/perf: add mdapi maker helper
2267 - intel/perf: expose some utility functions
2268 - intel/perf: extract register configuration
2269 - intel/perf: move registers to their own header
2271 - intel/perf: add support for querying kernel loaded configurations
2272 - intel/genxml: add generic perf counters registers
2273 - intel/genxml: add RPSTAT register for core frequency
2274 - intel/perf: add mdapi writes for register perf counters
2276 - docs: Add new Intel extension
2277 - intel/dev: store whether the device uses an aux map tables on devinfo
2279 - intel/perf: update ICL configurations
2280 - intel/dump_gpu: handle context create extended ioctl
2281 - intel/dev: set default num_eu_per_subslice on gen12
2289 - intel/perf: fix invalid hw_id in query results
2290 - intel/perf: set read buffer len to 0 to identify empty buffer
2291 - intel/perf: take into account that reports read can be fairly old
2292 - intel/perf: simplify the processing of OA reports
2293 - intel/perf: fix improper pointer access
2527 - intel/compiler: Remove unreachable() from brw_reg_type.c
2528 - intel/compiler: Restructure instruction compaction in preparation for
2530 - intel/compiler: Inline get_src_index()
2531 - intel/compiler: Make separate src0/src1 index tables
2532 - intel/compiler: Add instruction compaction support on Gen12
2548 - intel/compiler: avoid truncating int64_t to int
2601 - intel/compiler: Don't left-shift by >= the number of bits of the type
2602 - intel/compiler: Cast to target type before shifting left
2603 - intel/fs: Check for NULL key in fs_visitor constructor
2627 - intel/blorp: Halve the Gen12 fast-clear/resolve rectangle
2628 - intel/blorp: Don't assert aux slices match main slices
2635 - intel: Enable CCS_E for some formats on Gen12
2636 - intel/blorp: Disable depth testing for slow depth clears
2638 - intel: Use RENDER_SURFACE_STATE::DepthStencilResource
2639 - intel: Use 3DSTATE_DEPTH_BUFFER::ControlSurfaceEnable
2640 - intel: Enable CCS_E for R24_UNORM_X8_TYPELESS on TGL+
2642 - intel: Support HIZ_CCS in isl_surf_get_ccs_surf
2643 - intel/blorp: Assert against HiZ in surface states
2644 - intel/blorp: Treat HIZ_CCS like HiZ
2650 - intel: Refactor blorp_can_hiz_clear_depth()
2651 - intel/blorp: Satisfy HIZ_CCS fast-clear alignments
2653 - intel: Fix and use HIZ_CCS write through mode
2654 - intel/blorp: Satisfy clear color rules for HIZ_CCS
2689 - intel/fs: grab fail_msg from v32 instead of v16 when v32->run_cs
2691 - intel/fs: make scan/reduce work with SIMD32 when it fits 2 registers
2692 - intel/fs: roll the loop with the <0,1,0> additions in emit_scan()
2693 - intel/fs: the maximum supported stride width is 16
2694 - intel/fs: fix SHADER_OPCODE_CLUSTER_BROADCAST for SIMD32
2695 - intel/fs: don't forget the stride at generate_shuffle
2696 - intel/compiler: remove the operand restriction for src1 on GLK
2697 - intel/compiler: fix nir_op_{i,u}*32 on ICL
2774 - intel/tools: Fix aubinator usage of rb_tree.
2776 - intel/tools: Factor out GGTT allocation.
2777 - intel/tools: Use common code for GGTT address allocation.
2778 - intel/tools: Add basic aub_context code and helpers.
2779 - intel/tools: Support multiple contexts in intel_dump_gpu.
2780 - intel/blorp/gen12: Set FWCC when storing the clear color.
2964 - intel/eu/gen12: Implement immediate 64 bit constant encoding.
2966 - intel/compiler: Remove emit_alpha_to_coverage workaround from backend
2967 - intel: Add missing entry for brw_nir_lower_alpha_to_coverage in
2969 - intel/compiler: Add Immediate support for 3 source instruction
2970 - intel/compiler: Set bits according to source file
2971 - intel/compiler: Don't move immediate in register
2972 - intel/compiler: Refactor disassembly of sources in 3src instruction
2973 - intel/isl: Don't reconfigure aux surfaces for MCS
2976 - intel/blorp: Use isl_aux_usage_has_mcs instead of comparing
2978 - intel/isl: Support lossless compression with multisamples
2981 - intel/blorp: Assign correct view while clearing depth stencil
2982 - intel/blorp: Add helper function for stencil buffer resolve
2983 - intel: Track stencil aux usage on Gen12+
2984 - intel/blorp: Set stencil resolve enable bit
2991 - intel/isl: Allow stencil buffer to support compression on Gen12+
3015 - intel/nir: do not apply the fsin and fcos trig workarounds for consts
3029 - docs/relnotes: add support for VK_KHR_shader_float_controls on Intel
3179 - intel/dri: finish proper glthread
3193 - intel/genxml: generate pack files for gen12 on android builds
3194 - intel/isl: build android libmesa_isl for gen12