Lines Matching +full:vc4 +full:- +full:rules
27 # The Intrinsic class corresponds one-to-one with nir_intrinsic_info
49 - name: the intrinsic name
50 - src_components: list of the number of components per src, 0 means
53 - dest_components: number of destination components, -1 means no
56 - indices: list of constant indicies
57 - flags: list of semantic flags
58 - sysval: is this a system-value intrinsic
59 - bit_sizes: allowed dest bit_sizes or the source it must match
90 self.bit_size_src = bit_sizes[1] if isinstance(bit_sizes, tuple) else -1
118 def intrinsic(name, src_comp=[], dest_comp=-1, indices=[],
135 # The stream-id for GS emit_vertex/end_primitive intrinsics.
138 # The clip-plane id for load_user_clip_plane intrinsic.
181 # Non-zero if we are accessing an array image
188 # not set at the intrinsic if the NIR was created from SPIR-V.
204 # (X - align_offset) % align_mul == 0
283 intrinsic("load_deref", dest_comp=0, src_comp=[-1],
285 intrinsic("store_deref", src_comp=[-1, 0], indices=[WRITE_MASK, ACCESS])
286 intrinsic("copy_deref", src_comp=[-1, -1], indices=[DST_ACCESS, SRC_ACCESS])
287 intrinsic("memcpy_deref", src_comp=[-1, -1, 1], indices=[DST_ACCESS, SRC_ACCESS])
305 intrinsic("deref_buffer_array_length", src_comp=[-1], dest_comp=1,
310 intrinsic("get_ssbo_size", src_comp=[-1], dest_comp=1, bit_sizes=[32],
312 intrinsic("get_ubo_size", src_comp=[-1], dest_comp=1,
315 # Intrinsics which provide a run-time mode-check. Unlike the compile-time
317 intrinsic("deref_mode_is", src_comp=[-1], dest_comp=1,
319 intrinsic("addr_mode_is", src_comp=[-1], dest_comp=1,
344 # SpvOpTerminateInvocation from SPIR-V. Essentially a discard "for real".
347 # A workgroup-level control barrier. Any thread which hits this barrier will
358 # Control/Memory barrier with explicit scope. Follows the semantics of SPIR-V
387 # Additional SPIR-V ballot intrinsics
389 # These correspond to the SPIR-V opcodes
422 # Ballot ALU operations from SPIR-V.
434 # Shuffle operations from SPIR-V.
440 # Quad operations from SPIR-V.
469 # emit_vertex implements GLSL's EmitStreamVertex() built-in. It takes a single
472 # end_primitive implements GLSL's EndPrimitive() built-in.
491 # Rules:
492 # - This is a terminating instruction.
493 # - May only occur in workgroup-uniform control flow.
494 # - Dispatch sizes may be divergent (in which case the values
497 # - BASE: address of the task_payload variable used.
498 # - RANGE: size of the task_payload variable used.
517 intrinsic("trace_ray", src_comp=[-1, 1, 1, 1, 1, 1, 3, 1, 3, 1, -1])
521 intrinsic("accept_ray_intersection") # Not in SPIR-V; useful for lowering
524 intrinsic("execute_callable", src_comp=[1, -1])
536 intrinsic("rq_initialize", src_comp=[-1, -1, 1, 1, 3, 1, 3, 1])
538 intrinsic("rq_terminate", src_comp=[-1])
540 intrinsic("rq_proceed", src_comp=[-1], dest_comp=1)
542 intrinsic("rq_generate_intersection", src_comp=[-1, 1])
544 intrinsic("rq_confirm_intersection", src_comp=[-1])
546 intrinsic("rq_load", src_comp=[-1, 1], dest_comp=0, indices=[BASE,COLUMN])
561 intrinsic("rt_execute_callable", src_comp=[1, -1], indices=[CALL_IDX,STACK_SIZE])
565 intrinsic("rt_trace_ray", src_comp=[-1, 1, 1, 1, 1, 1, 3, 1, 3, 1, -1],
576 # The register offset may be non-constant but must by dynamically uniform
581 intrinsic(name + "_deref", src_comp=[-1], dest_comp=1, flags=flags)
585 intrinsic(name + "_deref", src_comp=[-1, 1], dest_comp=1)
589 intrinsic(name + "_deref", src_comp=[-1, 1, 1], dest_comp=1)
617 # All image intrinsics take a four-coordinate vector and a sample index as
620 # in use are undefined. Image store takes an additional four-component
625 intrinsic("image_deref_" + name, src_comp=[-1] + src_comp,
629 intrinsic("bindless_image_" + name, src_comp=[-1] + src_comp,
652 # CL-specific format queries
680 intrinsic("load_vulkan_descriptor", src_comp=[-1], dest_comp=0,
700 # 0: The SSBO buffer index (dynamically uniform in GLSL, possibly non-uniform
727 # has the low 32-bit and component Y has the high 32-bit.
733 intrinsic("deref_atomic_" + name, src_comp=[-1, 1], dest_comp=1, indices=[ACCESS])
734 intrinsic("ssbo_atomic_" + name, src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS])
744 intrinsic("deref_atomic_" + name, src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS])
745 intrinsic("ssbo_atomic_" + name, src_comp=[-1, 1, 1, 1], dest_comp=1, indices=[ACCESS])
787 # sample_id_no_per_sample is like sample_id but does not imply per-
791 # sample_pos_or_center is like sample_pos but does not imply per-sample
792 # shading. When per-sample dispatch is not enabled, it returns (0.5, 0.5).
806 # non-zero_base indicates the base is included
866 # Driver-specific viewport scale/offset parameters.
868 # VC4 and V3D need to emit a scaled version of the position in the vertex
897 # shader prolog to handle two-sided color without recompiles and therefore
908 # The first four are for the simple cases: pixel, centroid, per-sample
994 load("ubo", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET, RANGE_BASE, RANGE], flags=[CAN_ELIMINATE, CA…
996 load("ubo_vec4", [-1, 1], [ACCESS, BASE, COMPONENT], flags=[CAN_ELIMINATE, CAN_REORDER])
1007 load("ssbo", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE])
1058 store("ssbo", [-1, 1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET])
1100 # IR3-specific version of most SSBO intrinsics. The only different
1102 # the dword-offset, which is needed by the backend code apart from
1103 # the byte-offset already provided by NIR in one of the sources.
1107 # dword-offset always in the last source.
1142 # IR3-specific intrinsics for tessellation control shaders. cond_end_ir3 end
1150 # IR3-specific load/store intrinsics. These access a buffer used to pass data
1151 # between geometry stages - perhaps it's explicit access to the vertex cache.
1158 # IR3-specific load/store global intrinsics. They take a 64-bit base address
1159 # and a 32-bit offset. The hardware will add the base and the offset, which
1160 # saves us from doing 64-bit math on the base address.
1169 # IR3-specific bindless handle specifier. Similar to vulkan_resource_index, but
1175 # IR3-specific intrinsics for shader preamble. These are meant to be used like
1192 # IR3-specific intrinsic for stc. Should be used in the shader preamble.
1195 # IR3-specific intrinsic for ldc.k. Copies UBO to constant file.
1215 # src[] = { index, 16-byte-based-offset }
1249 # an sRGB->linear conversion, but linear values should be written to
1250 # raw_output_pan and the hardware handles linear->sRGB.
1261 # Loads the sample position array on Bifrost, in a packed Arm-specific format
1275 # load as many components as needed giving per-component addresses
1288 # src[] = { address, unsigned 32-bit offset }.
1290 # src[] = { value, address, unsigned 32-bit offset }.
1302 # Descriptor where ES outputs are stored for GS to read on GFX6-8
1322 # Vertex offsets used for GS per-vertex inputs
1339 # For NGG passthrough mode only. Pre-packed argument for export_primitive_amd.
1372 # 2. BVH node(64-bit pointer as 2x32 ...)
1397 # src[] = { 64-bit base address, 32-bit offset }.
1408 # Vertex stride in LS-HS buffer
1414 # V3D-specific instrinc for tile buffer color reads.
1423 # V3D-specific instrinc for per-sample tile buffer color writes.
1425 # The driver backend needs to identify per-sample color writes and emit
1432 # V3D-specific intrinsic to load the number of layers attached to
1439 # Intel-specific query for loading from the brw_image_param struct passed
1448 # Intrinsic to load a block of at least 32B of constant data from a 64-bit
1449 # global memory address. The memory address must be uniform and 32B-aligned.
1459 # Load a relocatable 32-bit value
1463 # 64-bit global address for a Vulkan descriptor set
1469 intrinsic("load_deref_block_intel", dest_comp=0, src_comp=[-1],
1471 intrinsic("store_deref_block_intel", src_comp=[-1, 0], indices=[WRITE_MASK, ACCESS])
1477 load("ssbo_block_intel", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE])
1486 store("ssbo_block_intel", [-1, 1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET])
1508 # Intel-specific ray-tracing intrinsic
1512 # System values used for ray-tracing on Intel