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Searched defs:And (Results 1 – 25 of 139) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DMIPatternMatch.h72 template <typename... Preds> struct And { struct
80 struct And<Pred, Preds...> : And<Preds...> { argument
/third_party/vixl/test/aarch32/
Dtest-assembler-aarch32.cc515 __ And(r3, r0, r1); in TEST() local
516 __ And(r4, r0, Operand(r1, LSL, 4)); in TEST() local
517 __ And(r5, r0, Operand(r1, LSR, 1)); in TEST() local
518 __ And(r6, r0, Operand(r1, ASR, 20)); in TEST() local
519 __ And(r7, r0, Operand(r1, ROR, 28)); in TEST() local
520 __ And(r8, r0, 0xff); in TEST() local
524 __ And(r9, r1, Operand(r1, RRX)); in TEST() local
528 __ And(r10, r1, Operand(r1, RRX)); in TEST() local
2948 __ And(r3, r3, 0xf0000000); in TEST() local
3035 __ And(r0, r0, r2); in TEST() local
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Dtest-simulator-cond-rd-rn-rm-ge-t32.cc473 __ And(saved_q_bit, saved_q_bit, QFlag); in TestHelper() local
485 __ And(saved_nzcv_bits, saved_nzcv_bits, NZCVFlag); in TestHelper() local
508 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper() local
516 __ And(q_bit, q_bit, QFlag); in TestHelper() local
524 __ And(ge_bits, ge_bits, GEFlags); in TestHelper() local
Dtest-simulator-cond-rd-rn-rm-q-a32.cc457 __ And(saved_q_bit, saved_q_bit, QFlag); in TestHelper() local
469 __ And(saved_nzcv_bits, saved_nzcv_bits, NZCVFlag); in TestHelper() local
492 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper() local
500 __ And(q_bit, q_bit, QFlag); in TestHelper() local
508 __ And(ge_bits, ge_bits, GEFlags); in TestHelper() local
Dtest-simulator-cond-rd-rn-rm-a32.cc1561 __ And(saved_q_bit, saved_q_bit, QFlag); in TestHelper() local
1573 __ And(saved_nzcv_bits, saved_nzcv_bits, NZCVFlag); in TestHelper() local
1596 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper() local
1604 __ And(q_bit, q_bit, QFlag); in TestHelper() local
1612 __ And(ge_bits, ge_bits, GEFlags); in TestHelper() local
Dtest-simulator-cond-rd-rn-rm-sel-t32.cc450 __ And(saved_q_bit, saved_q_bit, QFlag); in TestHelper() local
462 __ And(saved_nzcv_bits, saved_nzcv_bits, NZCVFlag); in TestHelper() local
485 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper() local
493 __ And(q_bit, q_bit, QFlag); in TestHelper() local
501 __ And(ge_bits, ge_bits, GEFlags); in TestHelper() local
Dtest-simulator-cond-rd-rn-rm-sel-a32.cc450 __ And(saved_q_bit, saved_q_bit, QFlag); in TestHelper() local
462 __ And(saved_nzcv_bits, saved_nzcv_bits, NZCVFlag); in TestHelper() local
485 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper() local
493 __ And(q_bit, q_bit, QFlag); in TestHelper() local
501 __ And(ge_bits, ge_bits, GEFlags); in TestHelper() local
Dtest-simulator-cond-rd-rn-rm-q-t32.cc457 __ And(saved_q_bit, saved_q_bit, QFlag); in TestHelper() local
469 __ And(saved_nzcv_bits, saved_nzcv_bits, NZCVFlag); in TestHelper() local
492 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper() local
500 __ And(q_bit, q_bit, QFlag); in TestHelper() local
508 __ And(ge_bits, ge_bits, GEFlags); in TestHelper() local
Dtest-simulator-cond-rd-rn-rm-t32.cc1559 __ And(saved_q_bit, saved_q_bit, QFlag); in TestHelper() local
1571 __ And(saved_nzcv_bits, saved_nzcv_bits, NZCVFlag); in TestHelper() local
1594 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper() local
1602 __ And(q_bit, q_bit, QFlag); in TestHelper() local
1610 __ And(ge_bits, ge_bits, GEFlags); in TestHelper() local
Dtest-simulator-cond-rd-rn-rm-ge-a32.cc473 __ And(saved_q_bit, saved_q_bit, QFlag); in TestHelper() local
485 __ And(saved_nzcv_bits, saved_nzcv_bits, NZCVFlag); in TestHelper() local
508 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper() local
516 __ And(q_bit, q_bit, QFlag); in TestHelper() local
524 __ And(ge_bits, ge_bits, GEFlags); in TestHelper() local
Dtest-simulator-cond-rdlow-operand-imm8-t32.cc1624 __ And(saved_q_bit, saved_q_bit, QFlag); in TestHelper() local
1639 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper() local
Dtest-simulator-cond-rd-operand-imm16-t32.cc472 __ And(saved_q_bit, saved_q_bit, QFlag); in TestHelper() local
487 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper() local
Dtest-simulator-cond-rd-operand-const-t32.cc634 __ And(saved_q_bit, saved_q_bit, QFlag); in TestHelper() local
649 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper() local
Dtest-simulator-cond-rd-operand-const-a32.cc519 __ And(saved_q_bit, saved_q_bit, QFlag); in TestHelper() local
534 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper() local
Dtest-simulator-cond-rd-rn-operand-const-a32.cc1154 __ And(saved_q_bit, saved_q_bit, QFlag); in TestHelper() local
1170 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper() local
Dtest-simulator-cond-rd-rn-a32.cc904 __ And(saved_q_bit, saved_q_bit, QFlag); in TestHelper() local
920 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper() local
Dtest-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc1007 __ And(saved_q_bit, saved_q_bit, QFlag); in TestHelper() local
1023 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper() local
Dtest-simulator-cond-rd-rn-operand-const-t32.cc1178 __ And(saved_q_bit, saved_q_bit, QFlag); in TestHelper() local
1194 __ And(nzcv_bits, nzcv_bits, NZCVFlag); in TestHelper() local
/third_party/vixl/examples/aarch64/
Dneon-matrix-multiply.cc68 __ And(x3, x0, x1); in GenerateNEONMatrixMultiply() local
69 __ And(x3, x3, x2); in GenerateNEONMatrixMultiply() local
Dgetting-started.cc42 __ And(x0, x0, x1); in GenerateDemoFunction() local
/third_party/vixl/examples/aarch32/
Dgetting-started.cc39 __ And(r0, r0, r1); in GenerateDemo() local
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSILowerControlFlow.cpp225 MachineInstr *And = in emitIf() local
311 MachineInstr *And = in emitElse() local
373 MachineInstr *And = nullptr, *Or = nullptr; in emitIfBreak() local
/third_party/vixl/benchmarks/aarch64/
Dbench-utils.cc219 __ And(PickR(size), PickR(size), Operand(PickR(size))); in GenerateOperandSequence() local
273 __ And(PickR(size), PickR(size), GetRandomBits(size)); in GenerateImmediateSequence() local
378 __ And(PickV().V16B(), PickV().V16B(), PickV().V16B()); in GenerateNEONSequence() local
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
DGuardUtils.cpp87 auto *And = dyn_cast<Instruction>(Cond); in parseWidenableBranch() local
/third_party/rust/crates/nom/src/
Dinternal.rs393 pub struct And<F, G> { struct
398 impl<'a, I, O1, O2, E, F: Parser<I, O1, E>, G: Parser<I, O2, E>> Parser<I, (O1, O2), E>
399 for And<F, G> argument

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