| /third_party/vixl/test/aarch32/ |
| D | test-assembler-aarch32.cc | 551 __ Ands(r0, r1, r1); in TEST() local
563 __ Ands(r0, r0, Operand(r1, LSL, 4)); in TEST() local
575 __ Ands(r0, r0, Operand(r1, LSR, 4)); in TEST() local
587 __ Ands(r0, r0, Operand(r1, ASR, 4)); in TEST() local
599 __ Ands(r0, r0, Operand(r1, ROR, 1)); in TEST() local
613 __ Ands(r2, r0, Operand(r1, RRX)); in TEST() local
628 __ Ands(r2, r0, Operand(r1, RRX)); in TEST() local
639 __ Ands(r0, r0, 0xf); in TEST() local
650 __ Ands(r0, r0, 0x80000000); in TEST() local
3281 __ Ands(r0, r0, 0); in TEST() local
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| D | code-generator-arm64.cc | 1137 __ Ands(i.OutputRegister(), i.InputOrZeroRegister64(0), in AssembleArchInstruction() local
1152 __ Ands(i.OutputRegister32(), i.InputOrZeroRegister32(0), in AssembleArchInstruction() local
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | macro-assembler-arm64-inl.h | 31 void TurboAssembler::Ands(const Register& rd, const Register& rn, in Ands() function
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| /third_party/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.cc | 809 void MacroAssembler::Ands(const Register& rd, in Emit() function in vixl::aarch64::MacroAssembler
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| D | macro-assembler-aarch64.h | 3658 void Ands(const PRegisterWithLaneSize& pd, in Ands() function
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| /third_party/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 688 __ Ands(w0, w1, Operand(w1)); in TEST() local
701 __ Ands(w0, w0, Operand(w1, LSR, 4)); in TEST() local
714 __ Ands(x0, x0, Operand(x1, ROR, 1)); in TEST() local
726 __ Ands(w0, w0, Operand(0xf)); in TEST() local
738 __ Ands(w0, w0, Operand(0x80000000)); in TEST() local
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| D | test-assembler-sve-aarch64.cc | 1085 __ Ands(p0.VnB(), p12.Zeroing(), p11.VnB(), p10.VnB()); in TEST_SVE() local
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| /third_party/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 1371 void Ands(Condition cond, Register rd, Register rn, const Operand& operand) { in Assembler() function
1385 void Ands(Register rd, Register rn, const Operand& operand) { in Assembler() function
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