1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * 4 * (C) COPYRIGHT 2019-2021 ARM Limited. All rights reserved. 5 * 6 * This program is free software and is provided to you under the terms of the 7 * GNU General Public License version 2 as published by the Free Software 8 * Foundation, and any use by you of this program is subject to the terms 9 * of such GNU license. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, you can access it online at 18 * http://www.gnu.org/licenses/gpl-2.0.html. 19 * 20 */ 21 22 #ifndef _UAPI_BASE_JM_KERNEL_H_ 23 #define _UAPI_BASE_JM_KERNEL_H_ 24 25 #include <linux/types.h> 26 27 /* Memory allocation, access/hint flags. 28 * 29 * See base_mem_alloc_flags. 30 */ 31 32 /* IN */ 33 /* Read access CPU side 34 */ 35 #define BASE_MEM_PROT_CPU_RD ((base_mem_alloc_flags)1 << 0) 36 37 /* Write access CPU side 38 */ 39 #define BASE_MEM_PROT_CPU_WR ((base_mem_alloc_flags)1 << 1) 40 41 /* Read access GPU side 42 */ 43 #define BASE_MEM_PROT_GPU_RD ((base_mem_alloc_flags)1 << 2) 44 45 /* Write access GPU side 46 */ 47 #define BASE_MEM_PROT_GPU_WR ((base_mem_alloc_flags)1 << 3) 48 49 /* Execute allowed on the GPU side 50 */ 51 #define BASE_MEM_PROT_GPU_EX ((base_mem_alloc_flags)1 << 4) 52 53 /* Will be permanently mapped in kernel space. 54 * Flag is only allowed on allocations originating from kbase. 55 */ 56 #define BASEP_MEM_PERMANENT_KERNEL_MAPPING ((base_mem_alloc_flags)1 << 5) 57 58 /* The allocation will completely reside within the same 4GB chunk in the GPU 59 * virtual space. 60 * Since this flag is primarily required only for the TLS memory which will 61 * not be used to contain executable code and also not used for Tiler heap, 62 * it can't be used along with BASE_MEM_PROT_GPU_EX and TILER_ALIGN_TOP flags. 63 */ 64 #define BASE_MEM_GPU_VA_SAME_4GB_PAGE ((base_mem_alloc_flags)1 << 6) 65 66 /* Userspace is not allowed to free this memory. 67 * Flag is only allowed on allocations originating from kbase. 68 */ 69 #define BASEP_MEM_NO_USER_FREE ((base_mem_alloc_flags)1 << 7) 70 71 #define BASE_MEM_RESERVED_BIT_8 ((base_mem_alloc_flags)1 << 8) 72 73 /* Grow backing store on GPU Page Fault 74 */ 75 #define BASE_MEM_GROW_ON_GPF ((base_mem_alloc_flags)1 << 9) 76 77 /* Page coherence Outer shareable, if available 78 */ 79 #define BASE_MEM_COHERENT_SYSTEM ((base_mem_alloc_flags)1 << 10) 80 81 /* Page coherence Inner shareable 82 */ 83 #define BASE_MEM_COHERENT_LOCAL ((base_mem_alloc_flags)1 << 11) 84 85 /* IN/OUT */ 86 /* Should be cached on the CPU, returned if actually cached 87 */ 88 #define BASE_MEM_CACHED_CPU ((base_mem_alloc_flags)1 << 12) 89 90 /* IN/OUT */ 91 /* Must have same VA on both the GPU and the CPU 92 */ 93 #define BASE_MEM_SAME_VA ((base_mem_alloc_flags)1 << 13) 94 95 /* OUT */ 96 /* Must call mmap to acquire a GPU address for the allocation 97 */ 98 #define BASE_MEM_NEED_MMAP ((base_mem_alloc_flags)1 << 14) 99 100 /* IN */ 101 /* Page coherence Outer shareable, required. 102 */ 103 #define BASE_MEM_COHERENT_SYSTEM_REQUIRED ((base_mem_alloc_flags)1 << 15) 104 105 /* Protected memory 106 */ 107 #define BASE_MEM_PROTECTED ((base_mem_alloc_flags)1 << 16) 108 109 /* Not needed physical memory 110 */ 111 #define BASE_MEM_DONT_NEED ((base_mem_alloc_flags)1 << 17) 112 113 /* Must use shared CPU/GPU zone (SAME_VA zone) but doesn't require the 114 * addresses to be the same 115 */ 116 #define BASE_MEM_IMPORT_SHARED ((base_mem_alloc_flags)1 << 18) 117 118 /** 119 * Bit 19 is reserved. 120 * 121 * Do not remove, use the next unreserved bit for new flags 122 */ 123 #define BASE_MEM_RESERVED_BIT_19 ((base_mem_alloc_flags)1 << 19) 124 125 /** 126 * Memory starting from the end of the initial commit is aligned to 'extension' 127 * pages, where 'extension' must be a power of 2 and no more than 128 * BASE_MEM_TILER_ALIGN_TOP_EXTENSION_MAX_PAGES 129 */ 130 #define BASE_MEM_TILER_ALIGN_TOP ((base_mem_alloc_flags)1 << 20) 131 132 /* Should be uncached on the GPU, will work only for GPUs using AARCH64 mmu 133 * mode. Some components within the GPU might only be able to access memory 134 * that is GPU cacheable. Refer to the specific GPU implementation for more 135 * details. The 3 shareability flags will be ignored for GPU uncached memory. 136 * If used while importing USER_BUFFER type memory, then the import will fail 137 * if the memory is not aligned to GPU and CPU cache line width. 138 */ 139 #define BASE_MEM_UNCACHED_GPU ((base_mem_alloc_flags)1 << 21) 140 141 /* 142 * Bits [22:25] for group_id (0~15). 143 * 144 * base_mem_group_id_set() should be used to pack a memory group ID into a 145 * base_mem_alloc_flags value instead of accessing the bits directly. 146 * base_mem_group_id_get() should be used to extract the memory group ID from 147 * a base_mem_alloc_flags value. 148 */ 149 #define BASEP_MEM_GROUP_ID_SHIFT 22 150 #define BASE_MEM_GROUP_ID_MASK \ 151 ((base_mem_alloc_flags)0xF << BASEP_MEM_GROUP_ID_SHIFT) 152 153 /* Must do CPU cache maintenance when imported memory is mapped/unmapped 154 * on GPU. Currently applicable to dma-buf type only. 155 */ 156 #define BASE_MEM_IMPORT_SYNC_ON_MAP_UNMAP ((base_mem_alloc_flags)1 << 26) 157 158 /* Use the GPU VA chosen by the kernel client */ 159 #define BASE_MEM_FLAG_MAP_FIXED ((base_mem_alloc_flags)1 << 27) 160 161 /* OUT */ 162 /* Kernel side cache sync ops required */ 163 #define BASE_MEM_KERNEL_SYNC ((base_mem_alloc_flags)1 << 28) 164 165 /* Force trimming of JIT allocations when creating a new allocation */ 166 #define BASEP_MEM_PERFORM_JIT_TRIM ((base_mem_alloc_flags)1 << 29) 167 168 /* Number of bits used as flags for base memory management 169 * 170 * Must be kept in sync with the base_mem_alloc_flags flags 171 */ 172 #define BASE_MEM_FLAGS_NR_BITS 30 173 174 /* A mask of all the flags which are only valid for allocations within kbase, 175 * and may not be passed from user space. 176 */ 177 #define BASEP_MEM_FLAGS_KERNEL_ONLY \ 178 (BASEP_MEM_PERMANENT_KERNEL_MAPPING | BASEP_MEM_NO_USER_FREE | \ 179 BASE_MEM_FLAG_MAP_FIXED | BASEP_MEM_PERFORM_JIT_TRIM) 180 181 /* A mask for all output bits, excluding IN/OUT bits. 182 */ 183 #define BASE_MEM_FLAGS_OUTPUT_MASK BASE_MEM_NEED_MMAP 184 185 /* A mask for all input bits, including IN/OUT bits. 186 */ 187 #define BASE_MEM_FLAGS_INPUT_MASK \ 188 (((1 << BASE_MEM_FLAGS_NR_BITS) - 1) & ~BASE_MEM_FLAGS_OUTPUT_MASK) 189 190 /* A mask of all currently reserved flags 191 */ 192 #define BASE_MEM_FLAGS_RESERVED \ 193 (BASE_MEM_RESERVED_BIT_8 | BASE_MEM_RESERVED_BIT_19) 194 195 #define BASEP_MEM_INVALID_HANDLE (0ul) 196 #define BASE_MEM_MMU_DUMP_HANDLE (1ul << LOCAL_PAGE_SHIFT) 197 #define BASE_MEM_TRACE_BUFFER_HANDLE (2ul << LOCAL_PAGE_SHIFT) 198 #define BASE_MEM_MAP_TRACKING_HANDLE (3ul << LOCAL_PAGE_SHIFT) 199 #define BASEP_MEM_WRITE_ALLOC_PAGES_HANDLE (4ul << LOCAL_PAGE_SHIFT) 200 /* reserved handles ..-47<<PAGE_SHIFT> for future special handles */ 201 #define BASE_MEM_COOKIE_BASE (64ul << LOCAL_PAGE_SHIFT) 202 #define BASE_MEM_FIRST_FREE_ADDRESS \ 203 ((BITS_PER_LONG << LOCAL_PAGE_SHIFT) + BASE_MEM_COOKIE_BASE) 204 205 /* Similar to BASE_MEM_TILER_ALIGN_TOP, memory starting from the end of the 206 * initial commit is aligned to 'extension' pages, where 'extension' must be a power 207 * of 2 and no more than BASE_MEM_TILER_ALIGN_TOP_EXTENSION_MAX_PAGES 208 */ 209 #define BASE_JIT_ALLOC_MEM_TILER_ALIGN_TOP (1 << 0) 210 211 /** 212 * If set, the heap info address points to a __u32 holding the used size in bytes; 213 * otherwise it points to a __u64 holding the lowest address of unused memory. 214 */ 215 #define BASE_JIT_ALLOC_HEAP_INFO_IS_SIZE (1 << 1) 216 217 /** 218 * Valid set of just-in-time memory allocation flags 219 * 220 * Note: BASE_JIT_ALLOC_HEAP_INFO_IS_SIZE cannot be set if heap_info_gpu_addr 221 * in %base_jit_alloc_info is 0 (atom with BASE_JIT_ALLOC_HEAP_INFO_IS_SIZE set 222 * and heap_info_gpu_addr being 0 will be rejected). 223 */ 224 #define BASE_JIT_ALLOC_VALID_FLAGS \ 225 (BASE_JIT_ALLOC_MEM_TILER_ALIGN_TOP | BASE_JIT_ALLOC_HEAP_INFO_IS_SIZE) 226 227 /** 228 * typedef base_context_create_flags - Flags to pass to ::base_context_init. 229 * 230 * Flags can be ORed together to enable multiple things. 231 * 232 * These share the same space as BASEP_CONTEXT_FLAG_*, and so must 233 * not collide with them. 234 */ 235 typedef __u32 base_context_create_flags; 236 237 /* No flags set */ 238 #define BASE_CONTEXT_CREATE_FLAG_NONE ((base_context_create_flags)0) 239 240 /* Base context is embedded in a cctx object (flag used for CINSTR 241 * software counter macros) 242 */ 243 #define BASE_CONTEXT_CCTX_EMBEDDED ((base_context_create_flags)1 << 0) 244 245 /* Base context is a 'System Monitor' context for Hardware counters. 246 * 247 * One important side effect of this is that job submission is disabled. 248 */ 249 #define BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED \ 250 ((base_context_create_flags)1 << 1) 251 252 /* Bit-shift used to encode a memory group ID in base_context_create_flags 253 */ 254 #define BASEP_CONTEXT_MMU_GROUP_ID_SHIFT (3) 255 256 /* Bitmask used to encode a memory group ID in base_context_create_flags 257 */ 258 #define BASEP_CONTEXT_MMU_GROUP_ID_MASK \ 259 ((base_context_create_flags)0xF << BASEP_CONTEXT_MMU_GROUP_ID_SHIFT) 260 261 /* Bitpattern describing the base_context_create_flags that can be 262 * passed to the kernel 263 */ 264 #define BASEP_CONTEXT_CREATE_KERNEL_FLAGS \ 265 (BASE_CONTEXT_SYSTEM_MONITOR_SUBMIT_DISABLED | \ 266 BASEP_CONTEXT_MMU_GROUP_ID_MASK) 267 268 /* Bitpattern describing the ::base_context_create_flags that can be 269 * passed to base_context_init() 270 */ 271 #define BASEP_CONTEXT_CREATE_ALLOWED_FLAGS \ 272 (BASE_CONTEXT_CCTX_EMBEDDED | BASEP_CONTEXT_CREATE_KERNEL_FLAGS) 273 274 /* 275 * Private flags used on the base context 276 * 277 * These start at bit 31, and run down to zero. 278 * 279 * They share the same space as base_context_create_flags, and so must 280 * not collide with them. 281 */ 282 283 /* Private flag tracking whether job descriptor dumping is disabled */ 284 #define BASEP_CONTEXT_FLAG_JOB_DUMP_DISABLED \ 285 ((base_context_create_flags)(1 << 31)) 286 287 /* Enable additional tracepoints for latency measurements (TL_ATOM_READY, 288 * TL_ATOM_DONE, TL_ATOM_PRIO_CHANGE, TL_ATOM_EVENT_POST) 289 */ 290 #define BASE_TLSTREAM_ENABLE_LATENCY_TRACEPOINTS (1 << 0) 291 292 /* Indicate that job dumping is enabled. This could affect certain timers 293 * to account for the performance impact. 294 */ 295 #define BASE_TLSTREAM_JOB_DUMPING_ENABLED (1 << 1) 296 297 #define BASE_TLSTREAM_FLAGS_MASK (BASE_TLSTREAM_ENABLE_LATENCY_TRACEPOINTS | \ 298 BASE_TLSTREAM_JOB_DUMPING_ENABLED) 299 /* 300 * Dependency stuff, keep it private for now. May want to expose it if 301 * we decide to make the number of semaphores a configurable 302 * option. 303 */ 304 #define BASE_JD_ATOM_COUNT 256 305 306 /* Maximum number of concurrent render passes. 307 */ 308 #define BASE_JD_RP_COUNT (256) 309 310 /* Set/reset values for a software event */ 311 #define BASE_JD_SOFT_EVENT_SET ((unsigned char)1) 312 #define BASE_JD_SOFT_EVENT_RESET ((unsigned char)0) 313 314 /** 315 * struct base_jd_udata - Per-job data 316 * 317 * This structure is used to store per-job data, and is completely unused 318 * by the Base driver. It can be used to store things such as callback 319 * function pointer, data to handle job completion. It is guaranteed to be 320 * untouched by the Base driver. 321 * 322 * @blob: per-job data array 323 */ 324 struct base_jd_udata { 325 __u64 blob[2]; 326 }; 327 328 /** 329 * typedef base_jd_dep_type - Job dependency type. 330 * 331 * A flags field will be inserted into the atom structure to specify whether a 332 * dependency is a data or ordering dependency (by putting it before/after 333 * 'core_req' in the structure it should be possible to add without changing 334 * the structure size). 335 * When the flag is set for a particular dependency to signal that it is an 336 * ordering only dependency then errors will not be propagated. 337 */ 338 typedef __u8 base_jd_dep_type; 339 340 #define BASE_JD_DEP_TYPE_INVALID (0) /**< Invalid dependency */ 341 #define BASE_JD_DEP_TYPE_DATA (1U << 0) /**< Data dependency */ 342 #define BASE_JD_DEP_TYPE_ORDER (1U << 1) /**< Order dependency */ 343 344 /** 345 * typedef base_jd_core_req - Job chain hardware requirements. 346 * 347 * A job chain must specify what GPU features it needs to allow the 348 * driver to schedule the job correctly. By not specifying the 349 * correct settings can/will cause an early job termination. Multiple 350 * values can be ORed together to specify multiple requirements. 351 * Special case is ::BASE_JD_REQ_DEP, which is used to express complex 352 * dependencies, and that doesn't execute anything on the hardware. 353 */ 354 typedef __u32 base_jd_core_req; 355 356 /* Requirements that come from the HW */ 357 358 /* No requirement, dependency only 359 */ 360 #define BASE_JD_REQ_DEP ((base_jd_core_req)0) 361 362 /* Requires fragment shaders 363 */ 364 #define BASE_JD_REQ_FS ((base_jd_core_req)1 << 0) 365 366 /* Requires compute shaders 367 * 368 * This covers any of the following GPU job types: 369 * - Vertex Shader Job 370 * - Geometry Shader Job 371 * - An actual Compute Shader Job 372 * 373 * Compare this with BASE_JD_REQ_ONLY_COMPUTE, which specifies that the 374 * job is specifically just the "Compute Shader" job type, and not the "Vertex 375 * Shader" nor the "Geometry Shader" job type. 376 */ 377 #define BASE_JD_REQ_CS ((base_jd_core_req)1 << 1) 378 379 /* Requires tiling */ 380 #define BASE_JD_REQ_T ((base_jd_core_req)1 << 2) 381 382 /* Requires cache flushes */ 383 #define BASE_JD_REQ_CF ((base_jd_core_req)1 << 3) 384 385 /* Requires value writeback */ 386 #define BASE_JD_REQ_V ((base_jd_core_req)1 << 4) 387 388 /* SW-only requirements - the HW does not expose these as part of the job slot 389 * capabilities 390 */ 391 392 /* Requires fragment job with AFBC encoding */ 393 #define BASE_JD_REQ_FS_AFBC ((base_jd_core_req)1 << 13) 394 395 /* SW-only requirement: coalesce completion events. 396 * If this bit is set then completion of this atom will not cause an event to 397 * be sent to userspace, whether successful or not; completion events will be 398 * deferred until an atom completes which does not have this bit set. 399 * 400 * This bit may not be used in combination with BASE_JD_REQ_EXTERNAL_RESOURCES. 401 */ 402 #define BASE_JD_REQ_EVENT_COALESCE ((base_jd_core_req)1 << 5) 403 404 /* SW Only requirement: the job chain requires a coherent core group. We don't 405 * mind which coherent core group is used. 406 */ 407 #define BASE_JD_REQ_COHERENT_GROUP ((base_jd_core_req)1 << 6) 408 409 /* SW Only requirement: The performance counters should be enabled only when 410 * they are needed, to reduce power consumption. 411 */ 412 #define BASE_JD_REQ_PERMON ((base_jd_core_req)1 << 7) 413 414 /* SW Only requirement: External resources are referenced by this atom. 415 * 416 * This bit may not be used in combination with BASE_JD_REQ_EVENT_COALESCE and 417 * BASE_JD_REQ_SOFT_EVENT_WAIT. 418 */ 419 #define BASE_JD_REQ_EXTERNAL_RESOURCES ((base_jd_core_req)1 << 8) 420 421 /* SW Only requirement: Software defined job. Jobs with this bit set will not be 422 * submitted to the hardware but will cause some action to happen within the 423 * driver 424 */ 425 #define BASE_JD_REQ_SOFT_JOB ((base_jd_core_req)1 << 9) 426 427 #define BASE_JD_REQ_SOFT_DUMP_CPU_GPU_TIME (BASE_JD_REQ_SOFT_JOB | 0x1) 428 #define BASE_JD_REQ_SOFT_FENCE_TRIGGER (BASE_JD_REQ_SOFT_JOB | 0x2) 429 #define BASE_JD_REQ_SOFT_FENCE_WAIT (BASE_JD_REQ_SOFT_JOB | 0x3) 430 431 /* 0x4 RESERVED for now */ 432 433 /* SW only requirement: event wait/trigger job. 434 * 435 * - BASE_JD_REQ_SOFT_EVENT_WAIT: this job will block until the event is set. 436 * - BASE_JD_REQ_SOFT_EVENT_SET: this job sets the event, thus unblocks the 437 * other waiting jobs. It completes immediately. 438 * - BASE_JD_REQ_SOFT_EVENT_RESET: this job resets the event, making it 439 * possible for other jobs to wait upon. It completes immediately. 440 */ 441 #define BASE_JD_REQ_SOFT_EVENT_WAIT (BASE_JD_REQ_SOFT_JOB | 0x5) 442 #define BASE_JD_REQ_SOFT_EVENT_SET (BASE_JD_REQ_SOFT_JOB | 0x6) 443 #define BASE_JD_REQ_SOFT_EVENT_RESET (BASE_JD_REQ_SOFT_JOB | 0x7) 444 445 #define BASE_JD_REQ_SOFT_DEBUG_COPY (BASE_JD_REQ_SOFT_JOB | 0x8) 446 447 /* SW only requirement: Just In Time allocation 448 * 449 * This job requests a single or multiple just-in-time allocations through a 450 * list of base_jit_alloc_info structure which is passed via the jc element of 451 * the atom. The number of base_jit_alloc_info structures present in the 452 * list is passed via the nr_extres element of the atom 453 * 454 * It should be noted that the id entry in base_jit_alloc_info must not 455 * be reused until it has been released via BASE_JD_REQ_SOFT_JIT_FREE. 456 * 457 * Should this soft job fail it is expected that a BASE_JD_REQ_SOFT_JIT_FREE 458 * soft job to free the JIT allocation is still made. 459 * 460 * The job will complete immediately. 461 */ 462 #define BASE_JD_REQ_SOFT_JIT_ALLOC (BASE_JD_REQ_SOFT_JOB | 0x9) 463 464 /* SW only requirement: Just In Time free 465 * 466 * This job requests a single or multiple just-in-time allocations created by 467 * BASE_JD_REQ_SOFT_JIT_ALLOC to be freed. The ID list of the just-in-time 468 * allocations is passed via the jc element of the atom. 469 * 470 * The job will complete immediately. 471 */ 472 #define BASE_JD_REQ_SOFT_JIT_FREE (BASE_JD_REQ_SOFT_JOB | 0xa) 473 474 /* SW only requirement: Map external resource 475 * 476 * This job requests external resource(s) are mapped once the dependencies 477 * of the job have been satisfied. The list of external resources are 478 * passed via the jc element of the atom which is a pointer to a 479 * base_external_resource_list. 480 */ 481 #define BASE_JD_REQ_SOFT_EXT_RES_MAP (BASE_JD_REQ_SOFT_JOB | 0xb) 482 483 /* SW only requirement: Unmap external resource 484 * 485 * This job requests external resource(s) are unmapped once the dependencies 486 * of the job has been satisfied. The list of external resources are 487 * passed via the jc element of the atom which is a pointer to a 488 * base_external_resource_list. 489 */ 490 #define BASE_JD_REQ_SOFT_EXT_RES_UNMAP (BASE_JD_REQ_SOFT_JOB | 0xc) 491 492 /* HW Requirement: Requires Compute shaders (but not Vertex or Geometry Shaders) 493 * 494 * This indicates that the Job Chain contains GPU jobs of the 'Compute 495 * Shaders' type. 496 * 497 * In contrast to BASE_JD_REQ_CS, this does not indicate that the Job 498 * Chain contains 'Geometry Shader' or 'Vertex Shader' jobs. 499 */ 500 #define BASE_JD_REQ_ONLY_COMPUTE ((base_jd_core_req)1 << 10) 501 502 /* HW Requirement: Use the base_jd_atom::device_nr field to specify a 503 * particular core group 504 * 505 * If both BASE_JD_REQ_COHERENT_GROUP and this flag are set, this flag 506 * takes priority 507 * 508 * This is only guaranteed to work for BASE_JD_REQ_ONLY_COMPUTE atoms. 509 * 510 * If the core availability policy is keeping the required core group turned 511 * off, then the job will fail with a BASE_JD_EVENT_PM_EVENT error code. 512 */ 513 #define BASE_JD_REQ_SPECIFIC_COHERENT_GROUP ((base_jd_core_req)1 << 11) 514 515 /* SW Flag: If this bit is set then the successful completion of this atom 516 * will not cause an event to be sent to userspace 517 */ 518 #define BASE_JD_REQ_EVENT_ONLY_ON_FAILURE ((base_jd_core_req)1 << 12) 519 520 /* SW Flag: If this bit is set then completion of this atom will not cause an 521 * event to be sent to userspace, whether successful or not. 522 */ 523 #define BASEP_JD_REQ_EVENT_NEVER ((base_jd_core_req)1 << 14) 524 525 /* SW Flag: Skip GPU cache clean and invalidation before starting a GPU job. 526 * 527 * If this bit is set then the GPU's cache will not be cleaned and invalidated 528 * until a GPU job starts which does not have this bit set or a job completes 529 * which does not have the BASE_JD_REQ_SKIP_CACHE_END bit set. Do not use 530 * if the CPU may have written to memory addressed by the job since the last job 531 * without this bit set was submitted. 532 */ 533 #define BASE_JD_REQ_SKIP_CACHE_START ((base_jd_core_req)1 << 15) 534 535 /* SW Flag: Skip GPU cache clean and invalidation after a GPU job completes. 536 * 537 * If this bit is set then the GPU's cache will not be cleaned and invalidated 538 * until a GPU job completes which does not have this bit set or a job starts 539 * which does not have the BASE_JD_REQ_SKIP_CACHE_START bit set. Do not use 540 * if the CPU may read from or partially overwrite memory addressed by the job 541 * before the next job without this bit set completes. 542 */ 543 #define BASE_JD_REQ_SKIP_CACHE_END ((base_jd_core_req)1 << 16) 544 545 /* Request the atom be executed on a specific job slot. 546 * 547 * When this flag is specified, it takes precedence over any existing job slot 548 * selection logic. 549 */ 550 #define BASE_JD_REQ_JOB_SLOT ((base_jd_core_req)1 << 17) 551 552 /* SW-only requirement: The atom is the start of a renderpass. 553 * 554 * If this bit is set then the job chain will be soft-stopped if it causes the 555 * GPU to write beyond the end of the physical pages backing the tiler heap, and 556 * committing more memory to the heap would exceed an internal threshold. It may 557 * be resumed after running one of the job chains attached to an atom with 558 * BASE_JD_REQ_END_RENDERPASS set and the same renderpass ID. It may be 559 * resumed multiple times until it completes without memory usage exceeding the 560 * threshold. 561 * 562 * Usually used with BASE_JD_REQ_T. 563 */ 564 #define BASE_JD_REQ_START_RENDERPASS ((base_jd_core_req)1 << 18) 565 566 /* SW-only requirement: The atom is the end of a renderpass. 567 * 568 * If this bit is set then the atom incorporates the CPU address of a 569 * base_jd_fragment object instead of the GPU address of a job chain. 570 * 571 * Which job chain is run depends upon whether the atom with the same renderpass 572 * ID and the BASE_JD_REQ_START_RENDERPASS bit set completed normally or 573 * was soft-stopped when it exceeded an upper threshold for tiler heap memory 574 * usage. 575 * 576 * It also depends upon whether one of the job chains attached to the atom has 577 * already been run as part of the same renderpass (in which case it would have 578 * written unresolved multisampled and otherwise-discarded output to temporary 579 * buffers that need to be read back). The job chain for doing a forced read and 580 * forced write (from/to temporary buffers) is run as many times as necessary. 581 * 582 * Usually used with BASE_JD_REQ_FS. 583 */ 584 #define BASE_JD_REQ_END_RENDERPASS ((base_jd_core_req)1 << 19) 585 586 /* SW-only requirement: The atom needs to run on a limited core mask affinity. 587 * 588 * If this bit is set then the kbase_context.limited_core_mask will be applied 589 * to the affinity. 590 */ 591 #define BASE_JD_REQ_LIMITED_CORE_MASK ((base_jd_core_req)1 << 20) 592 593 /* These requirement bits are currently unused in base_jd_core_req 594 */ 595 #define BASEP_JD_REQ_RESERVED \ 596 (~(BASE_JD_REQ_ATOM_TYPE | BASE_JD_REQ_EXTERNAL_RESOURCES | \ 597 BASE_JD_REQ_EVENT_ONLY_ON_FAILURE | BASEP_JD_REQ_EVENT_NEVER | \ 598 BASE_JD_REQ_EVENT_COALESCE | \ 599 BASE_JD_REQ_COHERENT_GROUP | BASE_JD_REQ_SPECIFIC_COHERENT_GROUP | \ 600 BASE_JD_REQ_FS_AFBC | BASE_JD_REQ_PERMON | \ 601 BASE_JD_REQ_SKIP_CACHE_START | BASE_JD_REQ_SKIP_CACHE_END | \ 602 BASE_JD_REQ_JOB_SLOT | BASE_JD_REQ_START_RENDERPASS | \ 603 BASE_JD_REQ_END_RENDERPASS | BASE_JD_REQ_LIMITED_CORE_MASK)) 604 605 /* Mask of all bits in base_jd_core_req that control the type of the atom. 606 * 607 * This allows dependency only atoms to have flags set 608 */ 609 #define BASE_JD_REQ_ATOM_TYPE \ 610 (BASE_JD_REQ_FS | BASE_JD_REQ_CS | BASE_JD_REQ_T | BASE_JD_REQ_CF | \ 611 BASE_JD_REQ_V | BASE_JD_REQ_SOFT_JOB | BASE_JD_REQ_ONLY_COMPUTE) 612 613 /** 614 * Mask of all bits in base_jd_core_req that control the type of a soft job. 615 */ 616 #define BASE_JD_REQ_SOFT_JOB_TYPE (BASE_JD_REQ_SOFT_JOB | 0x1f) 617 618 /* Returns non-zero value if core requirements passed define a soft job or 619 * a dependency only job. 620 */ 621 #define BASE_JD_REQ_SOFT_JOB_OR_DEP(core_req) \ 622 (((core_req) & BASE_JD_REQ_SOFT_JOB) || \ 623 ((core_req) & BASE_JD_REQ_ATOM_TYPE) == BASE_JD_REQ_DEP) 624 625 /** 626 * enum kbase_jd_atom_state 627 * 628 * @KBASE_JD_ATOM_STATE_UNUSED: Atom is not used. 629 * @KBASE_JD_ATOM_STATE_QUEUED: Atom is queued in JD. 630 * @KBASE_JD_ATOM_STATE_IN_JS: Atom has been given to JS (is runnable/running). 631 * @KBASE_JD_ATOM_STATE_HW_COMPLETED: Atom has been completed, but not yet 632 * handed back to job dispatcher for 633 * dependency resolution. 634 * @KBASE_JD_ATOM_STATE_COMPLETED: Atom has been completed, but not yet handed 635 * back to userspace. 636 */ 637 enum kbase_jd_atom_state { 638 KBASE_JD_ATOM_STATE_UNUSED, 639 KBASE_JD_ATOM_STATE_QUEUED, 640 KBASE_JD_ATOM_STATE_IN_JS, 641 KBASE_JD_ATOM_STATE_HW_COMPLETED, 642 KBASE_JD_ATOM_STATE_COMPLETED 643 }; 644 645 /** 646 * typedef base_atom_id - Type big enough to store an atom number in. 647 */ 648 typedef __u8 base_atom_id; 649 650 /** 651 * struct base_dependency - 652 * 653 * @atom_id: An atom number 654 * @dependency_type: Dependency type 655 */ 656 struct base_dependency { 657 base_atom_id atom_id; 658 base_jd_dep_type dependency_type; 659 }; 660 661 /** 662 * struct base_jd_fragment - Set of GPU fragment job chains used for rendering. 663 * 664 * @norm_read_norm_write: Job chain for full rendering. 665 * GPU address of a fragment job chain to render in the 666 * circumstance where the tiler job chain did not exceed 667 * its memory usage threshold and no fragment job chain 668 * was previously run for the same renderpass. 669 * It is used no more than once per renderpass. 670 * @norm_read_forced_write: Job chain for starting incremental 671 * rendering. 672 * GPU address of a fragment job chain to render in 673 * the circumstance where the tiler job chain exceeded 674 * its memory usage threshold for the first time and 675 * no fragment job chain was previously run for the 676 * same renderpass. 677 * Writes unresolved multisampled and normally- 678 * discarded output to temporary buffers that must be 679 * read back by a subsequent forced_read job chain 680 * before the renderpass is complete. 681 * It is used no more than once per renderpass. 682 * @forced_read_forced_write: Job chain for continuing incremental 683 * rendering. 684 * GPU address of a fragment job chain to render in 685 * the circumstance where the tiler job chain 686 * exceeded its memory usage threshold again 687 * and a fragment job chain was previously run for 688 * the same renderpass. 689 * Reads unresolved multisampled and 690 * normally-discarded output from temporary buffers 691 * written by a previous forced_write job chain and 692 * writes the same to temporary buffers again. 693 * It is used as many times as required until 694 * rendering completes. 695 * @forced_read_norm_write: Job chain for ending incremental rendering. 696 * GPU address of a fragment job chain to render in the 697 * circumstance where the tiler job chain did not 698 * exceed its memory usage threshold this time and a 699 * fragment job chain was previously run for the same 700 * renderpass. 701 * Reads unresolved multisampled and normally-discarded 702 * output from temporary buffers written by a previous 703 * forced_write job chain in order to complete a 704 * renderpass. 705 * It is used no more than once per renderpass. 706 * 707 * This structure is referenced by the main atom structure if 708 * BASE_JD_REQ_END_RENDERPASS is set in the base_jd_core_req. 709 */ 710 struct base_jd_fragment { 711 __u64 norm_read_norm_write; 712 __u64 norm_read_forced_write; 713 __u64 forced_read_forced_write; 714 __u64 forced_read_norm_write; 715 }; 716 717 /** 718 * typedef base_jd_prio - Base Atom priority. 719 * 720 * Only certain priority levels are actually implemented, as specified by the 721 * BASE_JD_PRIO_<...> definitions below. It is undefined to use a priority 722 * level that is not one of those defined below. 723 * 724 * Priority levels only affect scheduling after the atoms have had dependencies 725 * resolved. For example, a low priority atom that has had its dependencies 726 * resolved might run before a higher priority atom that has not had its 727 * dependencies resolved. 728 * 729 * In general, fragment atoms do not affect non-fragment atoms with 730 * lower priorities, and vice versa. One exception is that there is only one 731 * priority value for each context. So a high-priority (e.g.) fragment atom 732 * could increase its context priority, causing its non-fragment atoms to also 733 * be scheduled sooner. 734 * 735 * The atoms are scheduled as follows with respect to their priorities: 736 * * Let atoms 'X' and 'Y' be for the same job slot who have dependencies 737 * resolved, and atom 'X' has a higher priority than atom 'Y' 738 * * If atom 'Y' is currently running on the HW, then it is interrupted to 739 * allow atom 'X' to run soon after 740 * * If instead neither atom 'Y' nor atom 'X' are running, then when choosing 741 * the next atom to run, atom 'X' will always be chosen instead of atom 'Y' 742 * * Any two atoms that have the same priority could run in any order with 743 * respect to each other. That is, there is no ordering constraint between 744 * atoms of the same priority. 745 * 746 * The sysfs file 'js_ctx_scheduling_mode' is used to control how atoms are 747 * scheduled between contexts. The default value, 0, will cause higher-priority 748 * atoms to be scheduled first, regardless of their context. The value 1 will 749 * use a round-robin algorithm when deciding which context's atoms to schedule 750 * next, so higher-priority atoms can only preempt lower priority atoms within 751 * the same context. See KBASE_JS_SYSTEM_PRIORITY_MODE and 752 * KBASE_JS_PROCESS_LOCAL_PRIORITY_MODE for more details. 753 */ 754 typedef __u8 base_jd_prio; 755 756 /* Medium atom priority. This is a priority higher than BASE_JD_PRIO_LOW */ 757 #define BASE_JD_PRIO_MEDIUM ((base_jd_prio)0) 758 /* High atom priority. This is a priority higher than BASE_JD_PRIO_MEDIUM and 759 * BASE_JD_PRIO_LOW 760 */ 761 #define BASE_JD_PRIO_HIGH ((base_jd_prio)1) 762 /* Low atom priority. */ 763 #define BASE_JD_PRIO_LOW ((base_jd_prio)2) 764 /* Real-Time atom priority. This is a priority higher than BASE_JD_PRIO_HIGH, 765 * BASE_JD_PRIO_MEDIUM, and BASE_JD_PRIO_LOW 766 */ 767 #define BASE_JD_PRIO_REALTIME ((base_jd_prio)3) 768 769 /* Count of the number of priority levels. This itself is not a valid 770 * base_jd_prio setting 771 */ 772 #define BASE_JD_NR_PRIO_LEVELS 4 773 774 /** 775 * struct base_jd_atom_v2 - Node of a dependency graph used to submit a 776 * GPU job chain or soft-job to the kernel driver. 777 * 778 * @jc: GPU address of a job chain or (if BASE_JD_REQ_END_RENDERPASS 779 * is set in the base_jd_core_req) the CPU address of a 780 * base_jd_fragment object. 781 * @udata: User data. 782 * @extres_list: List of external resources. 783 * @nr_extres: Number of external resources or JIT allocations. 784 * @jit_id: Zero-terminated array of IDs of just-in-time memory 785 * allocations written to by the atom. When the atom 786 * completes, the value stored at the 787 * &struct_base_jit_alloc_info.heap_info_gpu_addr of 788 * each allocation is read in order to enforce an 789 * overall physical memory usage limit. 790 * @pre_dep: Pre-dependencies. One need to use SETTER function to assign 791 * this field; this is done in order to reduce possibility of 792 * improper assignment of a dependency field. 793 * @atom_number: Unique number to identify the atom. 794 * @prio: Atom priority. Refer to base_jd_prio for more details. 795 * @device_nr: Core group when BASE_JD_REQ_SPECIFIC_COHERENT_GROUP 796 * specified. 797 * @jobslot: Job slot to use when BASE_JD_REQ_JOB_SLOT is specified. 798 * @core_req: Core requirements. 799 * @renderpass_id: Renderpass identifier used to associate an atom that has 800 * BASE_JD_REQ_START_RENDERPASS set in its core requirements 801 * with an atom that has BASE_JD_REQ_END_RENDERPASS set. 802 * @padding: Unused. Must be zero. 803 * 804 * This structure has changed since UK 10.2 for which base_jd_core_req was a 805 * __u16 value. 806 * 807 * In UK 10.3 a core_req field of a __u32 type was added to the end of the 808 * structure, and the place in the structure previously occupied by __u16 809 * core_req was kept but renamed to compat_core_req. 810 * 811 * From UK 11.20 - compat_core_req is now occupied by __u8 jit_id[2]. 812 * Compatibility with UK 10.x from UK 11.y is not handled because 813 * the major version increase prevents this. 814 * 815 * For UK 11.20 jit_id[2] must be initialized to zero. 816 */ 817 struct base_jd_atom_v2 { 818 __u64 jc; 819 struct base_jd_udata udata; 820 __u64 extres_list; 821 __u16 nr_extres; 822 __u8 jit_id[2]; 823 struct base_dependency pre_dep[2]; 824 base_atom_id atom_number; 825 base_jd_prio prio; 826 __u8 device_nr; 827 __u8 jobslot; 828 base_jd_core_req core_req; 829 __u8 renderpass_id; 830 __u8 padding[7]; 831 }; 832 833 /** 834 * struct base_jd_atom - Same as base_jd_atom_v2, but has an extra seq_nr 835 * at the beginning. 836 * 837 * @seq_nr: Sequence number of logical grouping of atoms. 838 * @jc: GPU address of a job chain or (if BASE_JD_REQ_END_RENDERPASS 839 * is set in the base_jd_core_req) the CPU address of a 840 * base_jd_fragment object. 841 * @udata: User data. 842 * @extres_list: List of external resources. 843 * @nr_extres: Number of external resources or JIT allocations. 844 * @jit_id: Zero-terminated array of IDs of just-in-time memory 845 * allocations written to by the atom. When the atom 846 * completes, the value stored at the 847 * &struct_base_jit_alloc_info.heap_info_gpu_addr of 848 * each allocation is read in order to enforce an 849 * overall physical memory usage limit. 850 * @pre_dep: Pre-dependencies. One need to use SETTER function to assign 851 * this field; this is done in order to reduce possibility of 852 * improper assignment of a dependency field. 853 * @atom_number: Unique number to identify the atom. 854 * @prio: Atom priority. Refer to base_jd_prio for more details. 855 * @device_nr: Core group when BASE_JD_REQ_SPECIFIC_COHERENT_GROUP 856 * specified. 857 * @jobslot: Job slot to use when BASE_JD_REQ_JOB_SLOT is specified. 858 * @core_req: Core requirements. 859 * @renderpass_id: Renderpass identifier used to associate an atom that has 860 * BASE_JD_REQ_START_RENDERPASS set in its core requirements 861 * with an atom that has BASE_JD_REQ_END_RENDERPASS set. 862 * @padding: Unused. Must be zero. 863 */ 864 typedef struct base_jd_atom { 865 __u64 seq_nr; 866 __u64 jc; 867 struct base_jd_udata udata; 868 __u64 extres_list; 869 __u16 nr_extres; 870 __u8 jit_id[2]; 871 struct base_dependency pre_dep[2]; 872 base_atom_id atom_number; 873 base_jd_prio prio; 874 __u8 device_nr; 875 __u8 jobslot; 876 base_jd_core_req core_req; 877 __u8 renderpass_id; 878 __u8 padding[7]; 879 } base_jd_atom; 880 881 /* Job chain event code bits 882 * Defines the bits used to create ::base_jd_event_code 883 */ 884 enum { 885 BASE_JD_SW_EVENT_KERNEL = (1u << 15), /* Kernel side event */ 886 BASE_JD_SW_EVENT = (1u << 14), /* SW defined event */ 887 /* Event indicates success (SW events only) */ 888 BASE_JD_SW_EVENT_SUCCESS = (1u << 13), 889 BASE_JD_SW_EVENT_JOB = (0u << 11), /* Job related event */ 890 BASE_JD_SW_EVENT_BAG = (1u << 11), /* Bag related event */ 891 BASE_JD_SW_EVENT_INFO = (2u << 11), /* Misc/info event */ 892 BASE_JD_SW_EVENT_RESERVED = (3u << 11), /* Reserved event type */ 893 /* Mask to extract the type from an event code */ 894 BASE_JD_SW_EVENT_TYPE_MASK = (3u << 11) 895 }; 896 897 /** 898 * enum base_jd_event_code - Job chain event codes 899 * 900 * @BASE_JD_EVENT_RANGE_HW_NONFAULT_START: Start of hardware non-fault status 901 * codes. 902 * Obscurely, BASE_JD_EVENT_TERMINATED 903 * indicates a real fault, because the 904 * job was hard-stopped. 905 * @BASE_JD_EVENT_NOT_STARTED: Can't be seen by userspace, treated as 906 * 'previous job done'. 907 * @BASE_JD_EVENT_STOPPED: Can't be seen by userspace, becomes 908 * TERMINATED, DONE or JOB_CANCELLED. 909 * @BASE_JD_EVENT_TERMINATED: This is actually a fault status code - the job 910 * was hard stopped. 911 * @BASE_JD_EVENT_ACTIVE: Can't be seen by userspace, jobs only returned on 912 * complete/fail/cancel. 913 * @BASE_JD_EVENT_RANGE_HW_NONFAULT_END: End of hardware non-fault status codes. 914 * Obscurely, BASE_JD_EVENT_TERMINATED 915 * indicates a real fault, 916 * because the job was hard-stopped. 917 * @BASE_JD_EVENT_RANGE_HW_FAULT_OR_SW_ERROR_START: Start of hardware fault and 918 * software error status codes. 919 * @BASE_JD_EVENT_RANGE_HW_FAULT_OR_SW_ERROR_END: End of hardware fault and 920 * software error status codes. 921 * @BASE_JD_EVENT_RANGE_SW_SUCCESS_START: Start of software success status 922 * codes. 923 * @BASE_JD_EVENT_RANGE_SW_SUCCESS_END: End of software success status codes. 924 * @BASE_JD_EVENT_RANGE_KERNEL_ONLY_START: Start of kernel-only status codes. 925 * Such codes are never returned to 926 * user-space. 927 * @BASE_JD_EVENT_RANGE_KERNEL_ONLY_END: End of kernel-only status codes. 928 * @BASE_JD_EVENT_DONE: atom has completed successfull 929 * @BASE_JD_EVENT_JOB_CONFIG_FAULT: Atom dependencies configuration error which 930 * shall result in a failed atom 931 * @BASE_JD_EVENT_JOB_POWER_FAULT: The job could not be executed because the 932 * part of the memory system required to access 933 * job descriptors was not powered on 934 * @BASE_JD_EVENT_JOB_READ_FAULT: Reading a job descriptor into the Job 935 * manager failed 936 * @BASE_JD_EVENT_JOB_WRITE_FAULT: Writing a job descriptor from the Job 937 * manager failed 938 * @BASE_JD_EVENT_JOB_AFFINITY_FAULT: The job could not be executed because the 939 * specified affinity mask does not intersect 940 * any available cores 941 * @BASE_JD_EVENT_JOB_BUS_FAULT: A bus access failed while executing a job 942 * @BASE_JD_EVENT_INSTR_INVALID_PC: A shader instruction with an illegal program 943 * counter was executed. 944 * @BASE_JD_EVENT_INSTR_INVALID_ENC: A shader instruction with an illegal 945 * encoding was executed. 946 * @BASE_JD_EVENT_INSTR_TYPE_MISMATCH: A shader instruction was executed where 947 * the instruction encoding did not match the 948 * instruction type encoded in the program 949 * counter. 950 * @BASE_JD_EVENT_INSTR_OPERAND_FAULT: A shader instruction was executed that 951 * contained invalid combinations of operands. 952 * @BASE_JD_EVENT_INSTR_TLS_FAULT: A shader instruction was executed that tried 953 * to access the thread local storage section 954 * of another thread. 955 * @BASE_JD_EVENT_INSTR_ALIGN_FAULT: A shader instruction was executed that 956 * tried to do an unsupported unaligned memory 957 * access. 958 * @BASE_JD_EVENT_INSTR_BARRIER_FAULT: A shader instruction was executed that 959 * failed to complete an instruction barrier. 960 * @BASE_JD_EVENT_DATA_INVALID_FAULT: Any data structure read as part of the job 961 * contains invalid combinations of data. 962 * @BASE_JD_EVENT_TILE_RANGE_FAULT: Tile or fragment shading was asked to 963 * process a tile that is entirely outside the 964 * bounding box of the frame. 965 * @BASE_JD_EVENT_STATE_FAULT: Matches ADDR_RANGE_FAULT. A virtual address 966 * has been found that exceeds the virtual 967 * address range. 968 * @BASE_JD_EVENT_OUT_OF_MEMORY: The tiler ran out of memory when executing a job. 969 * @BASE_JD_EVENT_UNKNOWN: If multiple jobs in a job chain fail, only 970 * the first one the reports an error will set 971 * and return full error information. 972 * Subsequent failing jobs will not update the 973 * error status registers, and may write an 974 * error status of UNKNOWN. 975 * @BASE_JD_EVENT_DELAYED_BUS_FAULT: The GPU received a bus fault for access to 976 * physical memory where the original virtual 977 * address is no longer available. 978 * @BASE_JD_EVENT_SHAREABILITY_FAULT: Matches GPU_SHAREABILITY_FAULT. A cache 979 * has detected that the same line has been 980 * accessed as both shareable and non-shareable 981 * memory from inside the GPU. 982 * @BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL1: A memory access hit an invalid table 983 * entry at level 1 of the translation table. 984 * @BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL2: A memory access hit an invalid table 985 * entry at level 2 of the translation table. 986 * @BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL3: A memory access hit an invalid table 987 * entry at level 3 of the translation table. 988 * @BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL4: A memory access hit an invalid table 989 * entry at level 4 of the translation table. 990 * @BASE_JD_EVENT_PERMISSION_FAULT: A memory access could not be allowed due to 991 * the permission flags set in translation 992 * table 993 * @BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL1: A bus fault occurred while reading 994 * level 0 of the translation tables. 995 * @BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL2: A bus fault occurred while reading 996 * level 1 of the translation tables. 997 * @BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL3: A bus fault occurred while reading 998 * level 2 of the translation tables. 999 * @BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL4: A bus fault occurred while reading 1000 * level 3 of the translation tables. 1001 * @BASE_JD_EVENT_ACCESS_FLAG: Matches ACCESS_FLAG_0. A memory access hit a 1002 * translation table entry with the ACCESS_FLAG 1003 * bit set to zero in level 0 of the 1004 * page table, and the DISABLE_AF_FAULT flag 1005 * was not set. 1006 * @BASE_JD_EVENT_MEM_GROWTH_FAILED: raised for JIT_ALLOC atoms that failed to 1007 * grow memory on demand 1008 * @BASE_JD_EVENT_JOB_CANCELLED: raised when this atom was hard-stopped or its 1009 * dependencies failed 1010 * @BASE_JD_EVENT_JOB_INVALID: raised for many reasons, including invalid data 1011 * in the atom which overlaps with 1012 * BASE_JD_EVENT_JOB_CONFIG_FAULT, or if the 1013 * platform doesn't support the feature specified in 1014 * the atom. 1015 * @BASE_JD_EVENT_PM_EVENT: TODO: remove as it's not used 1016 * @BASE_JD_EVENT_TIMED_OUT: TODO: remove as it's not used 1017 * @BASE_JD_EVENT_BAG_INVALID: TODO: remove as it's not used 1018 * @BASE_JD_EVENT_PROGRESS_REPORT: TODO: remove as it's not used 1019 * @BASE_JD_EVENT_BAG_DONE: TODO: remove as it's not used 1020 * @BASE_JD_EVENT_DRV_TERMINATED: this is a special event generated to indicate 1021 * to userspace that the KBase context has been 1022 * destroyed and Base should stop listening for 1023 * further events 1024 * @BASE_JD_EVENT_REMOVED_FROM_NEXT: raised when an atom that was configured in 1025 * the GPU has to be retried (but it has not 1026 * started) due to e.g., GPU reset 1027 * @BASE_JD_EVENT_END_RP_DONE: this is used for incremental rendering to signal 1028 * the completion of a renderpass. This value 1029 * shouldn't be returned to userspace but I haven't 1030 * seen where it is reset back to JD_EVENT_DONE. 1031 * 1032 * HW and low-level SW events are represented by event codes. 1033 * The status of jobs which succeeded are also represented by 1034 * an event code (see @BASE_JD_EVENT_DONE). 1035 * Events are usually reported as part of a &struct base_jd_event. 1036 * 1037 * The event codes are encoded in the following way: 1038 * * 10:0 - subtype 1039 * * 12:11 - type 1040 * * 13 - SW success (only valid if the SW bit is set) 1041 * * 14 - SW event (HW event if not set) 1042 * * 15 - Kernel event (should never be seen in userspace) 1043 * 1044 * Events are split up into ranges as follows: 1045 * * BASE_JD_EVENT_RANGE_<description>_START 1046 * * BASE_JD_EVENT_RANGE_<description>_END 1047 * 1048 * code is in <description>'s range when: 1049 * BASE_JD_EVENT_RANGE_<description>_START <= code < 1050 * BASE_JD_EVENT_RANGE_<description>_END 1051 * 1052 * Ranges can be asserted for adjacency by testing that the END of the previous 1053 * is equal to the START of the next. This is useful for optimizing some tests 1054 * for range. 1055 * 1056 * A limitation is that the last member of this enum must explicitly be handled 1057 * (with an assert-unreachable statement) in switch statements that use 1058 * variables of this type. Otherwise, the compiler warns that we have not 1059 * handled that enum value. 1060 */ 1061 enum base_jd_event_code { 1062 /* HW defined exceptions */ 1063 BASE_JD_EVENT_RANGE_HW_NONFAULT_START = 0, 1064 1065 /* non-fatal exceptions */ 1066 BASE_JD_EVENT_NOT_STARTED = 0x00, 1067 BASE_JD_EVENT_DONE = 0x01, 1068 BASE_JD_EVENT_STOPPED = 0x03, 1069 BASE_JD_EVENT_TERMINATED = 0x04, 1070 BASE_JD_EVENT_ACTIVE = 0x08, 1071 1072 BASE_JD_EVENT_RANGE_HW_NONFAULT_END = 0x40, 1073 BASE_JD_EVENT_RANGE_HW_FAULT_OR_SW_ERROR_START = 0x40, 1074 1075 /* job exceptions */ 1076 BASE_JD_EVENT_JOB_CONFIG_FAULT = 0x40, 1077 BASE_JD_EVENT_JOB_POWER_FAULT = 0x41, 1078 BASE_JD_EVENT_JOB_READ_FAULT = 0x42, 1079 BASE_JD_EVENT_JOB_WRITE_FAULT = 0x43, 1080 BASE_JD_EVENT_JOB_AFFINITY_FAULT = 0x44, 1081 BASE_JD_EVENT_JOB_BUS_FAULT = 0x48, 1082 BASE_JD_EVENT_INSTR_INVALID_PC = 0x50, 1083 BASE_JD_EVENT_INSTR_INVALID_ENC = 0x51, 1084 BASE_JD_EVENT_INSTR_TYPE_MISMATCH = 0x52, 1085 BASE_JD_EVENT_INSTR_OPERAND_FAULT = 0x53, 1086 BASE_JD_EVENT_INSTR_TLS_FAULT = 0x54, 1087 BASE_JD_EVENT_INSTR_BARRIER_FAULT = 0x55, 1088 BASE_JD_EVENT_INSTR_ALIGN_FAULT = 0x56, 1089 BASE_JD_EVENT_DATA_INVALID_FAULT = 0x58, 1090 BASE_JD_EVENT_TILE_RANGE_FAULT = 0x59, 1091 BASE_JD_EVENT_STATE_FAULT = 0x5A, 1092 BASE_JD_EVENT_OUT_OF_MEMORY = 0x60, 1093 BASE_JD_EVENT_UNKNOWN = 0x7F, 1094 1095 /* GPU exceptions */ 1096 BASE_JD_EVENT_DELAYED_BUS_FAULT = 0x80, 1097 BASE_JD_EVENT_SHAREABILITY_FAULT = 0x88, 1098 1099 /* MMU exceptions */ 1100 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL1 = 0xC1, 1101 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL2 = 0xC2, 1102 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL3 = 0xC3, 1103 BASE_JD_EVENT_TRANSLATION_FAULT_LEVEL4 = 0xC4, 1104 BASE_JD_EVENT_PERMISSION_FAULT = 0xC8, 1105 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL1 = 0xD1, 1106 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL2 = 0xD2, 1107 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL3 = 0xD3, 1108 BASE_JD_EVENT_TRANSTAB_BUS_FAULT_LEVEL4 = 0xD4, 1109 BASE_JD_EVENT_ACCESS_FLAG = 0xD8, 1110 1111 /* SW defined exceptions */ 1112 BASE_JD_EVENT_MEM_GROWTH_FAILED = 1113 BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x000, 1114 BASE_JD_EVENT_TIMED_OUT = 1115 BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x001, 1116 BASE_JD_EVENT_JOB_CANCELLED = 1117 BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x002, 1118 BASE_JD_EVENT_JOB_INVALID = 1119 BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x003, 1120 BASE_JD_EVENT_PM_EVENT = 1121 BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_JOB | 0x004, 1122 1123 BASE_JD_EVENT_BAG_INVALID = 1124 BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_BAG | 0x003, 1125 1126 BASE_JD_EVENT_RANGE_HW_FAULT_OR_SW_ERROR_END = BASE_JD_SW_EVENT | 1127 BASE_JD_SW_EVENT_RESERVED | 0x3FF, 1128 1129 BASE_JD_EVENT_RANGE_SW_SUCCESS_START = BASE_JD_SW_EVENT | 1130 BASE_JD_SW_EVENT_SUCCESS | 0x000, 1131 1132 BASE_JD_EVENT_PROGRESS_REPORT = BASE_JD_SW_EVENT | 1133 BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_JOB | 0x000, 1134 BASE_JD_EVENT_BAG_DONE = BASE_JD_SW_EVENT | BASE_JD_SW_EVENT_SUCCESS | 1135 BASE_JD_SW_EVENT_BAG | 0x000, 1136 BASE_JD_EVENT_DRV_TERMINATED = BASE_JD_SW_EVENT | 1137 BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_INFO | 0x000, 1138 1139 BASE_JD_EVENT_RANGE_SW_SUCCESS_END = BASE_JD_SW_EVENT | 1140 BASE_JD_SW_EVENT_SUCCESS | BASE_JD_SW_EVENT_RESERVED | 0x3FF, 1141 1142 BASE_JD_EVENT_RANGE_KERNEL_ONLY_START = BASE_JD_SW_EVENT | 1143 BASE_JD_SW_EVENT_KERNEL | 0x000, 1144 BASE_JD_EVENT_REMOVED_FROM_NEXT = BASE_JD_SW_EVENT | 1145 BASE_JD_SW_EVENT_KERNEL | BASE_JD_SW_EVENT_JOB | 0x000, 1146 BASE_JD_EVENT_END_RP_DONE = BASE_JD_SW_EVENT | 1147 BASE_JD_SW_EVENT_KERNEL | BASE_JD_SW_EVENT_JOB | 0x001, 1148 1149 BASE_JD_EVENT_RANGE_KERNEL_ONLY_END = BASE_JD_SW_EVENT | 1150 BASE_JD_SW_EVENT_KERNEL | BASE_JD_SW_EVENT_RESERVED | 0x3FF 1151 }; 1152 1153 /** 1154 * struct base_jd_event_v2 - Event reporting structure 1155 * 1156 * @event_code: event code. 1157 * @atom_number: the atom number that has completed. 1158 * @udata: user data. 1159 * 1160 * This structure is used by the kernel driver to report information 1161 * about GPU events. They can either be HW-specific events or low-level 1162 * SW events, such as job-chain completion. 1163 * 1164 * The event code contains an event type field which can be extracted 1165 * by ANDing with BASE_JD_SW_EVENT_TYPE_MASK. 1166 */ 1167 struct base_jd_event_v2 { 1168 enum base_jd_event_code event_code; 1169 base_atom_id atom_number; 1170 struct base_jd_udata udata; 1171 }; 1172 1173 /** 1174 * struct base_dump_cpu_gpu_counters - Structure for 1175 * BASE_JD_REQ_SOFT_DUMP_CPU_GPU_COUNTERS 1176 * jobs. 1177 * @system_time: gpu timestamp 1178 * @cycle_counter: gpu cycle count 1179 * @sec: cpu time(sec) 1180 * @usec: cpu time(usec) 1181 * @padding: padding 1182 * 1183 * This structure is stored into the memory pointed to by the @jc field 1184 * of &struct base_jd_atom. 1185 * 1186 * It must not occupy the same CPU cache line(s) as any neighboring data. 1187 * This is to avoid cases where access to pages containing the structure 1188 * is shared between cached and un-cached memory regions, which would 1189 * cause memory corruption. 1190 */ 1191 1192 struct base_dump_cpu_gpu_counters { 1193 __u64 system_time; 1194 __u64 cycle_counter; 1195 __u64 sec; 1196 __u32 usec; 1197 __u8 padding[36]; 1198 }; 1199 1200 #endif /* _UAPI_BASE_JM_KERNEL_H_ */ 1201