| /third_party/skia/third_party/externals/swiftshader/third_party/SPIRV-Tools/utils/vscode/src/lsp/protocol/ |
| D | log.go | 116 const eor = "\r\n\r\n\r\n" const
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| /third_party/spirv-tools/utils/vscode/src/lsp/protocol/ |
| D | log.go | 116 const eor = "\r\n\r\n\r\n" const
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| /third_party/skia/third_party/externals/spirv-tools/utils/vscode/src/lsp/protocol/ |
| D | log.go | 116 const eor = "\r\n\r\n\r\n" const
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| /third_party/skia/third_party/externals/icu/source/common/ |
| D | ubidi.cpp | 2127 DirProp sor, DirProp eor) { in resolveImplicitLevels()
2750 DirProp sor, eor; in ubidi_setPara() local
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| /third_party/node/deps/icu-small/source/common/ |
| D | ubidi.cpp | 2127 DirProp sor, DirProp eor) { in resolveImplicitLevels()
2750 DirProp sor, eor; in ubidi_setPara() local
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| /third_party/icu/icu4c/source/common/ |
| D | ubidi.cpp | 2127 DirProp sor, DirProp eor) { in resolveImplicitLevels()
2750 DirProp sor, eor; in ubidi_setPara() local
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| /third_party/node/deps/v8/src/regexp/arm/ |
| D | regexp-macro-assembler-arm.cc | 573 __ eor(r0, current_character(), Operand(0x01)); in CheckSpecialCharacterClass() local
590 __ eor(r0, current_character(), Operand(0x01)); in CheckSpecialCharacterClass() local
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| /third_party/icu/icu4j/main/classes/core/src/com/ibm/icu/text/ |
| D | Bidi.java | 3403 private void resolveImplicitLevels(int start, int limit, short sor, short eor) in resolveImplicitLevels()
4162 short sor, eor; in setPara() local
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| /third_party/icu/ohos_icu4j/src/main/java/ohos/global/icu/text/ |
| D | Bidi.java | 3369 private void resolveImplicitLevels(int start, int limit, short sor, short eor) in resolveImplicitLevels()
4125 short sor, eor; in setPara() local
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| /third_party/vixl/test/aarch64/ |
| D | test-api-movprfx-aarch64.cc | 151 __ eor(z19.VnB(), p6.Merging(), z19.VnB(), z19.VnB()); in TEST() local
731 __ eor(z2.VnB(), p6.Merging(), z2.VnB(), z26.VnB()); in TEST() local
1125 __ eor(z3.VnS(), z3.VnS(), 4); in TEST() local
1422 __ eor(z4.VnD(), p0.Merging(), z4.VnD(), z10.VnD()); in TEST() local
1425 __ eor(z15.VnH(), z15.VnH(), 4); in TEST() local
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| D | test-trace-aarch64.cc | 147 __ eor(w19, w20, w21); in GenerateTestSequenceBase() local
148 __ eor(x22, x23, x24); in GenerateTestSequenceBase() local
781 __ eor(v29.V16B(), v25.V16B(), v3.V16B()); in GenerateTestSequenceNEON() local
782 __ eor(v3.V8B(), v16.V8B(), v28.V8B()); in GenerateTestSequenceNEON() local
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| D | test-assembler-aarch64.cc | 895 TEST(eor) { in TEST() argument
7351 __ eor(xzr, x0, x5); in TEST() local
7352 __ eor(xzr, x5, xzr); in TEST() local
7353 __ eor(xzr, xzr, x5); in TEST() local
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| /third_party/vixl/test/aarch32/ |
| D | test-assembler-aarch32.cc | 686 __ eor(r5, r2, r3); // Ensure that r2, r3 and r4 are identical. in TEST() local
687 __ eor(r6, r2, r4); in TEST() local
698 __ eor(r1, r1, r2); in TEST() local
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| /third_party/vixl/src/aarch64/ |
| D | assembler-sve-aarch64.cc | 115 void Assembler::eor(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in eor() function in vixl::aarch64::Assembler
148 void Assembler::eor(const ZRegister& zd, in eor() function in vixl::aarch64::Assembler
2382 void Assembler::eor(const ZRegister& zd, in eor() function in vixl::aarch64::Assembler
6141 void Assembler::eor(const PRegisterWithLaneSize& pd, in eor() function in vixl::aarch64::Assembler
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| D | assembler-aarch64.cc | 628 void Assembler::eor(const Register& rd, in eor() function in vixl::aarch64::Assembler
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| D | logic-aarch64.cc | 1048 LogicVRegister Simulator::eor(VectorFormat vform, in eor() function in vixl::aarch64::Simulator
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| /third_party/node/deps/v8/src/codegen/arm/ |
| D | assembler-arm.cc | 1546 void Assembler::eor(Register dst, Register src1, const Operand& src2, SBit s, in eor() function in v8::internal::Assembler
1551 void Assembler::eor(Register dst, Register src1, Register src2, SBit s, in eor() function in v8::internal::Assembler
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| /third_party/vixl/benchmarks/aarch32/ |
| D | asm-disasm-speed-test.cc | 260 __ eor(r1, r6, 0x1); in Generate_1() local
6822 __ eor(r1, r5, 0x1); in Generate_52() local
7097 __ eor(r1, r5, 0x1); in Generate_54() local
7372 __ eor(r1, r5, 0x1); in Generate_56() local
7902 __ eor(r1, r5, 0x1); in Generate_60() local
8284 __ eor(r1, r7, 0x1); in Generate_63() local
8692 __ eor(r1, fp, 0x1); in Generate_66() local
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| /third_party/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2209 void eor(Register rd, Register rn, const Operand& operand) { in eor() function
2212 void eor(Condition cond, Register rd, Register rn, const Operand& operand) { in eor() function
2215 void eor(EncodingSize size, in eor() function
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| /third_party/node/deps/v8/src/compiler/backend/arm/ |
| D | code-generator-arm.cc | 1124 __ eor(i.OutputRegister(), i.InputRegister(0), i.InputOperand2(1), in AssembleArchInstruction() local
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| /third_party/python/Lib/test/ |
| D | test_socket.py | 2763 def checkFlags(self, flags, eor=None, checkset=0, checkunset=0, ignore=0): argument
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| /third_party/node/deps/v8/src/builtins/arm/ |
| D | builtins-arm.cc | 2967 __ eor(result_reg, result_reg, Operand(double_high, ASR, 31)); in Generate_DoubleToI() local
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | assembler-arm64.cc | 943 void Assembler::eor(const Register& rd, const Register& rn, in eor() function in v8::internal::Assembler
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 1527 void AssemblerARM32::eor(const Operand *OpRd, const Operand *OpRn, in eor() function in Ice::ARM32::AssemblerARM32
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| /third_party/node/deps/v8/src/execution/arm64/ |
| D | simulator-logic-arm64.cc | 1021 LogicVRegister Simulator::eor(VectorFormat vform, LogicVRegister dst, in eor() function in v8::internal::Simulator
|