| /third_party/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 272 __ rbit(w12, w13); in GenerateTestSequenceBase() local
273 __ rbit(x14, x15); in GenerateTestSequenceBase() local
1326 __ rbit(v22.V16B(), v15.V16B()); in GenerateTestSequenceNEON() local
1327 __ rbit(v30.V8B(), v3.V8B()); in GenerateTestSequenceNEON() local
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| D | test-api-movprfx-aarch64.cc | 217 __ rbit(z17.VnH(), p1.Merging(), z17.VnH()); in TEST() local
798 __ rbit(z25.VnS(), p2.Merging(), z21.VnS()); in TEST() local
1519 __ rbit(z13.VnH(), p2.Merging(), z1.VnH()); in TEST() local
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | assembler-arm64.cc | 1167 void Assembler::rbit(const Register& rd, const Register& rn) { in rbit() function in v8::internal::Assembler
3474 void Assembler::rbit(const VRegister& vd, const VRegister& vn) { in rbit() function in v8::internal::Assembler
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| /third_party/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 1011 void Assembler::rbit(const Register& rd, const Register& rn) { in rbit() function in vixl::aarch64::Assembler
4454 void Assembler::rbit(const VRegister& vd, const VRegister& vn) { in rbit() function in vixl::aarch64::Assembler
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| D | assembler-sve-aarch64.cc | 5868 void Assembler::rbit(const ZRegister& zd, in rbit() function in vixl::aarch64::Assembler
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| D | logic-aarch64.cc | 2333 LogicVRegister Simulator::rbit(VectorFormat vform, in rbit() function in vixl::aarch64::Simulator
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| /third_party/node/deps/v8/src/compiler/backend/arm/ |
| D | code-generator-arm.cc | 1193 __ rbit(i.OutputRegister(), i.InputRegister(0)); in AssembleArchInstruction() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 2135 void AssemblerARM32::rbit(const Operand *OpRd, const Operand *OpRm, in rbit() function in Ice::ARM32::AssemblerARM32
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 5997 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0)); in LowerCTTZ() local
7825 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, MVT::i32, cast); in LowerVECTOR_SHUFFLE_i1() local
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| /third_party/node/deps/v8/src/codegen/arm/ |
| D | assembler-arm.cc | 2039 void Assembler::rbit(Register dst, Register src, Condition cond) { in rbit() function in v8::internal::Assembler
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| /third_party/node/deps/v8/src/execution/arm64/ |
| D | simulator-logic-arm64.cc | 1876 LogicVRegister Simulator::rbit(VectorFormat vform, LogicVRegister dst, in rbit() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2863 void rbit(Register rd, Register rm) { rbit(al, rd, rm); } in rbit() function
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| D | assembler-aarch32.cc | 8841 void Assembler::rbit(Condition cond, Register rd, Register rm) { in rbit() function in vixl::aarch32::Assembler
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| D | disasm-aarch32.cc | 2255 void Disassembler::rbit(Condition cond, Register rd, Register rm) { in rbit() function in vixl::aarch32::Disassembler
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