| /third_party/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 632 void Adr(Condition cond, Register rd, RawLiteral* literal) { in Assembler()
655 void Adr(Register rd, RawLiteral* literal) { Adr(al, rd, literal); } in Assembler()
812 void Vldr(Condition cond, DataType dt, DRegister rd, RawLiteral* literal) { in Assembler()
835 void Vldr(DataType dt, DRegister rd, RawLiteral* literal) { in Assembler()
838 void Vldr(Condition cond, DRegister rd, RawLiteral* literal) { in Assembler()
841 void Vldr(DRegister rd, RawLiteral* literal) { in Assembler()
845 void Vldr(Condition cond, DataType dt, SRegister rd, RawLiteral* literal) { in Assembler()
868 void Vldr(DataType dt, SRegister rd, RawLiteral* literal) { in Assembler()
871 void Vldr(Condition cond, SRegister rd, RawLiteral* literal) { in Assembler()
874 void Vldr(SRegister rd, RawLiteral* literal) { in Assembler()
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| D | disasm-aarch32.cc | 1129 Register rd, in adc()
1143 Register rd, in adcs()
1157 Register rd, in add()
1169 void Disassembler::add(Condition cond, Register rd, const Operand& operand) { in add()
1177 Register rd, in adds()
1189 void Disassembler::adds(Register rd, const Operand& operand) { in adds()
1195 Register rd, in addw()
1209 Register rd, in adr()
1219 Register rd, in and_()
1233 Register rd, in ands()
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| D | assembler-aarch32.h | 1891 void adc(Register rd, Register rn, const Operand& operand) { in adc()
1894 void adc(Condition cond, Register rd, Register rn, const Operand& operand) { in adc()
1898 Register rd, in adc()
1909 void adcs(Register rd, Register rn, const Operand& operand) { in adcs()
1912 void adcs(Condition cond, Register rd, Register rn, const Operand& operand) { in adcs()
1916 Register rd, in adcs()
1927 void add(Register rd, Register rn, const Operand& operand) { in add()
1930 void add(Condition cond, Register rd, Register rn, const Operand& operand) { in add()
1934 Register rd, in add()
1941 void add(Register rd, const Operand& operand) { add(al, rd, operand); } in add()
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| D | assembler-aarch32.cc | 1925 Register rd, in adc()
2013 Register rd, in adcs()
2101 Register rd, in add()
2316 void Assembler::add(Condition cond, Register rd, const Operand& operand) { in add()
2350 Register rd, in adds()
2485 void Assembler::adds(Register rd, const Operand& operand) { in adds()
2503 Register rd, in addw()
2540 Register rd, in adr()
2665 Register rd, in adr_info()
2699 Register rd, in and_()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | macro-assembler-arm64-inl.h | 24 void TurboAssembler::And(const Register& rd, const Register& rn, in And()
31 void TurboAssembler::Ands(const Register& rd, const Register& rn, in Ands()
43 void TurboAssembler::Bic(const Register& rd, const Register& rn, in Bic()
50 void MacroAssembler::Bics(const Register& rd, const Register& rn, in Bics()
57 void TurboAssembler::Orr(const Register& rd, const Register& rn, in Orr()
64 void TurboAssembler::Orn(const Register& rd, const Register& rn, in Orn()
71 void TurboAssembler::Eor(const Register& rd, const Register& rn, in Eor()
78 void TurboAssembler::Eon(const Register& rd, const Register& rn, in Eon()
114 void TurboAssembler::Add(const Register& rd, const Register& rn, in Add()
125 void TurboAssembler::Adds(const Register& rd, const Register& rn, in Adds()
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| D | assembler-arm64.h | 603 void bfi(const Register& rd, const Register& rn, int lsb, int width) { in bfi()
610 void bfxil(const Register& rd, const Register& rn, int lsb, int width) { in bfxil()
618 void asr(const Register& rd, const Register& rn, int shift) { in asr()
624 void sbfiz(const Register& rd, const Register& rn, int lsb, int width) { in sbfiz()
631 void sbfx(const Register& rd, const Register& rn, int lsb, int width) { in sbfx()
638 void sxtb(const Register& rd, const Register& rn) { sbfm(rd, rn, 0, 7); } in sxtb()
641 void sxth(const Register& rd, const Register& rn) { sbfm(rd, rn, 0, 15); } in sxth()
644 void sxtw(const Register& rd, const Register& rn) { sbfm(rd, rn, 0, 31); } in sxtw()
648 void lsl(const Register& rd, const Register& rn, int shift) { in lsl()
655 void lsr(const Register& rd, const Register& rn, int shift) { in lsr()
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| D | assembler-arm64.cc | 824 void Assembler::adr(const Register& rd, int imm21) { in adr()
829 void Assembler::adr(const Register& rd, Label* label) { in adr()
838 void Assembler::add(const Register& rd, const Register& rn, in add()
843 void Assembler::adds(const Register& rd, const Register& rn, in adds()
853 void Assembler::sub(const Register& rd, const Register& rn, in sub()
858 void Assembler::subs(const Register& rd, const Register& rn, in subs()
868 void Assembler::neg(const Register& rd, const Operand& operand) { in neg()
873 void Assembler::negs(const Register& rd, const Operand& operand) { in negs()
878 void Assembler::adc(const Register& rd, const Register& rn, in adc()
883 void Assembler::adcs(const Register& rd, const Register& rn, in adcs()
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| /third_party/mbedtls/library/ |
| D | mps_reader.c | 70 mbedtls_mps_reader const *rd) in mps_reader_is_accumulating()
82 mbedtls_mps_reader const *rd) in mps_reader_is_producing()
89 mbedtls_mps_reader const *rd) in mps_reader_is_consuming()
95 mbedtls_mps_reader const *rd) in mps_reader_get_fragment_offset()
109 mbedtls_mps_reader const *rd) in mps_reader_serving_from_accumulator()
119 static inline void mps_reader_zero(mbedtls_mps_reader *rd) in mps_reader_zero()
140 int mbedtls_mps_reader_init(mbedtls_mps_reader *rd, in mbedtls_mps_reader_init()
153 int mbedtls_mps_reader_free(mbedtls_mps_reader *rd) in mbedtls_mps_reader_free()
160 int mbedtls_mps_reader_feed(mbedtls_mps_reader *rd, in mbedtls_mps_reader_feed()
229 int mbedtls_mps_reader_get(mbedtls_mps_reader *rd, in mbedtls_mps_reader_get()
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| /third_party/node/deps/v8/src/codegen/loong64/ |
| D | assembler-loong64.cc | 363 bool Assembler::IsMov(Instr instr, Register rd, Register rj) { in IsMov()
370 bool Assembler::IsPcAddi(Instr instr, Register rd, int32_t si20) { in IsPcAddi()
704 void Assembler::GenBJ(Opcode opcode, Register rj, Register rd, int32_t si16) { in GenBJ()
721 FPURegister fj, FPURegister rd) { in GenSel()
728 void Assembler::GenRegister(Opcode opcode, Register rj, Register rd, in GenRegister()
748 void Assembler::GenRegister(Opcode opcode, FPURegister fj, Register rd) { in GenRegister()
761 void Assembler::GenRegister(Opcode opcode, FPUControlRegister fj, Register rd) { in GenRegister()
785 void Assembler::GenRegister(Opcode opcode, CFRegister cj, Register rd) { in GenRegister()
792 Register rd) { in GenRegister()
820 Register rd) { in GenImm()
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| D | macro-assembler-loong64.cc | 343 void TurboAssembler::Add_w(Register rd, Register rj, const Operand& rk) { in CallRecordWriteStub()
360 void TurboAssembler::Add_d(Register rd, Register rj, const Operand& rk) { in CallRecordWriteStub()
377 void TurboAssembler::Sub_w(Register rd, Register rj, const Operand& rk) { in CallRecordWriteStub()
402 void TurboAssembler::Sub_d(Register rd, Register rj, const Operand& rk) { in CallRecordWriteStub()
429 void TurboAssembler::Mul_w(Register rd, Register rj, const Operand& rk) { in CallRecordWriteStub()
442 void TurboAssembler::Mulh_w(Register rd, Register rj, const Operand& rk) { in CallRecordWriteStub()
455 void TurboAssembler::Mulh_wu(Register rd, Register rj, const Operand& rk) { in CallRecordWriteStub()
468 void TurboAssembler::Mul_d(Register rd, Register rj, const Operand& rk) { in CallRecordWriteStub()
481 void TurboAssembler::Mulh_d(Register rd, Register rj, const Operand& rk) { in CallRecordWriteStub()
494 void TurboAssembler::Div_w(Register rd, Register rj, const Operand& rk) { in CallRecordWriteStub()
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| /third_party/node/deps/v8/src/codegen/riscv64/ |
| D | assembler-riscv64.cc | 818 Register rd, Register rs1, Register rs2) { in GenInstrR()
828 FPURegister rd, FPURegister rs1, FPURegister rs2) { in GenInstrR()
838 Register rd, FPURegister rs1, Register rs2) { in GenInstrR()
848 FPURegister rd, Register rs1, Register rs2) { in GenInstrR()
858 FPURegister rd, FPURegister rs1, Register rs2) { in GenInstrR()
868 Register rd, FPURegister rs1, FPURegister rs2) { in GenInstrR()
877 void Assembler::GenInstrR4(uint8_t funct2, Opcode opcode, Register rd, in GenInstrR4()
888 void Assembler::GenInstrR4(uint8_t funct2, Opcode opcode, FPURegister rd, in GenInstrR4()
900 uint8_t funct3, Register rd, Register rs1, in GenInstrRAtomic()
910 void Assembler::GenInstrRFrm(uint8_t funct7, Opcode opcode, Register rd, in GenInstrRFrm()
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| D | assembler-riscv64.h | 1062 void mv(Register rd, Register rs) { addi(rd, rs, 0); } in mv()
1063 void not_(Register rd, Register rs) { xori(rd, rs, -1); } in not_()
1064 void neg(Register rd, Register rs) { sub(rd, zero_reg, rs); } in neg()
1065 void negw(Register rd, Register rs) { subw(rd, zero_reg, rs); } in negw()
1066 void sext_w(Register rd, Register rs) { addiw(rd, rs, 0); } in sext_w()
1067 void seqz(Register rd, Register rs) { sltiu(rd, rs, 1); } in seqz()
1068 void snez(Register rd, Register rs) { sltu(rd, zero_reg, rs); } in snez()
1069 void sltz(Register rd, Register rs) { slt(rd, rs, zero_reg); } in sltz()
1070 void sgtz(Register rd, Register rs) { slt(rd, zero_reg, rs); } in sgtz()
1072 void fmv_s(FPURegister rd, FPURegister rs) { fsgnj_s(rd, rs, rs); } in fmv_s()
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| D | macro-assembler-riscv64.cc | 340 void TurboAssembler::Add32(Register rd, Register rs, const Operand& rt) { in Add32()
370 void TurboAssembler::Add64(Register rd, Register rs, const Operand& rt) { in Add64()
409 void TurboAssembler::Sub32(Register rd, Register rs, const Operand& rt) { in Sub32()
451 void TurboAssembler::Sub64(Register rd, Register rs, const Operand& rt) { in Sub64()
500 void TurboAssembler::Mul32(Register rd, Register rs, const Operand& rt) { in Mul32()
512 void TurboAssembler::Mulh32(Register rd, Register rs, const Operand& rt) { in Mulh32()
525 void TurboAssembler::Mulhu32(Register rd, Register rs, const Operand& rt, in Mulhu32()
537 void TurboAssembler::Mul64(Register rd, Register rs, const Operand& rt) { in Mul64()
549 void TurboAssembler::Mulh64(Register rd, Register rs, const Operand& rt) { in Mulh64()
573 void TurboAssembler::Mod32(Register rd, Register rs, const Operand& rt) { in Mod32()
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| /third_party/openssl/crypto/ |
| D | mips_arch.h | 27 # define mflo(rd,rs,rt) dmulu rd,rs,rt argument
28 # define mfhi(rd,rs,rt) dmuhu rd,rs,rt argument
31 # define mflo(rd,rs,rt) mulu rd,rs,rt argument
32 # define mfhi(rd,rs,rt) muhu rd,rs,rt argument
36 # define mflo(rd,rs,rt) mflo rd argument
37 # define mfhi(rd,rs,rt) mfhi rd argument
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| /third_party/node/deps/openssl/openssl/crypto/ |
| D | mips_arch.h | 27 # define mflo(rd,rs,rt) dmulu rd,rs,rt argument
28 # define mfhi(rd,rs,rt) dmuhu rd,rs,rt argument
31 # define mflo(rd,rs,rt) mulu rd,rs,rt argument
32 # define mfhi(rd,rs,rt) muhu rd,rs,rt argument
36 # define mflo(rd,rs,rt) mflo rd argument
37 # define mfhi(rd,rs,rt) mfhi rd argument
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| /third_party/pulseaudio/src/modules/ |
| D | restart-module.c | 46 pa_restart_data *rd = userdata; in call_init() local
64 pa_restart_data *rd = userdata; in defer_callback() local
75 static void do_reinit(pa_mainloop_api *mainloop, pa_restart_data *rd) { in do_reinit()
91 pa_restart_data *rd; in pa_restart_module_reinit() local
114 void pa_restart_free(pa_restart_data *rd) { in pa_restart_free()
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| D | assembler-mips64.cc | 542 bool Assembler::IsMov(Instr instr, Register rd, Register rs) { in IsMov()
602 uint32_t rd = GetRd(instr); in IsNop() local
1068 Register rd, uint16_t sa, in GenInstrRegister()
1698 void Assembler::jalr(Register rs, Register rd) { in jalr()
1719 void Assembler::addu(Register rd, Register rs, Register rt) { in addu()
1723 void Assembler::addiu(Register rd, Register rs, int32_t j) { in addiu()
1727 void Assembler::subu(Register rd, Register rs, Register rt) { in subu()
1731 void Assembler::mul(Register rd, Register rs, Register rt) { in mul()
1739 void Assembler::muh(Register rd, Register rs, Register rt) { in muh()
1744 void Assembler::mulu(Register rd, Register rs, Register rt) { in mulu()
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| D | macro-assembler-mips64.cc | 338 void TurboAssembler::Addu(Register rd, Register rs, const Operand& rt) { in CallRecordWriteStub()
355 void TurboAssembler::Daddu(Register rd, Register rs, const Operand& rt) { in CallRecordWriteStub()
372 void TurboAssembler::Subu(Register rd, Register rs, const Operand& rt) { in CallRecordWriteStub()
398 void TurboAssembler::Dsubu(Register rd, Register rs, const Operand& rt) { in CallRecordWriteStub()
426 void TurboAssembler::Mul(Register rd, Register rs, const Operand& rt) { in CallRecordWriteStub()
439 void TurboAssembler::Mulh(Register rd, Register rs, const Operand& rt) { in CallRecordWriteStub()
462 void TurboAssembler::Mulhu(Register rd, Register rs, const Operand& rt) { in CallRecordWriteStub()
485 void TurboAssembler::Dmul(Register rd, Register rs, const Operand& rt) { in CallRecordWriteStub()
508 void TurboAssembler::Dmulh(Register rd, Register rs, const Operand& rt) { in CallRecordWriteStub()
619 void TurboAssembler::Mod(Register rd, Register rs, const Operand& rt) { in CallRecordWriteStub()
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| /third_party/icu/icu4c/source/test/cintltst/ |
| D | uregiontest.c | 366 const KnownRegion * rd; in TestKnownRegions() local
393 const KnownRegion * rd; in TestGetContainedRegions() local
474 const KnownRegion * rd; in TestGetContainedRegionsWithType() local
503 const KnownRegion * rd; in TestGetContainingRegion() local
527 const KnownRegion * rd; in TestGetContainingRegionWithType() local
604 const KnownRegion * rd; in TestContains() local
|
| /third_party/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 782 void bfi(const Register& rd, in bfi()
795 void bfxil(const Register& rd, in bfxil()
805 void bfc(const Register& rd, unsigned lsb, unsigned width) { in bfc()
812 void asr(const Register& rd, const Register& rn, unsigned shift) { in asr()
818 void sbfiz(const Register& rd, in sbfiz()
831 void sbfx(const Register& rd, in sbfx()
841 void sxtb(const Register& rd, const Register& rn) { sbfm(rd, rn, 0, 7); } in sxtb()
844 void sxth(const Register& rd, const Register& rn) { sbfm(rd, rn, 0, 15); } in sxth()
847 void sxtw(const Register& rd, const Register& rn) { sbfm(rd, rn, 0, 31); } in sxtw()
852 void lsl(const Register& rd, const Register& rn, unsigned shift) { in lsl()
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| D | macro-assembler-aarch64.cc | 491 const Register& rd, in Emit()
801 void MacroAssembler::And(const Register& rd, in Emit()
809 void MacroAssembler::Ands(const Register& rd, in Emit()
823 void MacroAssembler::Bic(const Register& rd, in Emit()
831 void MacroAssembler::Bics(const Register& rd, in Emit()
839 void MacroAssembler::Orr(const Register& rd, in Emit()
847 void MacroAssembler::Orn(const Register& rd, in Emit()
855 void MacroAssembler::Eor(const Register& rd, in Emit()
863 void MacroAssembler::Eon(const Register& rd, in Emit()
871 void MacroAssembler::LogicalMacro(const Register& rd, in Emit()
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| /third_party/node/deps/v8/src/codegen/mips/ |
| D | assembler-mips.cc | 616 bool Assembler::IsAddu(Instr instr, Register rd, Register rs, Register rt) { in IsAddu()
630 bool Assembler::IsMov(Instr instr, Register rd, Register rs) { in IsMov()
650 uint32_t rd = GetRd(instr); in IsNop() local
1139 Register rd, uint16_t sa, in GenInstrRegister()
1760 void Assembler::jalr(Register rs, Register rd) { in jalr()
1781 void Assembler::addu(Register rd, Register rs, Register rt) { in addu()
1785 void Assembler::addiu(Register rd, Register rs, int32_t j) { in addiu()
1789 void Assembler::subu(Register rd, Register rs, Register rt) { in subu()
1793 void Assembler::mul(Register rd, Register rs, Register rt) { in mul()
1801 void Assembler::mulu(Register rd, Register rs, Register rt) { in mulu()
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| /third_party/node/deps/openssl/config/archs/linux64-mips64/asm_avx2/crypto/bn/ |
| D | bn-mips.S | 5 # define mfqt(rd,rs,rt) ddivu rd,rs,rt argument
6 # define mfrm(rd,rs,rt) dmodu rd,rs,rt argument
9 # define mfqt(rd,rs,rt) divu rd,rs,rt argument
10 # define mfrm(rd,rs,rt) modu rd,rs,rt argument
13 # define mfqt(rd,rs,rt) mflo rd argument
14 # define mfrm(rd,rs,rt) mfhi rd argument
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| /third_party/node/deps/openssl/config/archs/linux64-mips64/asm/crypto/bn/ |
| D | bn-mips.S | 5 # define mfqt(rd,rs,rt) ddivu rd,rs,rt argument
6 # define mfrm(rd,rs,rt) dmodu rd,rs,rt argument
9 # define mfqt(rd,rs,rt) divu rd,rs,rt argument
10 # define mfrm(rd,rs,rt) modu rd,rs,rt argument
13 # define mfqt(rd,rs,rt) mflo rd argument
14 # define mfrm(rd,rs,rt) mfhi rd argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/DartARM32/ |
| D | assembler_arm.cc | 153 void Assembler::EmitShiftImmediate(Condition cond, Shift opcode, Register rd, in EmitShiftImmediate()
165 void Assembler::EmitShiftRegister(Condition cond, Shift opcode, Register rd, in EmitShiftRegister()
230 void Assembler::sbc(Register rd, Register rn, Operand o, Condition cond) { in sbc()
234 void Assembler::sbcs(Register rd, Register rn, Operand o, Condition cond) { in sbcs()
282 void Assembler::movs(Register rd, Operand o, Condition cond) { in movs()
367 void Assembler::muls(Register rd, Register rn, Register rm, Condition cond) { in muls()
482 void Assembler::ldrh(Register rd, Address ad, Condition cond) { in ldrh()
486 void Assembler::strh(Register rd, Address ad, Condition cond) { in strh()
490 void Assembler::ldrsb(Register rd, Address ad, Condition cond) { in ldrsb()
494 void Assembler::ldrsh(Register rd, Address ad, Condition cond) { in ldrsh()
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