| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_build_pm4.h | 39 #define SI_CHECK_SHADOWED_REGS(reg_offset, count) argument
308 static inline void radeon_set_sh_reg_func(struct radeon_cmdbuf *cs, unsigned reg_offset, in radeon_set_sh_reg_func()
316 static inline void radeon_set_sh_reg_idx3_func(struct radeon_cmdbuf *cs, unsigned reg_offset, in radeon_set_sh_reg_idx3_func()
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| /third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_winsys.c | 125 radv_amdgpu_winsys_read_registers(struct radeon_winsys *rws, unsigned reg_offset, in radv_amdgpu_winsys_read_registers()
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| /third_party/mesa3d/src/imagination/rogue/ |
| D | rogue_regalloc.c | 269 size_t reg_offset = reg_data->offset; in rogue_ra_alloc() local
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_vec4_visitor.cpp | 1070 src_reg *reladdr, int reg_offset) in get_scratch_offset()
1119 int reg_offset = base_offset + orig_src.offset / REG_SIZE; in emit_scratch_read() local
1148 int reg_offset = base_offset + inst->dst.offset / REG_SIZE; in emit_scratch_write() local
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| D | brw_ir_vec4.h | 232 reg_offset(const backend_reg &r) in reg_offset() function
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| D | brw_ir_fs.h | 181 reg_offset(const fs_reg &r) in reg_offset() function
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| D | brw_fs.cpp | 2255 unsigned reg_offset = 0; in split_virtual_grfs() local
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_shadowed_regs.c | 4031 unsigned reg_offset = R_02835C_PA_SC_TILE_STEERING_OVERRIDE; in ac_emulate_clear_state() local
4051 unsigned reg_offset, unsigned count) in ac_check_shadowed_regs()
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| D | ac_shader_util.c | 792 void ac_set_reg_cu_en(void *cs, unsigned reg_offset, uint32_t value, uint32_t clear_mask, in ac_set_reg_cu_en() argument
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| D | ac_debug.c | 241 static void ac_parse_set_reg_packet(FILE *f, unsigned count, unsigned reg_offset, in ac_parse_set_reg_packet()
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| /third_party/mesa3d/src/gallium/drivers/r600/ |
| D | eg_debug.c | 134 unsigned reg_offset) in ac_parse_set_reg_packet()
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| /third_party/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| D | amdgpu_winsys.c | 290 unsigned reg_offset, in amdgpu_read_registers()
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| /third_party/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_winsys.c | 731 unsigned reg_offset, in radeon_read_registers()
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| /third_party/ffmpeg/libavcodec/ |
| D | atrac3plusdsp.c | 131 int invert_phase, int reg_offset, float *out) in waves_synth()
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| /third_party/elfutils/libdw/ |
| D | cfi.h | 127 reg_offset, /* DW_CFA_offset_extended et al */ enumerator
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| /third_party/mesa3d/src/gallium/drivers/lima/ir/gp/ |
| D | regalloc.c | 397 unsigned reg_offset = ctx->alloc_start++; in find_free_value_reg() local
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| /third_party/mesa3d/src/panfrost/midgard/ |
| D | midgard_ra.c | 45 offset_swizzle(unsigned *swizzle, unsigned reg_offset, unsigned srcshift, unsigned dstshift, unsign… in offset_swizzle()
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| /third_party/mesa3d/src/intel/tools/ |
| D | aubinator_viewer.cpp | 109 handle_reg_write(void *user_data, uint32_t reg_offset, uint32_t reg_value) in handle_reg_write()
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| /third_party/mesa3d/src/gallium/drivers/r600/sb/ |
| D | sb_ir.h | 600 int reg_offset = select.sel() - array->base_gpr.sel(); in get_final_gpr() local
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| /third_party/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.cc | 1806 Register reg_offset = mem_op.GetRegisterOffset(); in Emit() local
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_cmd_buffer.c | 2429 unsigned reg_offset = 0, reg_count = 0; in radv_load_ds_clear_metadata() local
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| /third_party/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 12500 int64_t reg_offset = INT64_C(0x1087654321); in TEST() local
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